SCIENCE AND ENGINEERING NEWS
Fayetteville, AR — Research currently underway at the University of Arkansas may have a billion-dollar impact on the semiconductor industry. Scott Mason, assistant professor of industrial engineering, has received a grant from Semiconductor Research Corporation (SRC) for work that may revolutionize the fabrication of semiconductor wafers.
Mason is working with a consortium comprising the University of Arkansas, Arizona State University and the University of Wuerzberg, Germany. The grant totals $825,000 and the U of A will receive $225,000.
“This program expands the University’s expertise to the front end of wafer fabrication,” Mason said. “We already have a well-known program on the back end — assembly, testing and packaging — with our microelectronics and materials researchers, but industry is hungry for industrial engineers with a background in semiconductors.”
In addition to creating a research program that will employ several M.S. and Ph.D. students, Mason is developing a graduate-level course in semiconductor fabrication that will be taught in the fall 2001 semester.
Wafer fabrication refers to the process by which integrated circuits (ICs) are produced on silicon wafers. Demand for ICs has increased dramatically in recent years as the applications for them have increased. ICs are used in products ranging from industrial processing equipment to consumer electronics and appliances. IC manufacturers, such as Advanced Micro Devices and Intel, typically receive more orders than they can produce.
The SRC grant funds research to improve the scheduling and efficiency in the IC manufacturing process. Since IC manufacturers often deliver products late, manufacturers that can deliver the product on time will have a competitive advantage in the marketplace.
“If we can improve efficiency and throughput by only one wafer a day, it will have a significant effect,” Mason explained. “A typical wafer fabrication facility represents a $2 billion investment. Each wafer can be worth $50,000 – $100,000 and they are produced in lots of 25. At any given time, the inventory in a plant could exceed $0.5 billion.”
Wafer fabrication represents a particularly complex scheduling problem because wafers do not move through the plant in a linear fashion.
Depending on the configuration of the wafer, it may pass a point in the cycle, then go back to a previous tool, and this process may be repeated several times. Other complications can be caused by a tool breaking down or a bottleneck developing because of an overall slowing down of the process.
Currently managers typically develop a schedule for each day, but bottlenecks, breakdowns and other factors can severely distort the schedule. Recognizing and adjusting for these problems is complex and difficult.
The consortium is developing scheduling methodologies for wafer fabrication that will incorporate methods to recognize and overcome these problems. The resulting software will work with the company’s existing manufacturing software to improve workflow.
“Our goal is to make something that is actually used in industry, not to solve an academic problem,” said Mason. “Our results should make scheduling a wafer fab on a shift-by-shift basis — or even more frequently — a real possibility.”