Daresbury Laboratory Benchmarks Multi-Core Chips

By Christopher Lazou

December 16, 2005

On December 6th and 7th about 250 people attended the 16th Machine Evaluation Workshop at EPSRC Daresbury Laboratories, UK. This workshop is a leading UK national event dedicated to distributed, high performance scientific computing. The principle objective is to encourage close contact between the research communities from the Mathematics, Chemistry, Physics, Engineering and Materials Programmes of EPSRC and the major vendors of mid-range computing systems, workstations, servers, software and peripherals.

Most of the 25 presentations were from vendors, describing their own products, on topics such as hardware, compilers, graphics, storage and networking. They focused on cluster solutions, based on commodity chips, interconnect networks and associated file storage systems. An important component of the workshop is the availability of systems for benchmarking evaluation purposes.

There were exhibitions and presentations from eighteen companies, keen to promote their ready-made products including those based on AMD Opteron and the Intel Itanium 2 processor. A strong presence of AMD Opteron and Intel Bensley, early dual-core systems, as well as various models of blade products, were on display and available for demonstrations. 

Ron Bell, from the UK Atomic Weapons Establishment (AWE), started the workshop with a presentation titled: “The AWE HPC Benchmark”. This was an interesting talk in that it discussed AWE's benchmark based on workload profile characterization and projections of future user requirements. They are currently running an IBM P3 system with 1856 processors rated at 2.88 Tflop/s peak performance. The requirement is to buy a new system delivering 10 to 25 times greater performance than their current system, which translates to a system in the range of 30 to 70 Tflop/s peak performance.

The benchmark contains a combination of codes from the whole AWE user community, physicists, engineers and material scientists, weighted to reflect their workload. It measures both capacity (throughput) and capability (turnaround).

The physicists contributed plasma physics and hydrodynamic codes plus visualization. The engineers codes for solving explicit and implicit (100 MDOFs) models with as much as 30 million elements. From the Materials group, two molecular dynamics codes were used, DL-Poly from Daresbury and WARP from Sandia.

Ron went on to cogently discuss the pitfalls of benchmarking when dealing with systems of differing speeds. He gave an example of two systems A and B with system A twice as fast as B and B having twice the number of processors than A. He then presented the usual scenario where capacity can be achieved by partitioning system B into two, running both partitions in parallel giving the illusion that both systems have the same throughput.
He went on to say: “The answer is not system A, gives better turnaround times but has the same throughput. The correct answer is system A has higher throughput than system B because system B must scale further in order to achieve the required job turnaround and system B may be unable to give the required turnaround for some capability jobs. In conclusion, don't compare N-way on A with N-way on B. Adjust N so that turnaround is about the same on A and B”.

In running the AWE benchmark they found that: “There is a problem with measuring throughput of capability jobs. At modest levels of parallelism, scalability is largely unaffected by interconnect. Scalability is intrinsic to application. The ratio between systems is constant with PE count. At higher PE counts where performance turns over, relative throughput varies wildly and becomes meaningless.”

Also, it was very difficult to perform the capability test. There were very few benchmark data available, up to the turn over point. To measure the job turnaround at a point just before turn over, the best the system can do irrespective of number of PEs, became difficult. Generally, a system, scoring better on this measure would need more PEs to achieve it – so throughput was probably lower. For this reason, capacity and capability figures were presented as separate measures, with a warning about the large uncertainties on the capability figures.

Ron Bell wanted to be able to say things like: “System A has 10 percent higher throughput than system B for modestly parallel work, but system B has better scalability – so capability jobs show 20 percent higher throughput on B. If we assume half of the system will be dedicated to capability jobs, then System B gives more overall throughput”. This was not apparent from the benchmark results.

Ron Bell concluded: “The benchmark was too complex for vendors. The throughput test is not really useful as a benchmark. Multiple jobs don't usually interfere much. There was inadequate I/O on benchmark systems, but this should be excellent as an acceptance test. Capability was very difficult to quantify”.

In short, Ron Bell was saying that for large-scale applications (30 million elements), time to completion must be heavily weighted in the selection criteria of a system. Capability systems can always deliver capacity where capability is often beyond capacity systems, but capability is difficult to measure accurately as vendors do not usually have systems of that size for benchmarking.

Of course other factors often dominate the selection of large-scale systems. For example, one trade-off is price/performance; another, are perceived hidden benefits from having the same system as your collaborators. One suspects it depends on how one constructs the Total Cost of Ownership (TCO) integral. For my money, I would also include ease of use and Mean Time Between Failures (MTBF), especially with systems with tens or hundred thousand processors.

Chris Brown gave the “IBM HPC systems perspective” talk emphasizing that one size does not fit all. He explained that in addition to the IBM P5 line, IBM is exploring the low-power Cell processor technology. The speaker claimed that because IBM is a large company with a strong track record of innovation and in control of component developments, it is able to leverage these innovations across the whole design spectrum. For example, take the game processor developed from Cell technology for the large consumer market, add a couple of floating point pipes and what one has is the Blue Gene. Both the Blue Gene and the MareNostrum systems, based on the Power PC 970 FX processor, are examples of experimental technologies. IBM believes that next generation chip designs are focusing on high performance/power consumption ratios and that semiconductor power trends are driving future systems. With hundreds of thousands of processors, software tool makers will be challenged to create an easy to use development environment. I may also add, reliability, such as MTBF.

Jörg Stadler from NEC HPC Europe described the NEC SX-8 vector parallel system whose raison d'être is capability supercomputing. NEC is committed to continue to develop products at the top end of HPC using the latest technologies. Their next generation system is likely to be heterogeneous with a strong vector processing component. He also explained that they are offering total solutions to customers, from high computation to data management infrastructure, based on their super-scalar Itanium 2 system. As an example, he cited the DKRZ climate center in Germany where the computation element is delivered by the NEC SX-6 and the data management of some 220 terabytes using the NEC TX7 and Oracle. They also deliver tailor-made scalar systems in collaboration with other vendors. The 100 Tflop/s scalar system for the Tokyo Institute of Technology, where NEC is acting as the integrator, but collaborating with ClearSpeed, AMD and Sun Microsystems, was cited as an example.     

As in previous years, the Daresbury Benchmark results were of great interest. These consisted of a plethora of distributed memory benchmark results, compiled by Martyn Guest and his team from Daresbury, from many systems including the latest products from vendors using their latest two core chips. The Daresbury benchmark suite, used to obtain these results, consists of many computational chemistry kernel codes, molecular dynamics, Quantum Monte Carlo, Jacobi Solver, STREAM – measured sustainable memory bandwidth in HPC (TRIAD), the Ab Initio molecular electronic structure package, GAMESS-UK, and the parallel molecular dynamics benchmark, DL_POLY. The results from SPECfp2000, SPECInt2000 and other well-known benchmarks were also presented.

Martyn Guest gave a similar talk as previous years, this time the results were normalised against an Opteron – the AMD Opteron 852/2600 (EKO2.2) – see table below. Martyn emphasised that single processors are complex and often provide misleading results as they are almost always used in n-way nodes. If they are dual-core, use both processors; if quad-cores, use all four so that interactions of cache memory and communications are accounted in the performance measure. For example, in the case of the 32-way IBM P4 this normalizes availability of L3 cache memory, which reduces performance compared to using all L3 cache for one CPU. This applies to other vendors' products too. When more cores are added on a chip the interconnect fabric for transfer rates (bandwidth) to L3 cache need to be increased proportionately to handle the extra computational power from the extra cores. Otherwise, memory paths, if shared with the additional cores, are likely to degrade the overall system performance.

Note that the results presented below, reflect performance in computational chemistry and this does not necessarily reflect the performance of these computers in other application domains. Also, the results given are not normalized on price/performance, so no specific value-for-money comparisons are made or implied.

Looking at SPECfp 2000 relative to the HP RX5670 Itanium 2 (1.5GHz), the SGI Altix 3700 Bx2/1600-9M Itanium 2 system is 26 percent faster and the IBM e-Server P5 570/1900 is 22 percent faster, while the HP RX4640 Itanium 2/1600-9M is 29 percent faster. These systems deliver around 40 percent of their peak performance on the SPECfp 2000 metric.
The benchmark results compiled by the Daresbury team indicate that the Intel Itanium 2 systems are still the bright stars of today, but the IBM e-server P5 570/1900 is not far behind. They fare well as far as performance is concerned compared to other super-scalar chips, although one can detect a trend towards convergence. Performance of a particular chip tends to vary on different benchmarks and the version of compiler is run on, but one can see a pattern emerging. To give you a flavor of the benchmarks, here are some of the results, normalized on the AMD Opteron 852/2600 using the PathScale compiler EKO2.2 (for the Matrix-97, Chemistry Kernels, GAMES-UK and DL-POLY benchmarks):

The AMD Opteron 852/2600 (EKO2.2)     (100)
The AMD Opteron 852/2600 (PGI5.2)        (88)
The Dell PowerEdge 1850/3600 2MBL2      (72)
Sun Fire V40z 2.2GHz                                 (76)
The Bull NovaScale 4040 Itanium 2/1500     (98)
SGI Altix3700 Itanium 2/1500                      (98)
SGI Altix3700 Itanium 2/1600                    (105)
The HP RX5670 Itanium 2/1500-H              (99)
The HP RX1620 Itanium 2/1600-L             (106)
The HP RX1620 Itanium 2/1600-H             (121)
The IBM p-Series 690/1700                         (80)
The IBM e-Server p5 575/1500                    (78)
The IBM e-Server P5 570/1900                  (105)

Note that the HP compiler delivers about 15 percent improvement compared to its Linux counterpart on the HP RX1620. A similar pattern is also evident on the AMD Opteron 852/2600, when using PathScale's EKO (Ver.2.2) and the Portland Group's PGI (Ver.5.2) Fortran compilers.

A more interesting table was presented showing scaling performance when using multi-cores on a chip. In general they scaled reasonably well. There were few exceptions. One major bottleneck identified is the bandwidth imbalance from L2 to L3 cache, where the transfer rate remained as for one core, but has to deal with bandwidth requirements of two cores.

The rest of the workshop consisted of presentations from vendors, with a strong contingent from the FPGAs fraternity, Mitrion, Celoxica and Nallatech, and from users sharing their experience and presentations from a number of companies, specializing in providing tailored system solutions from commodity components on demand. Instead of buying pre-packaged products from traditional vendors, a contract is placed with a small computer integration company, such as ClusterVision or Streamline, to built a cluster from favored chips and an interconnect network, such as Gigabit Ethernet, QsNet, InfiniBand or Myrinet.

The presentations focused on cluster systems affordable by academic departments and associated organizations, which make the departmental computing environment. For example, Fiona Burgess and Michal Harasimiuk from ClearSpeed, presented their new co-processor, the CSX600, suitable for offloading compute-intense math library functions from serial CPUs. Michal claimed that: “Each CSX600 co-processor can sustain 25 Gflop/s on DGEMM, while consuming only 5 watts of power. The CSX600, now available, is a SIMD array of processors. Each PE is a VLIW processor with a multiple execution floating point adder and floating point multiplier in both 32-bit and 64-bit IEEE754 standard.

A two-chip board delivers 50 Gflop/s peak and uses 10 watts in total. It has up to one gigabyte shared DRAM for local processing. A dual CSX600 using PCI-X, 20 watts/card accelerator board gives 100 Gflop/s peak on DGEMM, BLAS, LAPACK, GROMACS, CHARMM NAND and so on. It is suitable for computation in finance, Monte Carlo and Generic math, providing transparent acceleration for packages such as MATLAB, Mathematica, NAG, Maple and entire applications in biochemistry.

There are some very positive trends in multi-core chip developments, but the workshop also had some surprises. These are too sensitive to be printed here. For those of you keen to add the latest 'gizmos' to your facilities, remember the Latin adage: “caveat emptor.” As the season of goodwill is upon us: Wishing you all, Seasons Greetings and a peaceful Happy New Year.

(Brands and names are the property of their respective owners)
Copyright: Christopher Lazou, HiPerCom Consultants, Ltd., UK., December 2005.

Subscribe to HPCwire's Weekly Update!

Be the most informed person in the room! Stay ahead of the tech trends with industy updates delivered to you every week!

Machine Learning at HPC User Forum: Drilling into Specific Use Cases

September 22, 2017

The 66th HPC User Forum held September 5-7, in Milwaukee, Wisconsin, at the elegant and historic Pfister Hotel, highlighting the 1893 Victorian décor and art of “The Grand Hotel Of The West,” contrasted nicely with Read more…

By Arno Kolster

Google Cloud Makes Good on Promise to Add Nvidia P100 GPUs

September 21, 2017

Google has taken down the notice on its cloud platform website that says Nvidia Tesla P100s are “coming soon.” That's because the search giant has announced the beta launch of the high-end P100 Nvidia Tesla GPUs on t Read more…

By George Leopold

Cray Wins $48M Supercomputer Contract from KISTI

September 21, 2017

It was a good day for Cray which won a $48 million contract from the Korea Institute of Science and Technology Information (KISTI) for a 128-rack CS500 cluster supercomputer. The new system, equipped with Intel Xeon Scal Read more…

By John Russell

HPE Extreme Performance Solutions

HPE Prepares Customers for Success with the HPC Software Portfolio

High performance computing (HPC) software is key to harnessing the full power of HPC environments. Development and management tools enable IT departments to streamline installation and maintenance of their systems as well as create, optimize, and run their HPC applications. Read more…

Adolfy Hoisie to Lead Brookhaven’s Computing for National Security Effort

September 21, 2017

Brookhaven National Laboratory announced today that Adolfy Hoisie will chair its newly formed Computing for National Security department, which is part of Brookhaven’s new Computational Science Initiative (CSI). Read more…

By John Russell

Machine Learning at HPC User Forum: Drilling into Specific Use Cases

September 22, 2017

The 66th HPC User Forum held September 5-7, in Milwaukee, Wisconsin, at the elegant and historic Pfister Hotel, highlighting the 1893 Victorian décor and art o Read more…

By Arno Kolster

Stanford University and UberCloud Achieve Breakthrough in Living Heart Simulations

September 21, 2017

Cardiac arrhythmia can be an undesirable and potentially lethal side effect of drugs. During this condition, the electrical activity of the heart turns chaotic, Read more…

By Wolfgang Gentzsch, UberCloud, and Francisco Sahli, Stanford University

PNNL’s Center for Advanced Tech Evaluation Seeks Wider HPC Community Ties

September 21, 2017

Two years ago the Department of Energy established the Center for Advanced Technology Evaluation (CENATE) at Pacific Northwest National Laboratory (PNNL). CENAT Read more…

By John Russell

Exascale Computing Project Names Doug Kothe as Director

September 20, 2017

The Department of Energy’s Exascale Computing Project (ECP) has named Doug Kothe as its new director effective October 1. He replaces Paul Messina, who is stepping down after two years to return to Argonne National Laboratory. Kothe is a 32-year veteran of DOE’s National Laboratory System. Read more…

Takeaways from the Milwaukee HPC User Forum

September 19, 2017

Milwaukee’s elegant Pfister Hotel hosted approximately 100 attendees for the 66th HPC User Forum (September 5-7, 2017). In the original home city of Pabst Blu Read more…

By Merle Giles

Kathy Yelick Charts the Promise and Progress of Exascale Science

September 15, 2017

On Friday, Sept. 8, Kathy Yelick of Lawrence Berkeley National Laboratory and the University of California, Berkeley, delivered the keynote address on “Breakthrough Science at the Exascale” at the ACM Europe Conference in Barcelona. In conjunction with her presentation, Yelick agreed to a short Q&A discussion with HPCwire. Read more…

By Tiffany Trader

DARPA Pledges Another $300 Million for Post-Moore’s Readiness

September 14, 2017

The Defense Advanced Research Projects Agency (DARPA) launched a giant funding effort to ensure the United States can sustain the pace of electronic innovation vital to both a flourishing economy and a secure military. Under the banner of the Electronics Resurgence Initiative (ERI), some $500-$800 million will be invested in post-Moore’s Law technologies. Read more…

By Tiffany Trader

IBM Breaks Ground for Complex Quantum Chemistry

September 14, 2017

IBM has reported the use of a novel algorithm to simulate BeH2 (beryllium-hydride) on a quantum computer. This is the largest molecule so far simulated on a quantum computer. The technique, which used six qubits of a seven-qubit system, is an important step forward and may suggest an approach to simulating ever larger molecules. Read more…

By John Russell

How ‘Knights Mill’ Gets Its Deep Learning Flops

June 22, 2017

Intel, the subject of much speculation regarding the delayed, rewritten or potentially canceled “Aurora” contract (the Argonne Lab part of the CORAL “ Read more…

By Tiffany Trader

Reinders: “AVX-512 May Be a Hidden Gem” in Intel Xeon Scalable Processors

June 29, 2017

Imagine if we could use vector processing on something other than just floating point problems.  Today, GPUs and CPUs work tirelessly to accelerate algorithms Read more…

By James Reinders

NERSC Scales Scientific Deep Learning to 15 Petaflops

August 28, 2017

A collaborative effort between Intel, NERSC and Stanford has delivered the first 15-petaflops deep learning software running on HPC platforms and is, according Read more…

By Rob Farber

Oracle Layoffs Reportedly Hit SPARC and Solaris Hard

September 7, 2017

Oracle’s latest layoffs have many wondering if this is the end of the line for the SPARC processor and Solaris OS development. As reported by multiple sources Read more…

By John Russell

Six Exascale PathForward Vendors Selected; DoE Providing $258M

June 15, 2017

The much-anticipated PathForward awards for hardware R&D in support of the Exascale Computing Project were announced today with six vendors selected – AMD Read more…

By John Russell

Russian Researchers Claim First Quantum-Safe Blockchain

May 25, 2017

The Russian Quantum Center today announced it has overcome the threat of quantum cryptography by creating the first quantum-safe blockchain, securing cryptocurrencies like Bitcoin, along with classified government communications and other sensitive digital transfers. Read more…

By Doug Black

Top500 Results: Latest List Trends and What’s in Store

June 19, 2017

Greetings from Frankfurt and the 2017 International Supercomputing Conference where the latest Top500 list has just been revealed. Although there were no major Read more…

By Tiffany Trader

IBM Clears Path to 5nm with Silicon Nanosheets

June 5, 2017

Two years since announcing the industry’s first 7nm node test chip, IBM and its research alliance partners GlobalFoundries and Samsung have developed a proces Read more…

By Tiffany Trader

Leading Solution Providers

Nvidia Responds to Google TPU Benchmarking

April 10, 2017

Nvidia highlights strengths of its newest GPU silicon in response to Google's report on the performance and energy advantages of its custom tensor processor. Read more…

By Tiffany Trader

Graphcore Readies Launch of 16nm Colossus-IPU Chip

July 20, 2017

A second $30 million funding round for U.K. AI chip developer Graphcore sets up the company to go to market with its “intelligent processing unit” (IPU) in Read more…

By Tiffany Trader

Google Debuts TPU v2 and will Add to Google Cloud

May 25, 2017

Not long after stirring attention in the deep learning/AI community by revealing the details of its Tensor Processing Unit (TPU), Google last week announced the Read more…

By John Russell

Google Releases Deeplearn.js to Further Democratize Machine Learning

August 17, 2017

Spreading the use of machine learning tools is one of the goals of Google’s PAIR (People + AI Research) initiative, which was introduced in early July. Last w Read more…

By John Russell

EU Funds 20 Million Euro ARM+FPGA Exascale Project

September 7, 2017

At the Barcelona Supercomputer Centre on Wednesday (Sept. 6), 16 partners gathered to launch the EuroEXA project, which invests €20 million over three-and-a-half years into exascale-focused research and development. Led by the Horizon 2020 program, EuroEXA picks up the banner of a triad of partner projects — ExaNeSt, EcoScale and ExaNoDe — building on their work... Read more…

By Tiffany Trader

Amazon Debuts New AMD-based GPU Instances for Graphics Acceleration

September 12, 2017

Last week Amazon Web Services (AWS) streaming service, AppStream 2.0, introduced a new GPU instance called Graphics Design intended to accelerate graphics. The Read more…

By John Russell

Cray Moves to Acquire the Seagate ClusterStor Line

July 28, 2017

This week Cray announced that it is picking up Seagate's ClusterStor HPC storage array business for an undisclosed sum. "In short we're effectively transitioning the bulk of the ClusterStor product line to Cray," said CEO Peter Ungaro. Read more…

By Tiffany Trader

GlobalFoundries: 7nm Chips Coming in 2018, EUV in 2019

June 13, 2017

GlobalFoundries has formally announced that its 7nm technology is ready for customer engagement with product tape outs expected for the first half of 2018. The Read more…

By Tiffany Trader

  • arrow
  • Click Here for More Headlines
  • arrow
Share This