Intel fellow and director of microprocessor research Shekhar Borkar recently sat down to discuss how Intel researchers plan to achieve new levels of microprocessor performance and power efficiency. In this article, Borkar explains how Intel researchers are confident about achieving a 10x improvement in MIPS (millions of instructions per second) per watt, and why Intel's platform approach is vital to that effort.

What is Intel's direction in microprocessor architecture over the next five to ten years?

We are continuing toward the vision of multi-core processors and platforms that we articulated a few years ago — what we called the “right-hand turn.” We started with multithreading that utilizes today's single-core hardware more efficiently. Now we are moving on to architectures where we use multiple processor cores on the die to provide higher and higher performance, as opposed to past trends of increasingly larger monolithic cores.

What makes Intel's platform approach different from other multiprocessor architectures, in terms of both processors and broader system-level technologies?

In our multi-core platforms, we have integrated a whole set of technologies to give the user the full user experience that he or she requires. Some of these are what we call the “*Ts” — a set of new technologies aimed at providing users with greater value and functionality in the platform. Our vision is that every technology in the platform should work together in harmony to give the final experience: a platform that is powerful, versatile, secure and reliable, affordable to own, and simple to manage.

Now a performance question: during the Fall '05 Intel Development Forum (IDF) Paul Otellini mentioned a 10x reduction in power and a 10x improvement in performance. Is this vision achievable, and if so, how do you intend to accomplish it?

It is absolutely achievable. In fact, Paul is articulating goals we identified five years ago, and we have already shown through our research how we will attain these goals. Now Paul is challenging us to make it a reality.

Here are the ingredients we need to get there. The first is to move away from using frequency alone to deliver performance, similar to what we are doing in Intel Centrino mobile technology. With Centrino, we don't talk frequency, but we do talk performance. We are delivering performance with the platform integration, without increasing power.

The second ingredient is multiplicity. Today we have multithreading and chip-level multiprocessing. Future processors will have multiple cores on the die. With the multi-core approach, you can increase your power and performance linearly, as opposed to the quadratic relationship between power and performance for larger monolithic processors. Therefore, multiple small cores have the potential to provide near-linear increases in performance with only linear increases in power (as opposed to quadratic increases in power with a large core).

But does this mean that power will increase with multiple cores? No. When we apply multiple processors to a problem, we can use that quadratic relationship between performance and power to our advantage. For example, a 15 percent drop in per-core performance can give us a 50 percent decrease in power usage. So in the future, we can double the number of processor cores on a die using processors that each have 15 percent lower performance than a larger monolithic processor, but we still greatly increase the overall processor performance, and we have cut power usage by 50 percent. So yes, I can get more performance while reducing power.

The third ingredient of the power/performance solution is what we call fixed function hardware. Using specialized hardware for specialized functions, you can get a lot more performance for the power. Let me give you an example. If you want to run some of the repetitive or enabling tasks like video processing, speech recognition, or network processing, what do we do today? We use general-purpose processors. These general-purpose processors are flexible. They can do anything, but at the expense of power. But in the future, because of Moore's Law, we can get a lot more transistors to design with. Why don't we take a budget of, say, 50 billion transistors and dedicate a few billion here and there? I can use those for fixed-function hardware. So there will be a block that does network processing here for you, here's a block that does DVD for you, and here's a block that does speech recognition. These are all fixed-function processors. All they do is the task assigned to them. They are not flexible, but they have the potential to give you very high performance at low power. And that is where active research is focused today.

So in the future, by integrating these three ingredients, a 10x increase in MIPS/watt is definitely achievable.

Do you anticipate any technology roadblocks in achieving this vision of improving performance/watt by 10x?

There are always challenges, what you call roadblocks. If there aren't any roadblocks, we don't have a job. So we have to do research to either circumvent them or move them. One roadblock that we saw 10 years ago was power, and you can see what we have done to solve the issues of power. In the future, one major challenge that we see is a reliability issue related to the circuitry.

Now by reliability, I don't mean the kind of reliability that you think about in the everyday world. Think about a transistor. When you build a transistor today, it functions for the normal lifetime of a transistor, which is about 7-10 years. In the future, as transistors become smaller and smaller, some percentage of individual transistors will stop performing to specification or they won't perform to spec for the normal period of time. A certain number will become what we call “aging” transistors. This is a hot research topic for us and for other researchers: how to design circuit architectures to circumvent the aging of the transistor.

Another example is what is called soft errors. Cosmic rays (neutrons) from outer space striking circuitry do not create any permanent damage, but they can corrupt data, hence called soft errors, as opposed to hard. As transistors become smaller, and transistor density increases, circuitry will be more prone to soft errors. We see these errors even today, but the magnitude of these errors could be much worse in the future.

These are the sorts of challenges for which we are forging ahead with full confidence and are finding solutions through research.

Intel is moving toward multi-core architectures with two, four, and eight-plus cores. How will these new multi-core architectures help manage power, and at the same time drastically improve performance?

In fact, multi-core architecture helps tremendously in managing power. If we look at the processors today, they are active for a short period of time. When you press a button on the keyboard, the processor becomes active, consumes 4-6 watts of power just for a few milliseconds while you are pressing the keys, and then goes to sleep. Today, we call this fine-grain power management. In the future, with multi-cores, we can do even finer levels of power management. Given something like eight cores, if you need only one core to do your task or to run your application, you activate only that one core, the right core. As a result, we save considerable power and reduce costs.

How will the next generation of multi-core help ensure power efficiency and improve Intel microarchitecture capabilities?

There are a few things it can do. One is more fine-grained power management, as I mentioned earlier. The second is that it can give a performance boost. Whenever the applications need maximum performance, for a very short time you have all the performance of all the cores. It's just like the turbo boost in your car. You don't run the turbo all the time when you are cruising on a highway. It's only when you want to pass another car that you use the turbo boost. It's the same thing with computing. If you need a turbo boost in your application, all the processors awaken for one millisecond, give you the performance, and then shut off. Only one processor is active. You get the best of both worlds: both high performance and low power.

With multi-cores, when you talk about fine-grain control, that assumes those cores are smaller and consume less power than today's monolithic cores?

Not necessarily. That is an active research topic today, because small is relative. How small is small? Is it Centrino small? Is it Pentium small? Is it Pentium II small, or is it Pentium 4 small? That is an active research topic: what core size do I need to get the highest performance and the lowest power within the power envelope?

How does Intel's “platformization” approach figure into the power/performance equation?

All the questions that you've asked show that devising a solution just for a microarchitecture or a circuit or software is not enough. What users need is a platform. To create a platform, you have the implementation of the microarchitecture using circuits. Those circuit designs become hardware products through manufacturing and process technology. Then this hardware technology becomes usable via the software technology.

We can't design hardware or software in a vacuum, like we did in the past. No more “I can make a really fast, super ‘C' compiler that will blow the socks off of anyone.” No, no, no. What I need to do now is to build our C compiler with a specific platform in mind. I'm going to write my kernels today to support my hardware in 2010. Then we get a usable platform that has fine-grain power management designed in: microarchitecture that will support it, circuits to implement it, and software that utilizes it.

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Shekhar Y. Borkar is an Intel fellow in the Corporate Technology Group and director of microprocessor research. Borkar is responsible for directing research in low-power circuits and high-speed signaling for Intel's future microprocessors. Borkar joined Intel in 1981. He worked on the design of the 8051 family of microcontrollers, the iWarp multi-computer and high-speed signaling technology for Intel supercomputers. Borkar is an adjunct faculty member of the Oregon Graduate Institute. He has published 10 articles and holds numerous patents. Borkar was born in Mumbai, India. He received a master's degree in electrical engineering from the University of Notre Dame in 1981, and masters and bachelors degrees in physics from the University of Bombay in 1979. To see a list of his patents and publications visit the Intel Web site.

Copyright (c) Intel Corporation 2006. All rights reserved. Reproduced by HPCwire with permission. This article was originally published in Intel's Technology@Intel Magazine.