Facing the Multi-Core Fear Factor

By Thomas Sterling

March 31, 2006

The continuing opportunity presented by semiconductor technology trends characterized by Moore's Law also imposes significant challenges to processor, system, and software designers. The point of diminishing returns has been reached in the exploitation of logic complexity in processor design, and this, combined with severe problems related to power consumption, has forced the industry to embrace the strategy of integrated multiple processor cores on a single die. This “multi-core” methodology is a dramatic shift from prior conventional practices. For the first time it demands that the mainstream software community engage in parallel processing, which until now was reserved for the rarefied field of supercomputing. The scientific and technical computing arena, which has for a long time relied on commodity components as a mainstay of their very large systems, must also address the new challenges of the multi-core era. With the aggravation of the memory wall and the increased dependency on application parallelism, effective use of multi-core technology for high performance computing is threatened by the complacency of backwards looking conventional practices. After more than a decade, a new paradigm for systems designers and application programmers may be required if further advances in HPC capability is to be sustained through the end of Moore's Law and the realization of nanoscale technology.

Historically, every major technology advance, when applied to high-end computing, and sometimes to mainstream commercial grade computing as well, has invoked a corresponding and complementary innovation in computer architecture and the underlying model of computation that it supports. These mutually synergistic changes were motivated by the need to exploit the opportunities afforded by the technologies, while mitigating their intrinsic limitations. Examples include vector computing in the 70's and array processing in the 80's, both of which use the SIMD model, and microprocessor-based MPP and cluster computing in the 90's, using message-passing. Since that last transition, technology has advanced by two orders of magnitude, according to at least one metric, now culminating in this leap to multi-core. The difficulties being faced by system designers and applications programmers have increased measurably, yet the old methods have continued to be employed, if stretched to the limit and beyond.

Is it time for the HPC community to embrace a new model of computation, one that addresses the challenges of the new technology while harnessing its opportunities? There are strong reasons why the vendor producers and the government consumers would prefer to avoid such a move. Often cited are investment in legacy codes, the need to leverage mainstream COTS technologies, and the costs of training those transitioning to a new paradigm. Also identified as objections are the host of failed (not adopted) models and architectures of the past. But this is different. The challenge does not belong uniquely to a fringe domain of HPC geeks, but rather to the entire industry. Parallelism is here. The memory wall is a barrier to everyone, and the future will be shared by scientist and commercial user alike.

What might such a model look like, even if we as a community were prepared to take such a bold step to recover the one to three orders of magnitude improvement potential of the raw technology? Like the previous process that brought us such models as MPI and OpenMP, now both widely used, it would have to address the critical challenges that motivate the move in the first place, and probably benefit from long-term experience by the research community in alternate techniques not yet embodied in mainstream practice. The critical problems faced now and in the past for effective parallel computing, including the use of multi-core are:

  • Latency – the number of cycles to a remote resource like local main memory (hundreds of cycles) or distributed nodes (thousands of cycles),
  • Overhead – the amount of work (again measured in cycles) to manage the parallelism and (through an Amdahl argument) determine the granularity and therefore the amount of parallelism that can be effectively exploited,
  • Contention – the delay time due to insufficient throughput such as chip pin or memory bandwidth, and
  • Starvation – the lack of useful work to be performed by the multiple cores either because there is not enough user parallelism due to poor load balancing.

One possible model that addresses these and synthesizes a number of complementing techniques developed by researchers over a decade or more — in some cases more than two decades — is being considered by researchers at Louisiana State University, the University of Delaware, and other institutions and is based on replacing the dominant Communicating Sequential Processes technique (message passing) with message-driven, split-phase, multi-threaded transaction processing, incorporating local synchronization primitives (e.g., the futures construct) and employing memory accelerator co-processor support. That's a lot of buzzwords but it amounts to a strategy that hides latency, exposes more parallelism and attacks the memory wall. For the sake of a name and in order to avoid such awkward phrases as above, we refer to this strategy as “ParalleX”, which is under development by the collaborating universities. ParalleX is not the simple solution that everyone would like (i.e. “the silver bullet”) just requiring a few changes to software to make everything alright. But ParalleX does suggest a comprehensive conceptual framework to consider the space of choices including some software techniques that could improve the use of large-scale distributed systems; techniques that have been pursued before, such as the UC Berkeley work in Active Messages a decade ago. More likely, ParalleX, if proven useful through future simulation studies, will provide a set of governing principles for a new generation of hardware and software systems that would enable effective use of future multi-core based computing.

The key concepts upon which ParalleX is based includes the following:

    1.  Multi granularity multithreading
    2.  Split-phase transactions
    3.  Prestaging
    4.  Global but hierarchical name spaces
    5.  Fine-grain event driven synchronization
    6.  Message-driven computing
    7.  In-memory synchronization

It is beyond the scope of these brief comments to describe ParalleX in any detail. It should be noted that every one of the above ideas is represented in some form in prior art. ParalleX as a synthesis of these may be original, but the basic semantics taken individually are not. Nonetheless, with respect to conventional practices, these techniques, if applied, would provide a new execution model permitting a new generation of hardware architecture, compilation methods, and runtime services for substantially greater efficiency across a broader range of application classes, while effectively exploiting the basic concept of multi-core component structures.

The impact on architecture may be significant but need not be disruptive. Augmenting the multi-core components with co-processors to facilitate both the message-driven computing event handling and multithreading scheduling, as well as the task data prestaging, could go along way in reducing the overhead for split-phase transaction processing, thus hiding the system-wide latency and local main memory latency. Adding processing in memory, perhaps in the external L3 cache, which is often DRAM technology or in the main memory itself, would greatly reduce the average access time to data for low temporal locality computation, the kind that is particularly ill-suited to conventional cache hierarchies. The use of in-memory fine-grain synchronization eliminates the need for global barriers and the inefficiencies that they impose, while exposing massive data parallelism for sparse irregular and time varying data structures. And global name space that doesn't assume cache coherency, and the costs (time and power) that that implies, but permits a copy semantics where specifically required (location consistency), may yield the best compromise between the two extremes.

ParalleX may not be the right model, but as a focus for discussion it exemplifies the strategic question of if and when the community once again moves forward to adapt system architecture structures to make best use of technology advances through the powerful conceptual medium of a new model of computation. It also identifies many of the critical challenges that any such model must address and suggests a number of promising techniques that could be employed to meet these challenges. While there is much resistance to change, and for good reasons, historically we have already done so. Perhaps, with the advent of widespread multi-core commercial components, it is time for the community to address the multi-core fear factors and begin the process towards the next paradigm of parallel computing and application programming.


Thomas Sterling is a Professor of Computer Science at Louisiana State University, a Faculty Associate at California Institute of Technology, and a Visiting Distinguished Scientist at Oak Ridge National Laboratory. He received his Ph.D as a Hertz Fellow from MIT in 1984. Thomas is probably best known as the “father” of Beowulf clusters and for his research on Petaflops computing architecture. He was one of several researchers to receive the Gordon Bell Prize for this work on Beowulf 1997. In 1996, he started the inter-disciplinary HTMT project to conduct a detailed point design study of an innovative Petaflops architecture. He currently leads the MIND memory accelerator architecture project for scalable data-intensive computing and is an investigator on the DOE sponsored Fast-OS Project to develop a new generation of configurable light-weight parallel runtime software system. Thomas is co-author of five books and holds six patents.

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