The Search For Next Generation Supercomputing

By Michael Feldman

April 7, 2006

In this special issue of HPCwire, all of our feature articles are devoted to DARPA's High Productivity Computer Systems (HPCS) program. The program is designed to take supercomputing to the petascale level and increase overall system productivity ten-fold by the end of this decade.

In 2001, DARPA initiated the HPCS program to drive the development of a new generation of economically viable, high productivity supercomputing systems for government and industry. As Phase II of the HPCS program draws to a close in the middle of this year, the three competing vendors — Cray, IBM and Sun Microsystems — are finalizing their R&D for their respective entries.

The new generation of supercomputers will scale to 10's to 100's of thousands of processors, connected by ultra-fast interconnects, and be able to access petabytes of memory. There are substantial challenges to construct such systems, but the technology that provide these capabilities is available now, or soon will be. The real challenge will be to build such systems in a cost effective way — a stated goal of HPCS is to produce commercially viable systems.

But the HPCS program is about more than just petaflops. The real value of an HPC system is measured by a variety of factors including cost (both up-front and lifecycle), performance, robustness, portability and programmability. Taken together, these factors represent the productivity of the system. One of the main goals of the HPCS program is to increase overall HPC productivity by a factor of ten compared to current technology. However, the concept of system productivity is quite complex and being able to define and measure it is, itself, a major focus of the HPCS effort.

Increasing productivity means creating more powerful software models. Recent surveys of supercomputing centers found that most HPC applications are being implemented with legacy programming language — FORTRAN, C, or C++ — usually with a mix of MPI or OpenMP to facilitate parallelism. It is widely believed that this software model will be inadequate for fully exploiting petascale systems. Even looking at today's terascale systems, the gap between hardware and software capabilities is already uncomfortably large. Programmability — the “time to solution” — is a big problem for HPC applications and is about to become bigger.

To address this, new programming languages and new development tools are also being researched. Each HPCS vendor has proposed a programming language specifically targeted for high performance computing — Chapel (Cray), X10 (IBM), and Fortress (Sun). New compiler and run-time technology will needed provide a portable, abstract programming model for highly parallelized applications. Debugging tools that can deal with thousand of threads will also need to be developed. At the same time, the software environment must also support the legacy HPC applications that have already been built with current toolsets. The software challenges are formidable.

Our first HPCS feature article is an excerpt of a recent interview we did with Douglass Post, chief scientist at the DoD High Performance Computing Modernization Program. He gives us his impressions of the HPCS program and talks about its significance to the HPC community. His considerable expertise in HPC modernization provides some interesting insights.

The remaining three feature articles were provided by the vendors, themselves. In them, they discuss their individual HPCS designs — Cray's Cascade, IBM's PERCS and Sun's Hero. Some of the design details are left to our imaginations, but all the vendors have presented a compelling vision of their next generation systems.

In Cray's Cascade, they are looking to implement their adaptive computing strategy, which they announced just last month. In this model, software transparently maps application code to the most appropriate processor in an integrated heterogeneous architecture (scalar, vector, multithreading and hardware accelerators ). Cray summarizes their design as “an HPC datacenter in a box.”

IBM's PERCS (Productive, Easy-to-Use, Reliable Computing System) design is, not surprisingly, based on their own POWER architecture. For IBM, this makes sense. They've got a big investment in the architecture and it is the basis of a lot of their HPC offerings, including the Blue Gene technology. The company also plans to leverage their expertise in semiconductor manufacturing to produce cutting-edge performance and reliability.

The Sun motto of “The Network is the Computer” is evident in their HPCS entry, named Hero. The company plans to use emerging interconnect technologies to provide dramatic increases in interprocessor communication. Proximity communications technology will be used to increase chip-to-chip data transfers, while silicon photonics will be used to speed inter-module communications. The Hero design also integrates object-based storage to provide a “smart” storage system.

Sometime this summer, DARPA will be selecting one (or possibly two) vendors to be funded for Phase III of HPCS, prototype development. This decision will have a direct effect on the direction of capability-class HPC systems for the next five to ten years and more far-reaching effects on overall HPC technology.

I hope you enjoy this special issue of HPCwire. As always, I appreciate any feedback. Mail me at [email protected].

— Michael Feldman

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