In the second part of our interview with Intel CTO, Justin Rattner, he shares his thoughts on the open source hardware model, answers our concerns about the future of the Itanium microprocessor, and talks about some innovative applications for flash memory in the HPC arena.
Open Source Hardware
Although the concept of open source hardware has been around for several years, only recently has it received the attention of major chip vendors. In December of 2005, IBM decided to make its PowerPC 405 core design freely available to researchers and academia. In that same month, Sun Microsystems announced it would make its 8-core UltraSPARC T1 microprocessor 'Niagara' design freely available to anyone, including other vendors. In March of this year it released the Verilog source code for the T1. We asked Justin Rattner what he thought about this new model for building microprocessor ecosystems.
“I'm really struggling to understand it,” admits Rattner. “Hardware is very different from software”
From his point of view, designing microprocessors requires a much larger investment than developing software. Developing a microprocessor require years of design and testing using highly specialized tools. This is followed by production in an expensive fab. He contrasts this with the less resource-intensive model of software, where prototyping can be done relatively quickly and then developed incrementally, often by sharing with other developers across the Internet.
“For software, the non-recurring engineering costs are relatively low as compared to hardware, where they're relatively high,” says Rattner. “Also, I think the successful open source projects are highly managed communities. There's the sense that everyone's pouring code into this funnel and good things are coming out the bottom. But if you look at Linux, Apache and some of the other real successes with open source, there's tremendous management involved in them. Trying to manage those kind of contributions in a hardware context seems to me to be formidable, and certainly unproven. I think we'll watch to see how it goes and see what benefits come from it.”
Rattner also notes that the processor volume has to approach the hundreds of millions to attract software developers. “Even investment funds, such as the Itanium Solution Alliance, have to deal with that reality,” he says. “Developers have to choose the platform that's going to provide them with the necessary return. I think that's really at the bottom of whole question. Putting an architecture in open source really doesn't alter that fundamental volume question.”
Speaking of Itanium, the CTO believes Intel's 64-bit answer to RISC is gaining momentum in the high-end server market. He points to the recent surge of the Itanium in Japan, where systems from NEC, Hitachi and Fujitsu are outpacing both Sparc- and Power-based servers. He also sees Itanium volume ramping up here. Its former rivals, MIPS and Alpha are all but gone from the server market, and HP's PA-RISC processor is being retired to make way for the Itanium.
“We're continuing to make a substantial investment in Itanium,” says Rattner. “We've got the Montecito coming to market. We've got processors in the design pipeline. The volumes are actually building relative to its direct competition, namely Sparc and Power. We firmly believe that it is destined to become the high-volume post-RISC microprocessor out there.”
According to Rattner, Itanium's mission is to provide an alternative to the proprietary RISC microprocessors, not as originally conceived by some, to create a dominant 64-bit architecture across the spectrum of servers, workstations, and desktops. Intel's aspirations to get into the Unix server market required a 64-bit solution that they believed could not be achieved with the x86 architecture.
“I really don't recall a time, in our own minds, where we positioned Itanium as a the ultimate replacement for x86,” says Rattner. “We always thought about it as a counter-strategy to RISC in the data center. We felt the opportunity existed for Intel to introduce a RISC-like alternative for people that were looking to move off of a proprietary architecture and on to a standard volume product. That's been the name of the game for Itanium for a decade. When judged against that objective, I think it's done remarkably well.”
As far as differentiating Itanium from the 64-bit x86 platforms, Rattner explains that there are a number of attributes which distinguish it, including relative cache size, address reach and RAS functionality. These features all point the architecture towards the higher end of the market.
“There's definitely space above the 64-bit x86 server processors and that's really the space that Power and some of the Sparc implementations target. Just look at the way Power is packaged. There's no x86 processor that gets the kind of multi-chip packaging that you get from IBM or that operates in a thermal envelope of hundreds of watts. That's really the Itanium space and I think you can expect to see us, in some sense, take the brakes off in terms of really putting Itanium into that high-end server space, well above where the [x86] Intel server processors will go.”
In explaining why the Itanium has been the target of a lot of criticism, Rattner admits that the platform got off to a poor start, which created some bad first impressions. The original Merced chip, released in 2001, was manufactured on a 180nm process with an underpowered cache. Its performance, especially integer performance, was uninspiring.
“It came to market either too late or too early,” says Ratter. “It missed its original introduction target by several years. The implementation that came to market basically lost a two-year Moore's Law cycle and didn't have the overwhelming performance lead that it would have had it if it had come to market in say, 1998 as opposed to 2000. By the virtue of the fact that it was late, the implemenation wasn't this kind of 'home run' from a performance point of view. So that definitely created an initial impression about the architecture which was a bit unfair because of the lateness of the design. When Itanium 2 came to market, what we call McKinley, those were quite timely. They were on the process cycle, not a cycle behind. I think it regained much of its credibility, but it had to overcome the perceptions that were built from the first implementation.”
The Road Ahead
Rattner also spoke about some of the upcoming technology we can expect to see from Intel after 2006. The company is planning to produce microprocessors on the 45nm process sometime in the second half of 2007. According to him, they've already demonstrated some of their key test vehicles using this new process technology. “Our two-year technology cadence is in very good shape and products are in the pipeline that will take advantage of 45nm technology,” says Rattner.
In addition. Intel is planning to continue its almost fanatical focus on energy efficiency — and not just at the microprocessor level. The company is looking to expand the use of flash memory beyond that of popular consumer devices (cell phones, portable music players, USB flash drives, etc.). Rattner says that Intel has some key intellectual property that enables them to lengthen the acceptable service life of these flash devices.
“They do have wearout mechanisms — you can only write them so many times,” explains Rattner. “But we've developed what I'll describe as system solutions to minimize the write activity across the array, to eliminate some of the erase-write cycle limitations.”
In the short-term, Intel plans to use flash technology to create a new level in the storage hierarchy on PC platforms, where it will be used to keep the disk much quieter, reducing its active duty cycle, and at the same time accelerate the performance by a factor of two to four. Rattner thinks we'll see the first PC platforms featuring flash memory in the first half of 2007.
“Now the area we haven't talked much about is the role that technology could play in the enterprise and in high performance computing,” says Rattner. “The storage gap is just as significant on the server side, if not more so. We're working now on defining what role the flash technology will play in the server space. Using back of envelope kind of calculations, it can have dramatic impact not only in performance and energy efficiency, but also in cost. Today people add disk spindles to get parallelism in the storage subsystems. Well when you alter the latency by several orders of magnitude, you can dramatically reduce the number of spindles. So if latency is the performance bottleneck, we think flash has tremendous potential.”