Thomas Sterling Speaks to the Future of HPC

By Christopher Lazou

June 9, 2006

At the recent NEC User Group meeting in Toronto Canada, Thomas Sterling gave a keynote address to share his thoughts about some of the key challenges facing the high performance computing community. At the event, contributing editor Christopher Lazou caught up with Sterling, where they discussed these challenges and talked about some possible solutions.

Lazou: Thomas, it's good that you can spare some of your valuable time to talk to me. We meet again this time at the annual NEC users group meeting, this year in Toronto, Canada, with an eclectic group of users of true supercomputing. As a keynote speaker, you are the man of the moment. Glancing at your many hats you wear, one can see you have a number of important roles and long experience in computer architecture research, so lets briefly discuss some of the burning issues concerning HPC and in the process try to gain an insight of your views and share them with the HPC community.

Last year you moved to LSU as Professor at the Department of Computer Science focusing on HPC systems architecture research. Can you briefly describe the key areas of research your team is concentrating on? Would this work be of benefit to HPC in the short term or is it blue-sky research?

Sterling: We are currently exploring key challenges of a new class of computer architecture to confront efficiency, scalability, power and reliability. This requires a paradigm shift of execution and programming models. There is a desperate need for intrinsic latency hiding mechanisms to be incorporated in the infrastructure of programming and runtime resource management.

We are developing a new model for computing called “ParalleX”, extending our earlier work in processor in memory (PIM), and combining these with new work in static dataflow to provide a new class of architecture that adaptively responds to variations in temporal locality. The short-term impact is that the execution model has a spin off of a programming methodology that can operate on conventional architecture. It should improve latency hiding and scalability. In some small way, this work is already influencing projects sponsored by the DoE, as part of the Fast OS project and by the NSF project (NGST).

Lazou: Is there any Federal investment in innovative high-risk computer architecture R&D?

Sterling: There is very little Federal funding for this type of research activity. There were recently several studies, which concluded that the HPC architecture research pipeline is empty. Examples of such studies include the National Academy of Science report, and the HECRTF and PITAC studies. The possible exception is the DARPA HPCS program, but you asked about “high risk” and it is not clear that HPCS falls in to that category. With respect to my own work that you asked about, I have Federal support for some relevant software projects. And, until recently NASA was sponsoring the hardware research but this funding ended last March. A small system architecture study is underway by NASA in which I am involved, as well. Elsewhere, there is some other good work being supported in FPGA-based computing and work at Stanford, University of Texas, and University of Washington. Hopefully, there will be new energy and direction from the agencies in the near future. Certainly it is in the best interest of their respective missions and that of the nation to reinvigorate such valuable explorations.

Lazou: In the next five years, silicon would be the material for high-end computer chips. Can architecture changes extend silicon life to say another five years?

Sterling: Yes. The research mentioned above at several universities could lead to significant improvements in the use of current generation silicon technology and suggests approaches to extending the useful life of silicon for general purpose computing down to near nano-scale. The work I and my collaborators are doing could constructively impact on this as well, so long as vendors accept the challenge and implement demonstrated improvements. Vendors cannot be expected to take the risk in a domain of such uncertainty. Rather, Federal funding should be used to explore the space of possible approaches and determine which concepts are viable. We are making poor use of silicon today compared to what it is capable of. I believe that new architectures can give us performance improvements of one to two orders of magnitude from what we get today. The IBM/Sony Cell architecture, for example, hints at the possibilities.

Lazou: What is the most promising material expected to replace silicon for supercomputing chip production?

Sterling: The most likely replacement for silicon is silicon; and by that I mean new semiconductor materials incorporating silicon. Beyond that, my personal opinion is that the most promising technologies likely to enhance the use of advanced silicon technologies are: a) chip to chip optical interconnects, b) Wafer-scale technology, but this has to have built-in fault tolerance, otherwise low yields will kill it. c) Niobium RSFQ super-conductive technology; this is unpopular, but the power benefits at higher clock rates are significant. And d) MRAM – magnetic RAM for low power, high density storage. There is also the possibility of new packaging techniques that may greatly increase density, such as 3-D structures; but this assumes we can get the heat out. In each of these cases we have enough proof of concept experiments in laboratory tests to demonstrate their promise Using fiber optics one can deliver close to one Terabit per second rates and super-conductive material can clock at in excess of 700 GHz. RSFQ was cited in a previous ITRS report by the SIA as a potential future technology.
 
Lazou: By 1986, there was a lot of optimism that GaAs and optical computing will become mainstream within a decade and yet twenty years on, with the exception of communication networks it is still a future aspiration. When are we expecting optical computing to become mainstream?

Sterling: Pure optical logic and optical memory is not presently an option, although some interesting work in nonlinear optical technologies is intriguing. There is some hybrid MRAM, but it is my understanding that presently magnetic storage is likely to outperform optical in terms of density and speed. There is no clear direction on this. At the risk of sounding somewhat lame, only time will tell.

Lazou: What are the engineering challenges to be overcome?

Sterling: In optical devices, the biggest challenge is the switch, which allows one to do logic and store functions. This will require significant advances in nonlinear optics to enable pure optical-to-optical functionality (without intervening electronics). Needless to say, the real challenge for optical devices to enter the mainstream is that they will have to be competitive with semiconductor silicon devices in terms of performance, power, density, reliability, and cost; not an easy set of requirements.

Lazou: The second phase of the DARPA high productivity initiative has been completed and, as I understand it, the three vendors, Cray, IBM and Sun Microsystems have presented their R&D results for DARPA evaluation and selection to award funding for the next phase. Do you have a preference of any of the three architectural paths?

Sterling: I have no preference. Each of the three projects highlighted certain improvements in systems design with some architecture extensions, without being disruptive in the market or to their product direction. I do wish that HPCS had found a way to make better use of this nation's research talent that exists outside the scope of the selected system vendors. I think had they done so, the program and the nation would have been better served.

Lazou: You have been involved in the Cray Cascade petaflops project in the past. How do you assess its potential?

Sterling: I was involved in Phase 1 of the Cascade project and helped initiate their Phase 2 effort, but I am no longer involved in that project. Therefore, I have no deep insight into the specific details of the currently proposed architecture. Phase 1 explored extremely interesting and potentially important innovations. While the current Cascade strategy is very different from Phase 1 studies, as I understand it, it does incorporate meaningful advances in technology, architecture, networking, and programming methodology towards improved productivity. Probably the other two participating vendors, IBM and Sun, would make similar claims.

Lazou: For petaflops projects vendors are resorting to heterogeneous systems, with additional components, for example, FPGAs, ClearSpeed co-processors, PIMS and so on, to minimize latencies. Are the vendors running the danger of creating a complex architecture and shifting the delays onto system management?

Sterling: Yes. There is a strong interest in heterogeneous processing, enabling optimal structures for key modalities of computing. There are clear examples, where this strategy delivers superior performance with respect to size and power, and in some cases cost. Yes, there is a real danger that this will result in runaway complexity. If however, such diversity of structure is implemented within a coherent framework, that permits an effective programming and resource management model, then, heterogeneous approaches may yield an important source of improvement. My team and I, are pursuing heterogeneous computing within the context of the memory system, to provide a kind of memory accelerator using advanced PIM architecture, to address an important dimension of performance degradation in today's architectures, for some classes of applications (e.g., adaptive mesh refinement and directed graph algorithms).

However, without a unified model of governing principles to coordinate the structure and organization (architecture) with the programming model, the final product is unlikely to deliver the identified potential benefits.

Lazou: What about the software aspects concerning these new systems? Are new languages the answer?

Sterling: We are programming the wrong computers. Almost all our computers are designed to be sequential with very little scalability. They are not designed to be large scale highly parallel HPC. They do not address the problems of parallel overheads, latency hiding, resource contention, starvation – a combination of parallelism and load balancing. Therefore, programmers are forced to explicitly overcome these barriers with their codes, through painstaking manipulation of details, some of which is not even directly accessible (e.g. caches). This was one of the important challenges that the DARPA HPCS program, attempted to attack.

Lazou: New languages (which by their nature are non standard) are unlikely to induce ISVs to risk porting their packages. How is this software hurdle to be overcome?

Sterling: Every language was a new language at one time. Most are not accepted by the mainstream. Some are adopted for niche applications. Very few have a major impact. The thing to remember is that over the next sixty years (the length of all electronic computing to date), we will write many times as much software than already exists today. The true legacy code is our future not our past; what we will be using, not necessarily just what we have been using, and has yet to be written. However, I do not believe there is a silver bullet for conventional architectures. New languages will need new architectures that will need new languages.

Lazou: As we are at an NEC user group meeting, can you comment on Japanese supercomputers and the recent Japanese government's initiative for future petaflops computers?

Sterling: The Japanese continue to demonstrate the viability and importance of custom parallel architecture, with the NEC SX-8 as an exemplar. They also recognize the importance and value of balanced system architectures, including sufficient bisection bandwidth and memory bandwidth. It is my hope that they will take these skills and perspectives to the next level and explore the potential for radically improved computing techniques. I do not think there is time to do this for the Japanese Petaflops initiative, which is to be delivered in the 2010 timeframe. But they could begin preliminary work now in preparation for the 32 Petaflops system, sometime in the next decade.

Lazou: Thank you Thomas, for your invaluable time and in sharing with our readers your opinions and insights, on the many challenges facing the HPC community.

—-

Dr. Thomas Sterling is a Professor at the Louisiana State University Department of Computer Science and Center for Computation and Technology. In addition, he holds the positions of Faculty Associate at the California Institute of Technology Center for Advanced Computing Research and Distinguished Visiting Scientist at the Oak Ridge National Laboratory. Since receiving his PhD from MIT as a Hertz Fellow in 1984, Dr. Sterling has engaged in a wide range of applied research associated with high performance computer systems architecture and software. He is widely recognized for his contributions in cluster computing through his leadership of the Beowulf Project (for which he was one of several to win the Gordon Bell Prize in 1997) and for his work in Petaflops scale system architecture through the HTMT and Cascade HPC system projects and the DIVA and Gilgamesh processor in memory (PIM) architecture projects. He is currently developing the ParalleX Model for future generation parallel computing and is co-investigator on DoE, NSF, and NASA sponsored research projects. Dr. Sterling holds six patents and is the co-author of some five books in the field.

Copyright (c) Christopher Lazou, HiPerCom Consultants, Ltd., UK. June 2006. Brands and names are the property of their respective owners.

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