A Personal View of Cray’s Message at ISC2006

By Christopher Lazou

July 14, 2006

… There was something endearing and personal about Johnny Von Neumann. He was the cleverest man I ever knew, without exception. And he was a genius, in the sense that a genius is a person who has two great ideas… J. Bronowski, “The Ascent of Man,” pp433, BBC 1973.

First, the conference preliminaries: Over 800 participants from 33 countries attended the 21st International Supercomputer Conference (ISC) and 74 exhibitors took part in the associated exhibition in its new venue, the city of Dresden.

This ISC annual event enables many Europeans to assess the new technology from Japanese and USA vendors and to also be updated by our American colleagues about where they are in addressing the issue of leadership in large scale scientific technical computing. The presentations at the conference were broad-based, with some at the cutting edge of developments.

As usual, Professor Dr. Hans Meuer and his team from the University of Mannheim put on a fine vendor exhibition — a collection of stimulating presentations — and delivered a seamless conference in yet another beautiful historical city, this time, Dresden. The main sponsors this year were HP and Intel, two vendors with a big share of the HPC market.

ISC2006 provided an opportunity for vendors to peddle their products and share their plans for products expected in the near future. This article highlights one path, taken by a single vendor, on how to deliver the productivity promise and sustained petaflops performance by 2010 and beyond. In this article I concentrate on Cray's way forward for the simple reason that the company just signed a $200 million contract with the U.S Department of Energy (DoE) for just such a system. This is a significant contract. The money is equivalent to one year of the company's turnover revenue, or two years funding for R&D.

What is then Cray up to? To briefly recap, the company is having a growing presence in large scale computing. For example, they have sold large systems in South Korea and Spain for weather/climate predictions, at Sandia in the USA and at AWE in the UK for simulations in nuclear weapons systems, and at CSCS in Switzerland and Oak Ridge National Laboratory (ORNL) in the USA for scientific research. They are currently negotiating with the Engineering and Physical Sciences Research Council (EPSRC) in the UK for delivering a 50-plus teraflops system to the scientific research community. They also provided systems for the Japan Advanced Institute of Science and Technology and a large Cray XD1 system at Toyota in Japan.

Last March Cray announced their 'Adaptive Supercomputing' vision. According to the company, adaptive supercomputing will cause a paradigm shift in the way users select and use HPC systems. Cray believes this model is necessary to support the future needs of HPC users as their need for higher performance on more complex applications outpaces Moore's Law. “Adapt the system to the application — not the application to the system,” said Steve Scott, CTO of Cray Inc, in March 2006.

Scott said that the increasing demand for better performance can no longer be achieved through Moore's law, processor improvements and a one-size-fits-all system mentality. HPC users are no longer getting the performance advances they need from microprocessors. The commercial response to the slowdown in single-core performance improvements has been to provide multi-core chips. These are general-purpose architectures, applicable to most widely used applications. But as is widely recognized, when scientific computing migrated to commodity platforms, interconnect speed, both in terms of bandwidth and latency, became the limiting factor on application performance and remains a bottleneck to this day.

Cray concluded that although multi-core commodity processors will deliver some improvement, exploiting parallelism through a variety of processor technologies using scalar, vector, multi-threading and hardware accelerators (for example FPGAs), will create the greatest opportunity for application acceleration.

The components for Cray's essentially MPP adaptive supercomputing are being put in place. The MPP scalar space is addressed by the AMD Opteron technology; the vector space is addressed with the X1E technology. The MTA technology along with the recent announcement that the DRC Computer Corporation has been selected by Cray to provide a new FPGA coprocessor module as a massively parallel reconfigurable option for future Cray supercomputers, completes the set — at least for the present.

Initially, Cray plans to market two different multi-architecture systems. These are codenamed the “Eldorado” (upgraded Cray XT3 technology plus multithreading) and “Black Widow” (upgraded Cray XT3 technology plus vector processors). They are on schedule to become available in 2007.

On June 15, 2006 Cray announced that it had signed a multi-year contract with the U.S. Department of Energy's (DoE) Oak Ridge National Laboratory (ORNL) to provide the world's first one petaflops-speed supercomputer.

The total contract, including systems and services, is valued at about $200 million and calls for progressive upgrades to ORNL's existing Cray XT3 supercomputer. This system will be upgraded to dual-core processors later this year, accelerating peak speed from 25 teraflops to 50 teraflops. Further upgrades will increase the performance to 100 teraflops, planned in late 2006, and to 250 teraflops, planned in late 2007.

ORNL is then expecting to install a next-generation Cray supercomputer in late 2008. This system, code-named 'Baker,' is designed to deliver peak performance of one petaflops, making it roughly three times faster than any existing computer in the world today. This system will contain the most advanced AMD Opteron processors available in 2008 timeframe, likely to be quad-core.

As readers of this publication are aware, there are many challenges to be overcome on the way to one petaflops productivity, including addressing memory and network subsystem capabilities and managing software complexity. In current architectures, processors are separated from memory, from which they fetch operand data to feed the arithmetic functional units. Processing delays accumulate as network latency adds up over the thousands of processors required for a one petaflops system.
As the High-End Crusader keeps reminding us: “The key task for system software, in heterogeneous-systems, lies in scheduling strategies and other system functions that maximize the performance extracted from scarce system resources, notably the heterogeneous system's limited global system bandwidth.” In other words, one must minimise and hide latency.

So at ISC2006, I listened to Steve Scott's presentations and also met with him privately. I asked him to put some meat on the ORNL petaflops announcement.

What I discovered is that the 'Baker' system, scheduled to be deployted in 2008, will be Opteron-based and consist of around 24 thousand AMD Opteron compute chips — no vectors, no MTA type threads and no FPGAs. It will however, integrate the successful communication and active management components of the Cray XD1. Cray sees this one petaflops system as phase one of the Cascade project.

I pressed for a detailed specification, but Steve understandably declined to be precise since the final configuration depends on future AMD chips. So I spoke with AMD and others. Using the 2008 timeline and the projected number of processors, I concluded that 'Baker' can be built with 24,000 AMD Opteron chips, using 65 nm technology at 2.8 GHz. To achieve this, each chip must have quad cores and each core must deliver four floating-point results per cycle. This scenario delivers just over one petaflops peak performance. 'Baker' will be using hypercube connectivity, that is, the interconnect based on the Cray XT3 technology. The power required is about six megawatts and the whole system fits into 136 cabinets. Getting 16 floating-point results per cycle (over 44 Gigaflops) out of a scalar chip requires a lot of bandwidth and system management.

The next natural question which arises is why an MPP architecture and how is Cray going to integrate the other three main compute components to fulfil the Cascade roadmap. Apparently scaling an SMP or cluster to such large numbers of processors is very difficult. Efficiency degrades sharply because of cache coherence requirements and operating system jitters.

The Cray XT3 MPP architecture is well understood and proven by its progeny, the successful Cray T3E. To remind the reader, the Cray T3E was designed in the early 1990s by a team headed by Steve Oberlin, which included a young Ph.D. engineer, straight out of University of Wisconsin, namely Steve Scott.

The Cray XT3 architecture incorporates the Cray T3E's E-registers for references. These registers support large numbers of fine-grained parallelism and therefore vectors map well onto the scalar hardware. The other great plus of this architecture stems from its high bandwidth network design. It uses a 3-D toroidal network which is very economical for global bandwidth, since it grows at the rate of the square root of (2/3)N. The current network design can support up to 60,000 multi-core processors.

For the Cascade petaflops system, Cray is introducing special hardware interfaces and also extending port support to 64, so that it can handle the interconnect efficiently. The Cascade design is addressing one of the fundamental barriers for achieving productivity on previous general-purpose systems, namely, that no one processor type is able to effectively encompass the needs of all application domains. For example, some applications require high global communication bandwidth or handle irregular data, whilst others use many threads but need little global communication. Incidentally, as a by-product, the use of threads alleviates the worst impact of Amdahl's Law and lowers the cost/flop.

Integrating heterogeneous elements may be technically possible, but users are more interested in how the Cray MPP system manages the flow of computation in an application in order to avoid loss of efficiency from the implication of Amdahl's Law.

According to Steve Scott, adaptive supercomputing is designed to deliver high productivity. The user is offered a hardware mix, providing a “best fit” for the application. The user has access to those heterogeneous resources with one user interface, without the need to understand the idiosyncrasies of different system types, and uses one set of tools. Cray is providing a compiler, which will analyse the user code and decide which part of the code to execute on each compute component, in order to achieve the optimised time to solution. This approach delivers human productivity by minimising the time for code development and debugging.

Cray claims that the flexibility of adaptive supercomputing allows a better mapping of the paradigm to the application needs. By having more powerful nodes (multi-core, with lower frequency and lower power) and less control in the compute processors, one can achieve more floating-point calculations.

The plan is to deliver adaptive supercomputing in a transparent, scalable, robust and optimised way, by using scalar, vector, multi-threading and possibly reconfigurable computing. At this final phase, one will see the development of Cray systems that incorporate dynamic resource allocation using software that automates adaptive supercomputing. The Cascade emerging technologies are expected to deliver this integrated platform in the 2009/10 timeframe. Cascade is expected to include heterogeneous processing at the node level, with fast scalar, vector and highly multithreaded capability, all in the same cabinet.

To complete the circle and end where I started, Johnny Von Neumann's two great ideas were of course the Von Neumann Computer Model we have been using for the last sixty years and the theory of games. His 'Computer and the Brain' work remained unfinished. I leave you with a tantalising thought. The Cray Company is synonymous with vector supercomputers, using the Von Neumann Model. Could it be that 'Adaptive Supercomputing' is its second great idea?


Copyright(c) Christopher Lazou, HiPerCom Consultants, Ltd., UK. July 2006. Brands and names are the property of their respective owners.

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