A Tutorial of the RDMA Model

By Renato Recio

September 15, 2006

[Editor's note: The complete article with graphics is available at http://www.hpcwire.com/hpc/885757.html]

RDMA encompasses more than can be encapsulated by a reference to RDMA Writes and RDMA Reads. The reduction of the RDMA programming model by describing a poor mapping over MPI or for that matter Sockets indicates a limited understanding of the extensive capabilities of the full RDMA Model.

Forward thinking architects look to future trends instead of stretching to illustrate (or alluding to) similes with past implementations when gauging the value of a technology. This paper will show how current trends in basic and derivative technologies, such as the periodic doubling of CMOS density, will continue to cement RDMA's already significant traction with HPC, its deep incorporation into the OS, and its growing position in database and storage solutions.

This article begins with an overview of the RDMA Model and then describes the attributes of a well performing RDMA chip architecture. It will describe how the RDMA Model can benefit existing APIs, such as MPI and Sockets. At the dismay of legacy network adapter architectures, it is worthwhile to note that APIs also evolve to take advantage of standardized networking enhancements. This article will describe API evolutionary steps that enable even higher performance benefits.

RDMA Model Basics

The RDMA Model is more than RDMA Writes and RDMA Reads. The RDMA Model provides mechanisms that enable out of user space operations to a previously registered user space memory buffer without operating system (OS) involvement. The registrations are stored in memory translation and protection tables (MTPT), which can be stored in system or adapter memory. These registrations are then used to translate and validate data that is being transmitted from or placed into the registered buffer. The data transfer mechanisms include Sends, RDMA Writes, RDMA Reads and Atomics, some vendors may have proprietary value added mechanisms too.

The RDMA Model is more than RDMA Writes and Reads. Following are the major capabilities that define the RDMA Model and contribute to making it the highly efficient solution that it is:

* The support of many Send/Receive Work Queue (WQ) Pairs (QPs), in the order of thousands to millions.

* Memory registration of user space buffers with the adapter and a mechanism to associate a registered buffer with one or more QPs.

* QP Work Queue Elements (WQEs) that can reference any previously registered buffers.

* Several standard Send WQE operation types: Send, RDMA Write and RDMA Read. In the case of InfiniBand these also include Atomic Fetch & Add and Compare & Swap.

* A mechanism to signal and retrieve the completion results of a previously submitted WQ operation.

To support the full range of middleware targeted by RDMA, a good RDMA Model ASIC has the following characteristics:

* It fully offloads the transport and data placement mechanisms. For example, having to wake up a thread to process an RDMA Write is a bad implementation that does not support all the middleware the RDMA Model targets.

* Transport and data placement performed via parallel finite state machines (FSMs). When a given function is very stable, an FSM implementation requires less gates and is faster compared with just using small, slow (compared to host CPU) embedded cores. Note, embedded cores can be used to aid and to support new functions.

* The QP and MTPT context is cached in the ASIC. ASIC vendor scaling of QP and MTPT context cache sizes to match the capabilities of new CMOS generations. Given CMOS circuit/area doubling trends, this allows at least a doubling of context size every 12-18 months. Further increases are possible when one considers that the rest of the ASIC logic doesn't need to double in size with each new ASIC generation.

* Both a reliable and unreliable transport is supported. Adapters that support the IB HCA specification must provide both. An iWARP RDMA enabled NIC (RNIC) can also support an unreliable transport (e.g. Layer 2 NIC or even UDP).

* Prefetch of WQE's, especially for Send and Shared Receive Queues to overlap I/O processing.

Vendors have implemented network adapters that support the RDMA Model and scale very well as the number of processes (and their associated QPs) is increased from 2 to 2049. For IB, Mellanox has posted an excellent paper showing the scaling bounds of their implementation, see: http://www.mellanox.com/pdf/whitepapers/PCIxVsMemfree_WP_100.pdf .

Programming over the RDMA Model

As with any programming model the success of its application depends largely on the method by which its semantics are implemented. When we created the InfiniBand RDMA Model, which was also the base we used for iWARP, some of us envisioned two programming models over the RDMA Model: one being the use of existing APIs over the RDMA Model and the other being the evolution of existing APIs and protocols to fully exploit the RDMA Model. Following is a description of how both of these programming models can take advantage of the RDMA Model.

There was no guidebook for mapping existing APIs (Sockets and MPI) that did not support memory registration over the RDMA Model. To help folks (e.g. SCSI, NFS, Sockets) map existing APIs over the RDMA Model, we observed the following:

* The layer between the API and the RDMA Model should support memory registration and two forms of data transfer, Send/Receive and RDMA Write/Read.

* Long lived memory registrations are used for Send/Receive data transfers. That is, the RDMA library performs a user space copy of the user's buffer into/out-of a long lived registered buffer.

* Dynamic memory registrations are used for RDMA Write/Read data transfers. That is, if the user space buffer isn't already registered (see 7th bullet in this list), the RDMA library dynamically registers the user space buffer.

* Memory registration has a finite number of deterministic CPU instructions, consisting of a context switching into the kernel, memory pinning by the kernel, memory registration with the adapter and a context switch back to user space.

* Out of user space memory copies also have a finite number of deterministic CPU instructions.

* If the overhead associated with buffer registration and de-registration exceeds the overhead associated with a user space buffer copy, then Send/Receive should be used. Otherwise RDMA Write/Read should be used. That is, Send/Receive should be used for control and small messages; and RDMA Writes/Reads for larger messages, where the cut-off between small and large is depends on the overheads (registration vs copy) associated with the OS/processor platform.

* Additionally, lazy de-registration algorithms were created to avoid the registration overhead for the case where the programmer re-uses buffers.

* For RDMA Writes and Reads, a buffer advertisement mechanism is necessary. The mechanism can be a-priori or a part of the programming model's wire protocol.

* The cost of scaling a reliable RDMA transport (IB Reliable Connected or iWARP) is analogous to the cost of scaling a reliable non-RDMA transport (e.g. TCP). That is, each connection must retain a context that is used for reliability checks. If reliability is required, then performing the reliability checks are required, whether they be performed in the host CPU or the adapter. If they are performed in the adapter, then to scale efficiently the adapter must have high bandwidth access to the context, just like the host CPU must have high bandwidth access to the context if the reliability check is performed on the host.

We also observed that the RDMA Model can be exploited ever further if the following are made visible to the programming model's API:

* Memory registrations. The Sockets Extensions standardized by the ICSC (see http://www.opengroup.org/icsc/uploads/40/6415/ES_API_1_0.pdf) support memory registration operations. This allows a user space program to perform a long lived registration of its buffer working space(s) and then transfer into/out-of those buffers without incurring any memory registration overhead. It eliminates the need to copy on Send/Receives and the need for a lazy de-registration algorithm. If you want to find out the state of these extensions, talk to your OS vendor.

* Asynchronous completions. Also standardized by the ICSC Sockets Extensions. This allows a user space program to post work to a QP through a Sockets library and continue processing without ever switching into kernel space. The user space program can then retrieve completions through asynchronous polls.

* RDMA Writes and Reads. Some of us tried to get these into ICSC Sockets Extensions 1.0, but it didn't make the 1.0 cut. Giving the user space program control of RDMA Writes and Reads enables a-priori usage models for small messages that exploit RDMA Write and Read semantics, such as the ability to perform a data transfer to a remote node without invoking a thread at the remote node. The uDAPL and the ICSC IT-API support RDMA Writes and Reads.

* Shared Receive Queues. This enables a more efficient WQE prefetch and buffer model at the receiver.

We now turn to the critique posted by Patrick Geoffray.

Response to Myricom's Geoffray Critique
Please note to conserve space in the list below, the following acronyms are used:

* VIA – Virtual Interface Architecture

* S/R – Send/Receive

* uDAPL – User Direct Access Provider Library

* IT-API – Interconnect Transport API

List of Myricom's Geoffray Critique versus “RDMA” Based Adapter Rebuttal: Critique —> Rebuttal.

1. VIA (1st RDMA standard) faded away. —> We used VIA as the base for IB Release 1.0, uDAPL and IT-API.

2. S/R uses local information for placement; RDMA requires memory registration. —> Out of user space data transfer is what requires memory registration for both S/R and RDMA.

3. MPI S/R requires the ability to match based on several criteria (Sender, Tag, Context). —> MPI S/R can be mapped over an RDMA (IB or iWARP) model's S/R and the matching mechanism can be implemented in software.

4. MPI S/R allows a message to be sent to multiple nodes. —> MPI S/R can use either a reliable (IB RC, iWARP) or unreliable transport (IB UD, UDP. To perform a reliable message send to multiple nodes, the reliable RDMA Model can be used, in which case the adapter performs the reliability checks. Otherwise the unreliable RDMA Model can be used, in which case the reliability checks must be performed in host software, which of course requires host CPU compute cycles. The latter may not be a problem if the host CPU is just doing data transfers, but if its doing other work (e.g. user space program computations), then obviously the reliability checks will increase the program's computation time.

5. MPI S/R allows a message to be sent even if the remote node has no buffer posted. —> MPI S/R can be implemented using an RDMA Model Shared Receive Queue, which the MPI driver can keep full. SRQs can be associated with either a reliable or unreliable QPs.

6. MPI S/R requires ordering between senders. —> When mapping MPI S/R over an RDMA Model's S/R, the software library/driver can add an ordering control to the message to provide ordering between senders.

7. MPI S/R can't make use of zero copy, doesn't state why. Presumably it's because buffers are dynamically registered. —> If the MPI program has a buffer working set, then MPI S/R can use lazy deregistration to avoid the registration overhead.

8. Sockets S/R can't make use of zero copy. —> Myricom's Geoffray statement is false. For programs that use Sockets Extensions 1.0, the user can statically register its user space working set, in one region if its contiguous in VA space, and reuse those buffers without incurring any registration overhead. These registered buffers can then be used to perform zero copy on both S/R and RDMA Writes/Reads. Additionally, the Sockets Direct Protocol (SDP) can be used to exploit RDMA for large messages.

9. To do zero-copy, local side needs to know where it's going to read/write the data on the remote side. —> Myricom's Geoffray statement is false. If Send/Receive is used, the local side doesn't need to know where the data is going in the remote side.

10 MPI sender has to wait for the MPI receiver to be ready before completing the communication and reusing the send buffer. —> Myricom's Geoffray statement is false. If Send/Receive is used, the local side doesn't need to know where the data is going in the remote side.

11. Most MPI implementations that claim zero-copy actually do a memory copy for small messages. The RDMA model does not help in any way. —> Myricom's Geoffray statement is false, the RDMA Model is more than RDMA Writes/Reads. When we created and standardized protocols that use the RDMA Model (SDP, iSER, NFS/RDMA) we observed that for small messages the RDMA Model's S/R mechanism is more efficient than RDMA Write/Reads. However, MVAPICH and Open MPI have implemented mechanisms to do RDMA transfers even for small messages. This does involve pre-registering a set of RDMA buffers and exchanging addresses and keys, but that only happens once during connection setup. Once everything is set up, even small message transfers show benefit of using RDMA, even with the attendant copy in/out of the RDMA buffers. There are questions of scalability with this, but it is a mechanism that is available for those that want to tune their MPI setup to use it.

12. Registration and deregistration provides the lowest overhead for large messages. Memory copies provides the lowest overhead for small messages. —> Myricom's Geoffray statement is false, long-lived registrations provide the lowest overhead.

13. With RDMA Write only one process can safely write into a remote buffer at a time. An RDMA buffer is required for each possible sender, receiver then looks for messages in N-1 locations (N = processes). —> Studies have shown that in distributed, parallel scientific applications, most processes only engage in point-to-point communications with a small number of peer processes (J. S. Vetter and F. Mueller. Communication Characteristics of Large-Scale Scientific Applications for Contemporary Cluster Architectures. In IPDPS, April 2002). This has led MVAPICH and Open MPI to move from fully-connected models to dynamic-connection models which limit the number of reliably-connected processes by using dynamic and adaptive connection management techniques. This, in turn, reduces overall resource usage and avoids the N-1 connection/scalability issues.

14. RDMA is a connected model. (a QP in one process is associated with a QP in a different process), requiring N-1 Receive Queue resources. —> True for 1st generation reliable (IB RC) transports. Not true for 2nd generation reliable (iWARP, IB 1.2 RC) transports, which implement Shared Receive Queues. Not true for unreliable (IB UD, UDP) transports.

15. Shared Receive Queue is inherently an S/R model, perhaps a sign that native RDMA interconnects are slowly migrating to the more efficient Send/Recv programming model. —> Standard RDMA Models have since day 1 supported Send/Receive and RDMA.
Upper level protocols (e.g. SDP, iSER, NFS/RDMA) over “RDMA” have since day 1 supported Send/Receive and RDMA.

16. SRQ does not address the overhead of initially establishing the connections, so a connection-on-demand mechanism is needed to hide the problem. —> Offloading a reliable (IB RC, iWARP) Send/Receive or RDMA transport to an adapter makes sense for long-lived connections. For short lived connections, because of the connection establishment/destruction overhead, its better to either use an offloaded unreliable transport (IB UD, UDP) or a host transport.

17. The RDMA programming model does not fit well with the two-sided semantic constraints of MPI or the Sockets interface. —> The RDMA programming model fits very well with both, as I've described in this rebuttal. For Sockets, I've described how the ICSC Socket Extensions 1.0 and SDP eliminate the memory registration issues Myricom's Geoffray raises. For MPI, both Mvapich and Open MPI have moved beyond N-1 RDMA connections and use dynamic and adaptive mechanisms for managing and restricting RDMA connections to large data transfers and frequently communicating processes. However, perhaps the RDMA programming model does not fit very well for some legacy network adapter implementations.
 
Short Critique on Host Transport Based HPC Adapters
 
There are a number of networking adapters that accelerate the transport layer but do not fully eliminate the transport layer from the host. For instance, layer-2 network accelerations have been available on Ethernet adapters for several years (e.g. checksum offload). In the HPC space some vendors accelerate the transport in the adapter, but still require the host to perform a portion of the transport reliability check processing. Given Myricom's Patrick Geoffray critique, it seems Myrinet adapters perform reliability checks in software running in the host CPU.

Adapters that do not fully eliminate data placement and transport layer functions from the host obviously have a higher CPU utilization cost than those that do. This cost is even higher if the host's transport layer processing must be performed in the kernel. If the adapter fully performs the data placement and transport layer functions, then the CPU overhead can be avoided because the transport completely resides in the adapter.

Does the above mean all adapters that perform a portion of the transport processing in the host are bad? No, Ethernet adapters that provide a layer-2 service work very well for short-lived connections and communications to clients. However, for cluster market segments, adapters that support the RDMA Model are a better fit than legacy adapters that perform a portion of the transport processing in the host.

It is interesting to note that almost twice as many new machines in the top100 are using InfiniBand than Myrinet and that Myrinet market share is being pinched by standard protocols, InfiniBand when high performance is needed and 1 Gbps Ethernet, soon 10 Gbps iWARP Ethernet, otherwise. Additionally, 3 machines in the top 10 use InfiniBand, whereas none use Myrinet. Apparently the RDMA Model scales sufficiently well to meet the needs of the high-end HPC market.

Conclusion
 
It is easy to see how the RDMA Model threatens legacy network adapters that have not evolved to its capabilities. The model fits well with the existing two-sided semantic constraints of MPI and the Sockets interface. It performs even better when the API evolves, such as the ICSC Sockets Extensions 1.0 evolution, to support RDMA Model capabilities, such as memory registration. The performance levels of the RDMA Model have been well published. Legacy network adapter vendors that don't support the RDMA Model usually point to the “inability to scale” myth claiming that for N processes to reliably talk to each other, N-1 process contexts are required in the network adapter. Of course, they often forget to mention that with any reliable transport N-1 process contexts are required somewhere to maintain end-end ordering guarantees. Perhaps the omission occurs, because most of these vendors perform the end-end ordering guarantees in the host CPU, which takes away cycles from the program that uses the adapter.

It is true that history always repeats itself, APIs and protocols are evolving to take advantage of the evolutionary step represented by the RDMA Model. However, like all evolutions, some legacy network adapter architectures will not be able to make the evolutionary step and will continue to struggle with a diminishing cluster market share.

The author would like to thank the following folks for their input during reviews of this article: Brad Benton, Jimmy Hill, Mike Ko, Rick Maule, Bernard Metzler and Claudia Salzberg.

—–

Renato Recio is an IBM Distinguished Engineer and Chief Engineer of IBM eSystems Networks. He was one of the founding and contributing engineers of Future IO (which merged with Next Generation IO to become InfiniBand), InfiniBand, iWARP (RDMA stack over TCP/IP) and iSER (iSCSI Extensions for RDMA). He also contributed to the Sockets Direct Protocol and helped in the founding of the ICSC. He has contributed to the architecture of several IBM RDMA and layer-2 networking adapters. He is currently co-chairing the PCI IO Virtualization Working Group, which is standardizing mechanisms that accelerate IO Virtualization and enable multiple hosts to share multi-root aware PCI Express switches and adapters.

Subscribe to HPCwire's Weekly Update!

Be the most informed person in the room! Stay ahead of the tech trends with industy updates delivered to you every week!

White House Scientific Integrity Report Addresses AI and ML Ethics

January 26, 2022

Earlier this month, the White House Office of Science and Technology Policy (OSTP) Scientific Integrity Task Force released a report titled “Protecting the Integrity of Government Science.” While broad-based and over Read more…

IBM Quantum Debuts Classical Entanglement Forging to Expand Simulation Capabilities

January 26, 2022

IBM last week reported a new technique – entanglement forging – that uses both quantum and classical computing resources to double the size of select simulation problems that can be solved on current quantum computer Read more…

Lenovo Launches Its TruScale HPC as a Service Offering

January 26, 2022

Lenovo today announced TruScale High Performance Computing as a Service (HPCaaS), which it says will offer a “cloud-like experience” to HPC organizations of all sizes. The new HPC-as-a-Service is part of the TruScale Read more…

Ceremorphic Touts Its HPC/AI Silicon Technology as It Exits Stealth

January 25, 2022

In a market still filling with fledging silicon chips, Ceremorphic, Inc. has exited stealth and is telling the world about what it calls its patented new ThreadArch multi-thread processor technology that is intended to h Read more…

Quantum Watch: Neutral Atoms Draw Growing Attention as Promising Qubit Technology

January 25, 2022

Currently, there are many qubit technologies vying for sway in quantum computing. So far, superconducting (IBM, Google) and trapped ion (IonQ, Quantinuum) have dominated the conversation. Microsoft’s proposed topologic Read more…

AWS Solution Channel

Register for the AWS “Speeds n’ Feeds” event on Feb. 9th

Since the debut of the first ‘Beowulf’ cluster in 1994, HPC has been a race between technologists squeezing as much performance as possible from hardware, and scale economics driving mass-production prices to affordable levels. Read more…

Meta’s Massive New AI Supercomputer Will Be ‘World’s Fastest’

January 24, 2022

Fresh off its rebrand last October, Meta (née Facebook) is putting muscle behind its vision of a metaversal future with a massive new AI supercomputer called the AI Research SuperCluster (RSC). Meta says that RSC will b Read more…

Lenovo Launches Its TruScale HPC as a Service Offering

January 26, 2022

Lenovo today announced TruScale High Performance Computing as a Service (HPCaaS), which it says will offer a “cloud-like experience” to HPC organizations of Read more…

Ceremorphic Touts Its HPC/AI Silicon Technology as It Exits Stealth

January 25, 2022

In a market still filling with fledging silicon chips, Ceremorphic, Inc. has exited stealth and is telling the world about what it calls its patented new Thread Read more…

Quantum Watch: Neutral Atoms Draw Growing Attention as Promising Qubit Technology

January 25, 2022

Currently, there are many qubit technologies vying for sway in quantum computing. So far, superconducting (IBM, Google) and trapped ion (IonQ, Quantinuum) have Read more…

Meta’s Massive New AI Supercomputer Will Be ‘World’s Fastest’

January 24, 2022

Fresh off its rebrand last October, Meta (née Facebook) is putting muscle behind its vision of a metaversal future with a massive new AI supercomputer called t Read more…

IBM Watson Health Finally Sold by IBM After 11 Months of Rumors

January 21, 2022

IBM has sold its underachieving IBM Watson Health unit for an undisclosed price tag to a global investment firm after almost a year’s worth of rumors that sai Read more…

Supercomputer Analysis Shows the Atmospheric Reach of the Tonga Eruption

January 21, 2022

On Saturday, an enormous eruption on the volcanic islands of Hunga Tonga and Hunga Haʻapai shook the Pacific Ocean. The explosion, which could be heard six tho Read more…

NSB Issues US State of Science and Engineering 2022 Report

January 20, 2022

This week the National Science Board released its biannual U.S. State of Science and Engineering 2022 report, as required by the NSF Act. Broadly, the report presents a near-term view of S&E based mostly on 2019 data. To a large extent, this year’s edition echoes trends from the last few reports. The U.S. is still a world leader in R&D spending and S&E education... Read more…

Multiverse Targets ‘Quantum Computing for the Masses’

January 19, 2022

The race to deliver quantum computing solutions that shield users from the underlying complexity of quantum computing is heating up quickly. One example is Multiverse Computing, a European company, which today launched the second financial services product in its Singularity product group. The new offering, Fair Price, “delivers a higher accuracy in fair price calculations for financial... Read more…

IonQ Is First Quantum Startup to Go Public; Will It be First to Deliver Profits?

November 3, 2021

On October 1 of this year, IonQ became the first pure-play quantum computing start-up to go public. At this writing, the stock (NYSE: IONQ) was around $15 and its market capitalization was roughly $2.89 billion. Co-founder and chief scientist Chris Monroe says it was fun to have a few of the company’s roughly 100 employees travel to New York to ring the opening bell of the New York Stock... Read more…

US Closes in on Exascale: Frontier Installation Is Underway

September 29, 2021

At the Advanced Scientific Computing Advisory Committee (ASCAC) meeting, held by Zoom this week (Sept. 29-30), it was revealed that the Frontier supercomputer is currently being installed at Oak Ridge National Laboratory in Oak Ridge, Tenn. The staff at the Oak Ridge Leadership... Read more…

AMD Launches Milan-X CPU with 3D V-Cache and Multichip Instinct MI200 GPU

November 8, 2021

At a virtual event this morning, AMD CEO Lisa Su unveiled the company’s latest and much-anticipated server products: the new Milan-X CPU, which leverages AMD’s new 3D V-Cache technology; and its new Instinct MI200 GPU, which provides up to 220 compute units across two Infinity Fabric-connected dies, delivering an astounding 47.9 peak double-precision teraflops. “We're in a high-performance computing megacycle, driven by the growing need to deploy additional compute performance... Read more…

Intel Reorgs HPC Group, Creates Two ‘Super Compute’ Groups

October 15, 2021

Following on changes made in June that moved Intel’s HPC unit out of the Data Platform Group and into the newly created Accelerated Computing Systems and Graphics (AXG) business unit, led by Raja Koduri, Intel is making further updates to the HPC group and announcing... Read more…

Nvidia Buys HPC Cluster Management Company Bright Computing

January 10, 2022

Graphics chip powerhouse Nvidia today announced that it has acquired HPC cluster management company Bright Computing for an undisclosed sum. Unlike Nvidia’s bid to purchase semiconductor IP company Arm, which has been stymied by regulatory challenges, the Bright deal is a straightforward acquisition that aims to expand... Read more…

D-Wave Embraces Gate-Based Quantum Computing; Charts Path Forward

October 21, 2021

Earlier this month D-Wave Systems, the quantum computing pioneer that has long championed quantum annealing-based quantum computing (and sometimes taken heat fo Read more…

Killer Instinct: AMD’s Multi-Chip MI200 GPU Readies for a Major Global Debut

October 21, 2021

AMD’s next-generation supercomputer GPU is on its way – and by all appearances, it’s about to make a name for itself. The AMD Radeon Instinct MI200 GPU (a successor to the MI100) will, over the next year, begin to power three massive systems on three continents: the United States’ exascale Frontier system; the European Union’s pre-exascale LUMI system; and Australia’s petascale Setonix system. Read more…

Three Chinese Exascale Systems Detailed at SC21: Two Operational and One Delayed

November 24, 2021

Details about two previously rumored Chinese exascale systems came to light during last week’s SC21 proceedings. Asked about these systems during the Top500 media briefing on Monday, Nov. 15, list author and co-founder Jack Dongarra indicated he was aware of some very impressive results, but withheld comment when asked directly if he had... Read more…

Leading Solution Providers

Contributors

Lessons from LLVM: An SC21 Fireside Chat with Chris Lattner

December 27, 2021

Today, the LLVM compiler infrastructure world is essentially inescapable in HPC. But back in the 2000 timeframe, LLVM (low level virtual machine) was just getting its start as a new way of thinking about how to overcome shortcomings in the Java Virtual Machine. At the time, Chris Lattner was a graduate student of... Read more…

2021 Gordon Bell Prize Goes to Exascale-Powered Quantum Supremacy Challenge

November 18, 2021

Today at the hybrid virtual/in-person SC21 conference, the organizers announced the winners of the 2021 ACM Gordon Bell Prize: a team of Chinese researchers leveraging the new exascale Sunway system to simulate quantum circuits. The Gordon Bell Prize, which comes with an award of $10,000 courtesy of HPC pioneer Gordon Bell, is awarded annually... Read more…

Meta’s Massive New AI Supercomputer Will Be ‘World’s Fastest’

January 24, 2022

Fresh off its rebrand last October, Meta (née Facebook) is putting muscle behind its vision of a metaversal future with a massive new AI supercomputer called t Read more…

Nvidia Defends Arm Acquisition Deal: a ‘Once-in-a-Generation Opportunity’

January 13, 2022

GPU-maker Nvidia is continuing to try to keep its proposed acquisition of British chip IP vendor Arm Ltd. alive, despite continuing concerns from several governments around the world. In its latest action, Nvidia filed a 29-page response to the U.K. government to point out a list of potential benefits of the proposed $40 billion deal. Read more…

Julia Update: Adoption Keeps Climbing; Is It a Python Challenger?

January 13, 2021

The rapid adoption of Julia, the open source, high level programing language with roots at MIT, shows no sign of slowing according to data from Julialang.org. I Read more…

Top500: No Exascale, Fugaku Still Reigns, Polaris Debuts at #12

November 15, 2021

No exascale for you* -- at least, not within the High-Performance Linpack (HPL) territory of the latest Top500 list, issued today from the 33rd annual Supercomputing Conference (SC21), held in-person in St. Louis, Mo., and virtually, from Nov. 14–19. "We were hoping to have the first exascale system on this list but that didn’t happen," said Top500 co-author... Read more…

TACC Unveils Lonestar6 Supercomputer

November 1, 2021

The Texas Advanced Computing Center (TACC) is unveiling its latest supercomputer: Lonestar6, a three peak petaflops Dell system aimed at supporting researchers Read more…

10nm, 7nm, 5nm…. Should the Chip Nanometer Metric Be Replaced?

June 1, 2020

The biggest cool factor in server chips is the nanometer. AMD beating Intel to a CPU built on a 7nm process node* – with 5nm and 3nm on the way – has been i Read more…

  • arrow
  • Click Here for More Headlines
  • arrow
HPCwire