ClearSpeed Looks for Traction With Cooler FLOPS

By Michael Feldman

September 29, 2006

The commoditization of high performance computing has driven the expansion of this market rather dramatically in recent years. IDC reported year-to-year growth of 23 percent in 2005. High-volume x86 processors, memory chips, and open source software are all working to reduce the price of supercomputing. However, other forces are at work that are driving costs in the other direction. One aspect that has gotten much press lately is the increasing amounts of energy and cooling required to support all this “cheap” computing.

A significant portion of that energy is used to compute floating point operations — the heart of high performance technical computing — using relatively inefficient general-purpose processors. Thus the recent interest in floating point acceleration from ClearSpeed coprocessors, graphics processing units (GPUs) and the Cell processors. While much attention has been focused on the latter two in recent months, ClearSpeed is seen by some as the dark horse in the race to better floating point performance. According to Stephen McKinnon, ClearSpeed's new COO, the company is uniquely focused on coprocessor floating point acceleration for the HPC marketplace and believes it has the roadmap to keep it ahead of potential rivals for the foreseeable future.

“We're in a position where there are lots of companies sniffing around our technologies,” observes McKinnon. “Some of them are doing it because they're tire-kickers, others are doing it because they want to keep their finger on the pulse of what's going on and some are doing it because they have a clear and present need for better technology. I've been working very diligently with my business development organization to make sure we make we figure out which prospect is which.”

ClearSpeed's commodity rivals, GPUs and the Cell processor, represent high-volume, low-cost solutions that offer outstanding levels of floating point performance. But from ClearSpeed's perspective, it sees its own acceleration technology much differently from these other two solutions. Using the performance-per-watt mantra, the company is attempting to distance itself from its commodity competition.

McKinnon points out that the fundamental architectures of GPUs and the current Cell implementation are single precision floating point, not double precision, which is the standard in the HPC world. In addition, they are not low-power devices. Some of the latest ATI GPUs consume hundreds of watts of electricity.

“If you want 250 frames per second in 32-bit/pixel graphics so you can see your monsters explode and see the blood fly all over the screen — gorgeous,” McKinnon exclaims. “But if you want to put several thousand of these in a machine room doing seismic data exploration, it's the wrong device. You'll boil up every power supply you've got.”

“GPUs are called GPUs because they're graphic processing units,” adds McKinnon. “They have been beautifully designed for outstanding graphics acceleration. And you can use them to do floating point acceleration. But they aren't designed to do that and they don't do it half as well as a dedicated device does. In the same way, you wouldn't use a ClearSpeed board to do graphics acceleration.”

In the case of the Cell, McKinnon believes it is actually less well-designed for acceleration than GPUs because it's a stand-alone processor. While ClearSpeed provides a dedicated coprocessor for CPU speed-up, the Cell code must be run independently from the host, complicating the software model.

“Cell has a similar legacy,” says McKinnon. “Again, a great device for doing what it was designed to do. And obviously you can use it in other environments, but that's not what it was designed for.”

ClearSpeed's Advance board, which hosts dual CSX600 coprocessors, represents the company's current HPC accelerator offering. Each CSX600 provides 25 GFLOPS of single or double precision performance while using only 10 watts of power. The coprocessor contains an array of 96 processing elements, each containing multiple processing units that have a high level of internal instruction and data parallelism. The Advance board provides 50 GFLOPS of performance and dissipates approximately 25 watts.

The company offers a software development kit (SDK) that contain libraries, tools and documentation that is used to develop code for the Advance board. The current libraries provide an API for a variety of functions including random number, trignometric, exponentiation, DGEMM and FFT. ClearSpeed admits that the SDK is at a “beta” stage of maturity, but plans for more extensive support over the next six months.

“We have found customers who are ready, willing and able to take our products at the current level of maturity and work with us to help them achieve the technical solution in their current environments,” explains McKinnon. “So I would describe our current condition as: we are learning how to run. Some very friendly customers are helping us do that.”

One group that ClearSpeed is targeting for the future is the financial services community. Using Monte Carlo simulations for a portfolio risk management application, they have demonstrated a performance increase of more than 4X by using their accelerator boards (using 40 watts less power per board than a CPU-only based solution). With the time-sensitive nature of managing portfolios with real-time data, faster solutions can yield real competive advantages. According to McKinnon, ClearSpeed technology evaluations are currently ongoing in a number of prominent financial services companies, based in New York and London. He added that they are working on similar types of accleration solutions for oil and gas customers.

Due to the proprietary nature of the work in the financial services and oil & gas industries, these types of customers do a great deal of in-house code development, so they are comfortable using the low-level ClearSpeed libraries to develop their own code. Other types of users, such as you would find in the national labs, also prefer to do their cutting-edge work at the device API level.

“That's a great market and that's our first market,” says McKinnon. “Our product is mature enough to be absolutely viable and relevant in that market. But later we are planning to have solutions for a broader stream of users — in university research environments or in smaller financial services or other environments, where they don't have the programming skills or the programming infrastructure in place to develop their own solution.”

When they first shipped the ClearSpeed technology for their early deployments, such as the Tokyo Institute of Technology  supercomputer installation, all the customer received were boards along with the low-level libaries. Now they are shipping the beta version of their software development environment, which provides a better programming environment along with debugging support. In the next three to six months, they plan to complete the product, offering a full-featured solution for in-house HPC developers.

But over the next year, the goal is to provide a plug-and-play solution. By attracting software vendors that are willing to integrate their code with the ClearSpeed libraries, customers will be able to use the accelerator hardware with little if any application code changes. Ideally, ClearSpeed would like users to be able to use tools like Mathematica and MATLAB transparently with their boards.

Within the same time period, they're planning to launch upgraded hardware. The next version of their boards will support PCIe (currently supports PCI-X). This week at the Intel Developer Forum, the company announced it is also supporting the “Geneseo” proposal to extend PCIe. Although there is no public roadmap beyond PCI, the company is also investigating other processor bus interconnects with the major chip manufacturers.

In addition, ClearSpeed is already developing the next generation of their coprocessor technology, which promises greater performance. Says McKinnon: “I can confidently say that within 12 months, we're going to be offering four times the performance that we are today.”

That would imply the production of boards providing 200 GFLOPS, targeting customers with the greatest HPC needs — national labs, financial institutions and seismic exploration users. This group is willing to pay premium prices for the fastest acceleration they can obtain.

A larger community of users with more modest requirements, for example university computing labs for biology and chemistry applications, will be content with something less than cutting-edge performance. ClearSpeed intends to go after them as well, by providing a lower cost product. McKinnon says this offering will be introduced within two years. Here ClearSpeed is envisioning a higher volume market, on the order of millions of units. At that level of production, they might start to resemble a more commodity-like solution.

“There's going to be a very large community of people who will need the best and lowest power consumption for numeric acceleration and that's where we'll be playing,” concludes McKinnon. “We believe we will be the commodity supplier for the high performance acceleration marketplace.”

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