Why Pretend?

By Christopher C. Aycock, MS

October 6, 2006

InfiniBand and iWARP have industry heavyweights behind them, to be sure. But this kind of smug satisfaction has only led to a case of the Emperor's New Clothes in which no one is willing to admit to the inadequacy of RDMA in general and VIA in particular.

Kernel Bypass, Zero Copy, and Asynchronous Communication

Networks are a shared resource. Traditional networks such as Ethernet require that the resource be protected by the kernel, which presents a tremendous performance bottleneck when latency is an issue. Furthermore, data is copied to and from pre-allocated buffers, which can hurt bandwidth for large messages.

Many of today's high-performance networks from vendors such as Myricom and Quadrics handle the protection across process boundaries directly through the network interface card (NIC). This setup bypasses the kernel and lets communication occur at the user level, thereby removing the bottleneck of mode switching.

Most modern high-performance networks also have direct memory access (DMA) in which the NIC accesses main memory directly while the CPU is free to perform other tasks. DMA not only eliminates copying, but also permits communication to overlap with computation. This facet is similar to prefetching in the cache as it reduces the effective latency. Taking advantage of this feature in an application only requires asynchronous communication, which is represented as multithreaded designs in Sockets or as nonblocking primitives in MPI — MPI_Isend() and MPI_Irecv().

Send/Receive and RDMA

Most of the above capabilities are available through the widely-used two-sided semantics of Send/Receive communication. That is, the communication runs entirely at the user level, allows the local (sending) node to act without copying, and frees the CPU to perform other tasks. Send/Receive does have a drawback though: the remote (receiving) node must copy the message to its final destination; the benefit of zero-copy only exists for the sending node.

With one-sided semantics in remote direct memory access (RDMA), the receiving NIC uses DMA to place the data into a buffer that has been specified by the sending node. RDMA extends zero-copy benefits to the remote node.

For the NIC to access the data through RDMA, the user's page must actually be in memory and not on the disk. Pinning the page to physical memory requires a memory registration, which invokes the operating system. This is actually an expensive procedure as it requires the kernel and is exactly what high-performance networks are supposed to avoid!

Furthermore, the sending node must know the destination memory address on the receiving node. Most applications, such as those written in Sockets or MPI, will require that this information be exchanged prior to communication. The synchronization here is performed through the Send/Receive semantics in a rendezvous protocol, which adds even more overhead.

Workarounds for RDMA

It is possible to overcome RDMA's shortcomings and still realize the benefit of zero-copy communication on the remote node. Certain supercomputers such as the Blue Gene rely on a custom lightweight kernel that only runs one process; because there is no paging, there is no requirement for memory registration.

Alternatively, QsNet works by patching the kernel so that the NIC may access the appropriate data once the page has been loaded into memory. Patches are developed for very specific versions of the kernel based on assumptions regarding the Linux API. Given this level of required specificity, administering a cluster that involves kernel patches can be quite tedious.

As for InfiniBand, it is possible to rely on caching techniques. That is, if a certain memory region will be remotely accessed multiple times, then the software — an implementation of MPI, for example — may build a table of memory registrations on the receiving node.

In any case, synchronization remains unavoidable in most programs. The sending node must know the destination memory address on the remote node to perform RDMA. There are some special cases where the address will be known ahead of time, as in MPI-2's remote memory access functions — MPI_Put() and MPI_Get(). But these routines are not widely used and represent a niche application.

Specific Issues with the Virtual Interface Architecture (VIA)

MVAPICH is a port of MPICH to InfiniBand maintained by D. K. Panda's team at Ohio State University. This implementation provides a reference for other communication layers on VIA-based networks, such as InfiniBand and iWARP. Of particular interest is that OSU's collection of related research papers contain a series of design patterns for software on RDMA networks.

Design patterns are best-practice architecture that permit reuse of a solution to a common programming problem. Some language researchers, such as Paul Graham and Peter Norvig, believe that design patterns are really a sign that the underlying language is incomplete. After all, a pattern implies automation, and automation implies a machine.

By extension, the design patterns from OSU demonstrate that InfiniBand lacks the foundations that would best serve most of its users. Now some designers, such as John Hennessy and David Patterson, believe that an architecture should provide primitives and not solutions. But given that the (committee-defined) InfiniBand standard is over a thousand pages long, it should be fairly obvious which view the IB Trade Association holds.

In contrast, both the Elan and MX libraries (for QsNet and Myrinet, respectively) have been specifically built to present the common functionality required in most applications. The solution-oriented VIA community should have done the same with their libraries, such DAPL and the OpenFabrics verbs API.

Personal Notes

I was motivated to write this article after reading “A Tutorial of the RDMA Model” from IBM's Renato Recio, which in turn was a response to “A Critique of RDMA” from Myricom's Patrick Geoffray. I got the impression that Recio was writing to protect the image of VIA rather than provide a sound rebuttal to Geoffray's technical arguments about RDMA. For example, Geoffray's criticism that RDMA is not adequate for Sockets is met with the response that the user can rely on Extended Sockets or the Sockets Direct Protocol (SDP). Extended Sockets is a different library from Sockets, albeit somewhat similar; SDP is a protocol used above and beyond the RDMA paradigm. Geoffray essentially said that RDMA is handicapped and Recio responded that RDMA has a choice of crutches.

What is particularly telling is that Recio fell back on the old technique of using sales volume to justify technical soundness. He states, “it is interesting to note that almost twice as many new machines in the top100 are using InfiniBand than Myrinet.” This is like saying that Titanic was the best movie ever produced since it sold the most tickets. If IBM really did believe the sales-volume pitch, it would stop making POWER chips and simply bundle x86 with its servers.

I wrote this article as a knowledgeable end user; I will leave the marketing brochures to the vendors. At Oxford we used to believe that RDMA was a godsend for the BSP-style programming found in MPI-2 or Cray's SHMEM. Indeed, Geoffray's article states that RDMA networks “can be leveraged successfully for one-sided programming paradigms.” After having studied both the paradigms and the networks, I have come to the conclusion that models such as the partitioned global address space languages are really best suited for ccNUMA machines. And indeed, that is what RDMA is: a crude approximation of a non-commodity machine useful only for niche applications.

Sockets work just fine on vanilla Ethernet. MPI works on Ethernet. Google's MapReduce works on Ethernet. Maybe this is the architecture we should be building on.

The author would like to thank Richard Brent and Peter Strazdins for their comments on an earlier draft of this article.

—–

Christopher C. Aycock is wrapping up his PhD from Oxford University, where his thesis topic is in communications programming paradigms for high-performance networks. He is currently a visiting fellow at the Australian National University and can be reached via chris@hpcanswers.com.

Subscribe to HPCwire's Weekly Update!

Be the most informed person in the room! Stay ahead of the tech trends with industy updates delivered to you every week!

Energy Exascale Earth System Model Version 2 Promises Twice the Speed

October 18, 2021

The Energy Exascale Earth System Model (E3SM) is an ongoing Department of Energy (DOE) earth system modeling, simulation and prediction project aiming to “assert and maintain an international scientific leadership posi Read more…

Intel Reorgs HPC Group, Creates Two ‘Super Compute’ Groups

October 15, 2021

Following on changes made in June that moved Intel’s HPC unit out of the Data Platform Group and into the newly created Accelerated Computing Systems and Graphics (AXG) business unit, led by Raja Koduri, Intel is making further updates to the HPC group and announcing... Read more…

Royalty-free stock illustration ID: 1938746143

MosaicML, Led by Naveen Rao, Comes Out of Stealth Aiming to Ease Model Training

October 15, 2021

With more and more enterprises turning to AI for a myriad of tasks, companies quickly find out that training AI models is expensive, difficult and time-consuming. Finding a new approach to deal with those cascading challenges is the aim of a new startup, MosaicML, that just came out of stealth... Read more…

NSF Awards $11M to SDSC, MIT and Univ. of Oregon to Secure the Internet

October 14, 2021

From a security standpoint, the internet is a problem. The infrastructure developed decades ago has cracked, leaked and been patched up innumerable times, leaving vulnerabilities that are difficult to address due to cost Read more…

SC21 Announces Science and Beyond Plenary: the Intersection of Ethics and HPC

October 13, 2021

The Intersection of Ethics and HPC will be the guiding topic of SC21's Science & Beyond plenary, inspired by the event tagline of the same name. The evening event will be moderated by Daniel Reed with panelists Crist Read more…

AWS Solution Channel

Cost optimizing Ansys LS-Dyna on AWS

Organizations migrate their high performance computing (HPC) workloads from on-premises infrastructure to Amazon Web Services (AWS) for advantages such as high availability, elastic capacity, latest processors, storage, and networking technologies; Read more…

Quantum Workforce – NSTC Report Highlights Need for International Talent

October 13, 2021

Attracting and training the needed quantum workforce to fuel the ongoing quantum information sciences (QIS) revolution is a hot topic these days. Last week, the U.S. National Science and Technology Council issued a report – The Role of International Talent in Quantum Information Science... Read more…

Intel Reorgs HPC Group, Creates Two ‘Super Compute’ Groups

October 15, 2021

Following on changes made in June that moved Intel’s HPC unit out of the Data Platform Group and into the newly created Accelerated Computing Systems and Graphics (AXG) business unit, led by Raja Koduri, Intel is making further updates to the HPC group and announcing... Read more…

Royalty-free stock illustration ID: 1938746143

MosaicML, Led by Naveen Rao, Comes Out of Stealth Aiming to Ease Model Training

October 15, 2021

With more and more enterprises turning to AI for a myriad of tasks, companies quickly find out that training AI models is expensive, difficult and time-consuming. Finding a new approach to deal with those cascading challenges is the aim of a new startup, MosaicML, that just came out of stealth... Read more…

Quantum Workforce – NSTC Report Highlights Need for International Talent

October 13, 2021

Attracting and training the needed quantum workforce to fuel the ongoing quantum information sciences (QIS) revolution is a hot topic these days. Last week, the U.S. National Science and Technology Council issued a report – The Role of International Talent in Quantum Information Science... Read more…

Eni Returns to HPE for ‘HPC4’ Refresh via GreenLake

October 13, 2021

Italian energy company Eni is upgrading its HPC4 system with new gear from HPE that will be installed in Eni’s Green Data Center in Ferrera Erbognone (a provi Read more…

The Blueprint for the National Strategic Computing Reserve

October 12, 2021

Over the last year, the HPC community has been buzzing with the possibility of a National Strategic Computing Reserve (NSCR). An in-utero brainchild of the COVID-19 High-Performance Computing Consortium, an NSCR would serve as a Merchant Marine for urgent computing... Read more…

UCLA Researchers Report Largest Chiplet Design and Early Prototyping

October 12, 2021

What’s the best path forward for large-scale chip/system integration? Good question. Cerebras has set a high bar with its wafer scale engine 2 (WSE-2); it has 2.6 trillion transistors, including 850,000 cores, and was fabricated using TSMC’s 7nm process on a roughly 8” x 8” silicon footprint. Read more…

What’s Next for EuroHPC: an Interview with EuroHPC Exec. Dir. Anders Dam Jensen

October 7, 2021

One year after taking the post as executive director of the EuroHPC JU, Anders Dam Jensen reviews the project's accomplishments and details what's ahead as EuroHPC's operating period has now been extended out to the year 2027. Read more…

University of Bath Unveils Janus, an Azure-Based Cloud HPC Environment

October 6, 2021

The University of Bath is upgrading its HPC infrastructure, which it says “supports a growing and wide range of research activities across the University.” Read more…

Ahead of ‘Dojo,’ Tesla Reveals Its Massive Precursor Supercomputer

June 22, 2021

In spring 2019, Tesla made cryptic reference to a project called Dojo, a “super-powerful training computer” for video data processing. Then, in summer 2020, Tesla CEO Elon Musk tweeted: “Tesla is developing a [neural network] training computer... Read more…

Enter Dojo: Tesla Reveals Design for Modular Supercomputer & D1 Chip

August 20, 2021

Two months ago, Tesla revealed a massive GPU cluster that it said was “roughly the number five supercomputer in the world,” and which was just a precursor to Tesla’s real supercomputing moonshot: the long-rumored, little-detailed Dojo system. Read more…

Esperanto, Silicon in Hand, Champions the Efficiency of Its 1,092-Core RISC-V Chip

August 27, 2021

Esperanto Technologies made waves last December when it announced ET-SoC-1, a new RISC-V-based chip aimed at machine learning that packed nearly 1,100 cores onto a package small enough to fit six times over on a single PCIe card. Now, Esperanto is back, silicon in-hand and taking aim... Read more…

CentOS Replacement Rocky Linux Is Now in GA and Under Independent Control

June 21, 2021

The Rocky Enterprise Software Foundation (RESF) is announcing the general availability of Rocky Linux, release 8.4, designed as a drop-in replacement for the soon-to-be discontinued CentOS. The GA release is launching six-and-a-half months... Read more…

US Closes in on Exascale: Frontier Installation Is Underway

September 29, 2021

At the Advanced Scientific Computing Advisory Committee (ASCAC) meeting, held by Zoom this week (Sept. 29-30), it was revealed that the Frontier supercomputer is currently being installed at Oak Ridge National Laboratory in Oak Ridge, Tenn. The staff at the Oak Ridge Leadership... Read more…

Intel Completes LLVM Adoption; Will End Updates to Classic C/C++ Compilers in Future

August 10, 2021

Intel reported in a blog this week that its adoption of the open source LLVM architecture for Intel’s C/C++ compiler is complete. The transition is part of In Read more…

Intel Reorgs HPC Group, Creates Two ‘Super Compute’ Groups

October 15, 2021

Following on changes made in June that moved Intel’s HPC unit out of the Data Platform Group and into the newly created Accelerated Computing Systems and Graphics (AXG) business unit, led by Raja Koduri, Intel is making further updates to the HPC group and announcing... Read more…

Hot Chips: Here Come the DPUs and IPUs from Arm, Nvidia and Intel

August 25, 2021

The emergence of data processing units (DPU) and infrastructure processing units (IPU) as potentially important pieces in cloud and datacenter architectures was Read more…

Leading Solution Providers

Contributors

AMD-Xilinx Deal Gains UK, EU Approvals — China’s Decision Still Pending

July 1, 2021

AMD’s planned acquisition of FPGA maker Xilinx is now in the hands of Chinese regulators after needed antitrust approvals for the $35 billion deal were receiv Read more…

HPE Wins $2B GreenLake HPC-as-a-Service Deal with NSA

September 1, 2021

In the heated, oft-contentious, government IT space, HPE has won a massive $2 billion contract to provide HPC and AI services to the United States’ National Security Agency (NSA). Following on the heels of the now-canceled $10 billion JEDI contract (reissued as JWCC) and a $10 billion... Read more…

Julia Update: Adoption Keeps Climbing; Is It a Python Challenger?

January 13, 2021

The rapid adoption of Julia, the open source, high level programing language with roots at MIT, shows no sign of slowing according to data from Julialang.org. I Read more…

10nm, 7nm, 5nm…. Should the Chip Nanometer Metric Be Replaced?

June 1, 2020

The biggest cool factor in server chips is the nanometer. AMD beating Intel to a CPU built on a 7nm process node* – with 5nm and 3nm on the way – has been i Read more…

Quantum Roundup: IBM, Rigetti, Phasecraft, Oxford QC, China, and More

July 13, 2021

IBM yesterday announced a proof for a quantum ML algorithm. A week ago, it unveiled a new topology for its quantum processors. Last Friday, the Technical Univer Read more…

The Latest MLPerf Inference Results: Nvidia GPUs Hold Sway but Here Come CPUs and Intel

September 22, 2021

The latest round of MLPerf inference benchmark (v 1.1) results was released today and Nvidia again dominated, sweeping the top spots in the closed (apples-to-ap Read more…

Frontier to Meet 20MW Exascale Power Target Set by DARPA in 2008

July 14, 2021

After more than a decade of planning, the United States’ first exascale computer, Frontier, is set to arrive at Oak Ridge National Laboratory (ORNL) later this year. Crossing this “1,000x” horizon required overcoming four major challenges: power demand, reliability, extreme parallelism and data movement. Read more…

Intel Unveils New Node Names; Sapphire Rapids Is Now an ‘Intel 7’ CPU

July 27, 2021

What's a preeminent chip company to do when its process node technology lags the competition by (roughly) one generation, but outmoded naming conventions make i Read more…

  • arrow
  • Click Here for More Headlines
  • arrow
HPCwire