Why Pretend?

By Christopher C. Aycock, MS

October 6, 2006

InfiniBand and iWARP have industry heavyweights behind them, to be sure. But this kind of smug satisfaction has only led to a case of the Emperor's New Clothes in which no one is willing to admit to the inadequacy of RDMA in general and VIA in particular.

Kernel Bypass, Zero Copy, and Asynchronous Communication

Networks are a shared resource. Traditional networks such as Ethernet require that the resource be protected by the kernel, which presents a tremendous performance bottleneck when latency is an issue. Furthermore, data is copied to and from pre-allocated buffers, which can hurt bandwidth for large messages.

Many of today's high-performance networks from vendors such as Myricom and Quadrics handle the protection across process boundaries directly through the network interface card (NIC). This setup bypasses the kernel and lets communication occur at the user level, thereby removing the bottleneck of mode switching.

Most modern high-performance networks also have direct memory access (DMA) in which the NIC accesses main memory directly while the CPU is free to perform other tasks. DMA not only eliminates copying, but also permits communication to overlap with computation. This facet is similar to prefetching in the cache as it reduces the effective latency. Taking advantage of this feature in an application only requires asynchronous communication, which is represented as multithreaded designs in Sockets or as nonblocking primitives in MPI — MPI_Isend() and MPI_Irecv().

Send/Receive and RDMA

Most of the above capabilities are available through the widely-used two-sided semantics of Send/Receive communication. That is, the communication runs entirely at the user level, allows the local (sending) node to act without copying, and frees the CPU to perform other tasks. Send/Receive does have a drawback though: the remote (receiving) node must copy the message to its final destination; the benefit of zero-copy only exists for the sending node.

With one-sided semantics in remote direct memory access (RDMA), the receiving NIC uses DMA to place the data into a buffer that has been specified by the sending node. RDMA extends zero-copy benefits to the remote node.

For the NIC to access the data through RDMA, the user's page must actually be in memory and not on the disk. Pinning the page to physical memory requires a memory registration, which invokes the operating system. This is actually an expensive procedure as it requires the kernel and is exactly what high-performance networks are supposed to avoid!

Furthermore, the sending node must know the destination memory address on the receiving node. Most applications, such as those written in Sockets or MPI, will require that this information be exchanged prior to communication. The synchronization here is performed through the Send/Receive semantics in a rendezvous protocol, which adds even more overhead.

Workarounds for RDMA

It is possible to overcome RDMA's shortcomings and still realize the benefit of zero-copy communication on the remote node. Certain supercomputers such as the Blue Gene rely on a custom lightweight kernel that only runs one process; because there is no paging, there is no requirement for memory registration.

Alternatively, QsNet works by patching the kernel so that the NIC may access the appropriate data once the page has been loaded into memory. Patches are developed for very specific versions of the kernel based on assumptions regarding the Linux API. Given this level of required specificity, administering a cluster that involves kernel patches can be quite tedious.

As for InfiniBand, it is possible to rely on caching techniques. That is, if a certain memory region will be remotely accessed multiple times, then the software — an implementation of MPI, for example — may build a table of memory registrations on the receiving node.

In any case, synchronization remains unavoidable in most programs. The sending node must know the destination memory address on the remote node to perform RDMA. There are some special cases where the address will be known ahead of time, as in MPI-2's remote memory access functions — MPI_Put() and MPI_Get(). But these routines are not widely used and represent a niche application.

Specific Issues with the Virtual Interface Architecture (VIA)

MVAPICH is a port of MPICH to InfiniBand maintained by D. K. Panda's team at Ohio State University. This implementation provides a reference for other communication layers on VIA-based networks, such as InfiniBand and iWARP. Of particular interest is that OSU's collection of related research papers contain a series of design patterns for software on RDMA networks.

Design patterns are best-practice architecture that permit reuse of a solution to a common programming problem. Some language researchers, such as Paul Graham and Peter Norvig, believe that design patterns are really a sign that the underlying language is incomplete. After all, a pattern implies automation, and automation implies a machine.

By extension, the design patterns from OSU demonstrate that InfiniBand lacks the foundations that would best serve most of its users. Now some designers, such as John Hennessy and David Patterson, believe that an architecture should provide primitives and not solutions. But given that the (committee-defined) InfiniBand standard is over a thousand pages long, it should be fairly obvious which view the IB Trade Association holds.

In contrast, both the Elan and MX libraries (for QsNet and Myrinet, respectively) have been specifically built to present the common functionality required in most applications. The solution-oriented VIA community should have done the same with their libraries, such DAPL and the OpenFabrics verbs API.

Personal Notes

I was motivated to write this article after reading “A Tutorial of the RDMA Model” from IBM's Renato Recio, which in turn was a response to “A Critique of RDMA” from Myricom's Patrick Geoffray. I got the impression that Recio was writing to protect the image of VIA rather than provide a sound rebuttal to Geoffray's technical arguments about RDMA. For example, Geoffray's criticism that RDMA is not adequate for Sockets is met with the response that the user can rely on Extended Sockets or the Sockets Direct Protocol (SDP). Extended Sockets is a different library from Sockets, albeit somewhat similar; SDP is a protocol used above and beyond the RDMA paradigm. Geoffray essentially said that RDMA is handicapped and Recio responded that RDMA has a choice of crutches.

What is particularly telling is that Recio fell back on the old technique of using sales volume to justify technical soundness. He states, “it is interesting to note that almost twice as many new machines in the top100 are using InfiniBand than Myrinet.” This is like saying that Titanic was the best movie ever produced since it sold the most tickets. If IBM really did believe the sales-volume pitch, it would stop making POWER chips and simply bundle x86 with its servers.

I wrote this article as a knowledgeable end user; I will leave the marketing brochures to the vendors. At Oxford we used to believe that RDMA was a godsend for the BSP-style programming found in MPI-2 or Cray's SHMEM. Indeed, Geoffray's article states that RDMA networks “can be leveraged successfully for one-sided programming paradigms.” After having studied both the paradigms and the networks, I have come to the conclusion that models such as the partitioned global address space languages are really best suited for ccNUMA machines. And indeed, that is what RDMA is: a crude approximation of a non-commodity machine useful only for niche applications.

Sockets work just fine on vanilla Ethernet. MPI works on Ethernet. Google's MapReduce works on Ethernet. Maybe this is the architecture we should be building on.

The author would like to thank Richard Brent and Peter Strazdins for their comments on an earlier draft of this article.

—–

Christopher C. Aycock is wrapping up his PhD from Oxford University, where his thesis topic is in communications programming paradigms for high-performance networks. He is currently a visiting fellow at the Australian National University and can be reached via chris@hpcanswers.com.

Subscribe to HPCwire's Weekly Update!

Be the most informed person in the room! Stay ahead of the tech trends with industy updates delivered to you every week!

Scalable Informatics Ceases Operations

March 23, 2017

On the same day we reported on the uncertain future for HPC compiler company PathScale, we are sad to learn that another HPC vendor, Scalable Informatics, is closing its doors. Read more…

By Tiffany Trader

‘Strategies in Biomedical Data Science’ Advances IT-Research Synergies

March 23, 2017

“Strategies in Biomedical Data Science: Driving Force for Innovation” by Jay A. Etchings is both an introductory text and a field guide for anyone working with biomedical data. Read more…

By Tiffany Trader

HPC Compiler Company PathScale Seeks Life Raft

March 23, 2017

HPCwire has learned that HPC compiler company PathScale has fallen on difficult times and is asking the community for help or actively seeking a buyer for its assets. Read more…

By Tiffany Trader

Google Launches New Machine Learning Journal

March 22, 2017

On Monday, Google announced plans to launch a new peer review journal and “ecosystem” Read more…

By John Russell

HPE Extreme Performance Solutions

HFT Firms Turn to Co-Location to Gain Competitive Advantage

High-frequency trading (HFT) is a high-speed, high-stakes world where every millisecond matters. Finding ways to execute trades faster than the competition translates directly to greater revenue for firms, brokerages, and exchanges. Read more…

Swiss Researchers Peer Inside Chips with Improved X-Ray Imaging

March 22, 2017

Peering inside semiconductor chips using x-ray imaging isn’t new, but the technique hasn’t been especially good or easy to accomplish. Read more…

By John Russell

LANL Simulation Shows Massive Black Holes Break ‘Speed Limit’

March 21, 2017

A new computer simulation based on codes developed at Los Alamos National Laboratory (LANL) is shedding light on how supermassive black holes could have formed in the early universe contrary to most prior models which impose a limit on how fast these massive ‘objects’ can form. Read more…

Quantum Bits: D-Wave and VW; Google Quantum Lab; IBM Expands Access

March 21, 2017

For a technology that’s usually characterized as far off and in a distant galaxy, quantum computing has been steadily picking up steam. Read more…

By John Russell

Intel Ships Drives Based on 3D XPoint Non-volatile Memory

March 20, 2017

Intel Corp. has begun shipping new storage drives based on its 3D XPoint non-volatile memory technology as it targets data-driven workloads. Intel’s new Optane solid-state drives, designated P4800X, seek to combine the attributes of memory and storage in the same device. Read more…

By George Leopold

HPC Compiler Company PathScale Seeks Life Raft

March 23, 2017

HPCwire has learned that HPC compiler company PathScale has fallen on difficult times and is asking the community for help or actively seeking a buyer for its assets. Read more…

By Tiffany Trader

Quantum Bits: D-Wave and VW; Google Quantum Lab; IBM Expands Access

March 21, 2017

For a technology that’s usually characterized as far off and in a distant galaxy, quantum computing has been steadily picking up steam. Read more…

By John Russell

Trump Budget Targets NIH, DOE, and EPA; No Mention of NSF

March 16, 2017

President Trump’s proposed U.S. fiscal 2018 budget issued today sharply cuts science spending while bolstering military spending as he promised during the campaign. Read more…

By John Russell

CPU-based Visualization Positions for Exascale Supercomputing

March 16, 2017

In this contributed perspective piece, Intel’s Jim Jeffers makes the case that CPU-based visualization is now widely adopted and as such is no longer a contrarian view, but is rather an exascale requirement. Read more…

By Jim Jeffers, Principal Engineer and Engineering Leader, Intel

US Supercomputing Leaders Tackle the China Question

March 15, 2017

Joint DOE-NSA report responds to the increased global pressures impacting the competitiveness of U.S. supercomputing. Read more…

By Tiffany Trader

New Japanese Supercomputing Project Targets Exascale

March 14, 2017

Another Japanese supercomputing project was revealed this week, this one from emerging supercomputer maker, ExaScaler Inc., and Keio University. The partners are working on an original supercomputer design with exascale aspirations. Read more…

By Tiffany Trader

Nvidia Debuts HGX-1 for Cloud; Announces Fujitsu AI Deal

March 9, 2017

On Monday Nvidia announced a major deal with Fujitsu to help build an AI supercomputer for RIKEN using 24 DGX-1 servers. Read more…

By John Russell

HPC4Mfg Advances State-of-the-Art for American Manufacturing

March 9, 2017

Last Friday (March 3, 2017), the High Performance Computing for Manufacturing (HPC4Mfg) program held an industry engagement day workshop in San Diego, bringing together members of the US manufacturing community, national laboratories and universities to discuss the role of high-performance computing as an innovation engine for American manufacturing. Read more…

By Tiffany Trader

For IBM/OpenPOWER: Success in 2017 = (Volume) Sales

January 11, 2017

To a large degree IBM and the OpenPOWER Foundation have done what they said they would – assembling a substantial and growing ecosystem and bringing Power-based products to market, all in about three years. Read more…

By John Russell

TSUBAME3.0 Points to Future HPE Pascal-NVLink-OPA Server

February 17, 2017

Since our initial coverage of the TSUBAME3.0 supercomputer yesterday, more details have come to light on this innovative project. Of particular interest is a new board design for NVLink-equipped Pascal P100 GPUs that will create another entrant to the space currently occupied by Nvidia's DGX-1 system, IBM's "Minsky" platform and the Supermicro SuperServer (1028GQ-TXR). Read more…

By Tiffany Trader

Tokyo Tech’s TSUBAME3.0 Will Be First HPE-SGI Super

February 16, 2017

In a press event Friday afternoon local time in Japan, Tokyo Institute of Technology (Tokyo Tech) announced its plans for the TSUBAME3.0 supercomputer, which will be Japan’s “fastest AI supercomputer,” Read more…

By Tiffany Trader

IBM Wants to be “Red Hat” of Deep Learning

January 26, 2017

IBM today announced the addition of TensorFlow and Chainer deep learning frameworks to its PowerAI suite of deep learning tools, which already includes popular offerings such as Caffe, Theano, and Torch. Read more…

By John Russell

Lighting up Aurora: Behind the Scenes at the Creation of the DOE’s Upcoming 200 Petaflops Supercomputer

December 1, 2016

In April 2015, U.S. Department of Energy Undersecretary Franklin Orr announced that Intel would be the prime contractor for Aurora: Read more…

By Jan Rowell

Is Liquid Cooling Ready to Go Mainstream?

February 13, 2017

Lost in the frenzy of SC16 was a substantial rise in the number of vendors showing server oriented liquid cooling technologies. Three decades ago liquid cooling was pretty much the exclusive realm of the Cray-2 and IBM mainframe class products. That’s changing. We are now seeing an emergence of x86 class server products with exotic plumbing technology ranging from Direct-to-Chip to servers and storage completely immersed in a dielectric fluid. Read more…

By Steve Campbell

Enlisting Deep Learning in the War on Cancer

December 7, 2016

Sometime in Q2 2017 the first ‘results’ of the Joint Design of Advanced Computing Solutions for Cancer (JDACS4C) will become publicly available according to Rick Stevens. He leads one of three JDACS4C pilot projects pressing deep learning (DL) into service in the War on Cancer. Read more…

By John Russell

BioTeam’s Berman Charts 2017 HPC Trends in Life Sciences

January 4, 2017

Twenty years ago high performance computing was nearly absent from life sciences. Today it’s used throughout life sciences and biomedical research. Genomics and the data deluge from modern lab instruments are the main drivers, but so is the longer-term desire to perform predictive simulation in support of Precision Medicine (PM). There’s even a specialized life sciences supercomputer, ‘Anton’ from D.E. Shaw Research, and the Pittsburgh Supercomputing Center is standing up its second Anton 2 and actively soliciting project proposals. There’s a lot going on. Read more…

By John Russell

Leading Solution Providers

HPC Startup Advances Auto-Parallelization’s Promise

January 23, 2017

The shift from single core to multicore hardware has made finding parallelism in codes more important than ever, but that hasn’t made the task of parallel programming any easier. Read more…

By Tiffany Trader

HPC Technique Propels Deep Learning at Scale

February 21, 2017

Researchers from Baidu’s Silicon Valley AI Lab (SVAIL) have adapted a well-known HPC communication technique to boost the speed and scale of their neural network training and now they are sharing their implementation with the larger deep learning community. Read more…

By Tiffany Trader

CPU Benchmarking: Haswell Versus POWER8

June 2, 2015

With OpenPOWER activity ramping up and IBM’s prominent role in the upcoming DOE machines Summit and Sierra, it’s a good time to look at how the IBM POWER CPU stacks up against the x86 Xeon Haswell CPU from Intel. Read more…

By Tiffany Trader

IDG to Be Bought by Chinese Investors; IDC to Spin Out HPC Group

January 19, 2017

US-based publishing and investment firm International Data Group, Inc. (IDG) will be acquired by a pair of Chinese investors, China Oceanwide Holdings Group Co., Ltd. Read more…

By Tiffany Trader

US Supercomputing Leaders Tackle the China Question

March 15, 2017

Joint DOE-NSA report responds to the increased global pressures impacting the competitiveness of U.S. supercomputing. Read more…

By Tiffany Trader

Trump Budget Targets NIH, DOE, and EPA; No Mention of NSF

March 16, 2017

President Trump’s proposed U.S. fiscal 2018 budget issued today sharply cuts science spending while bolstering military spending as he promised during the campaign. Read more…

By John Russell

Intel and Trump Announce $7B for Fab 42 Targeting 7nm

February 8, 2017

In what may be an attempt by President Trump to reset his turbulent relationship with the high tech industry, he and Intel CEO Brian Krzanich today announced plans to invest more than $7 billion to complete Fab 42. Read more…

By John Russell

Nvidia Sees Bright Future for AI Supercomputing

November 23, 2016

Graphics chipmaker Nvidia made a strong showing at SC16 in Salt Lake City last week. Read more…

By Tiffany Trader

  • arrow
  • Click Here for More Headlines
  • arrow
Share This