The problem is a well understood one: Microprocessor performance has outstripped data communication performance, which limits performance of data-intensive applications on standard cluster architectures. The temptation is to scale the cluster out even more, but this yields diminishing returns since the imbalance between the CPU and interconnects scales as well. It's like trying to make a car go faster by adding more valves to the engine.
Three OEM start-ups — Fabric7, PANTA System and Liquid Computing — are attacking the problem with scale-out commodity architectures and each has come up with a compelling design. In August, we focused on Fabric7's solution, and last week, PANTA Systems' new offering. In this week's issue, we spotlight Liquid Computing via an interview with the CEO and co-founder, Brian Hurley. Their new product is being announced for general availability next week.
Although the three companies have come up with rather different architectures, they are employing similar approaches. But you wouldn't guess that talking with them. In my conversations with the trio over the past few months, each tried to distance its solution from the other two. And while the three designs are very different, the basic technology is similar.
The common piece in the solution is to use HyperTransport (HT) technology to control allocation of hardware resources (CPUs, I/O, memory, and network communication) at the physical level. Each vendor provides a software interface that enables the user to dynamically create or dissolve HT communication links to various resources. This allows the user to more easily balance data bandwidth requirements with computing resources. With today's HT technology and AMD dual-core processors, an 8-way (core) SMP is possible. In 2007, the next generation of technology will allow for a 32-way SMP configuration, and a year after that, 128-way systems.
The other common architectural element involves just adding more data pipes in the machine, which helps to address the traditional imbalance in computation versus communication.
The capability to create designer SMP nodes from a common pool of highly connected hardware seems pretty novel. But virtualization via hardware is an established concept. Mainframes have been doing hard partitioning for years. But users pay a lot for this flexibility. With the advent of standard HyperTransport technology, this capability is now available to commodity AMD processor-based systems. Offering resource virtualization — and by extension, reliability — with industry standard parts challenges the big UNIX and Linux machines used for data-intensive enterprise computing. At the same time, it provides a more flexible design to fixed-architecture clusters and offers an interesting alternative for high performance technical computing users.
While virtualization is already well-established in the enterprise, its adoption into HPC will require some re-education. The problem here is that the term has become stigmatized to suggest that it comes with a performance penalty — a big no-no in the HPC culture. This is because conventional virtualization solutions in the enterprise involve a software layer that consumes CPU cycles. The HyperTransport-based solution avoids this particular drawback by establishing hardware resources at the physical layer.
Using virtualization and faster interconnects to make a more flexible commodity-based computing system has a lot of appeal. According to Liquid Computing, IDC believes that about half of the potential market for HPC clusters are held back because of some of the issues that an interconnect-centric architecture addresses. Being able to improve manageability by moving away from the departmentalization of clusters across a company towards a more consolidated infrastructure is something many large enterprise HPC users could benefit from. For that half of the cluster market, the classic enterprise RAS (Reliability, Availability and Serviceability) features are highly valued. And the consolidation of resources has the added benefit of reducing energy, cooling and space requirements.
Because of all the advantages of this type of scalable architecture, the market opportunities span technical computing, high performance enterprise computing, IT outsourcing/ASP, and telecom OEMs. The three vendors are feeling their way into these markets. Currently, Fabric7 is concentrating its efforts on the enterprise market, but is keeping an eye on HPC. PANTA Systems seems to be going after both the enterprise and HPC markets from the get-go. Liquid Computing, while initially targeting HPC, appears to want to use that sector as a springboard to a broader IT market.
With the merging of HPC with enterprise computing, it's a confusing time for both vendors and users. Andy Church, VP of Marketing at Liquid Computing, reported that in conversations they've had with IDC's Earl Joseph, the analyst confirmed the notion that there is a gray area between traditional high performance technical computing and enterprise IT outsourcing. This is reflected by the range of users interested in Liquid Computing's offering. The company's early adopters include customers in the enterprise technical computing, ASP, IT outsourcing and telecommunications OEM markets. For vendors like these, it's becoming more difficult to talk about enterprise computing and HPC as separate markets. “Our perspective is that those worlds are merging,” said Church.
AMD + ATI = Fusion
It's AMD's fault. I vowed to stop writing about GPUs for at least a few issues. But with this week's announcement by AMD to build integrated CPU-GPU processors based on x86 cores and ATI GPU technology, I'm forced to add a few more thoughts on the topic.
The news of this hybrid processor initiative came on the same day that the merger of the AMD and ATI was finalized. To me, this is like announcing plans for your first baby during your honeymoon, which suggests that the two companies were devising this idea during their early courtship. By the way, AMD gets to be the groom in this metaphor since it will keep its name. ATI gets subsumed into AMD, website and all.
Without going into much detail in the announcement, AMD declared its plans to create a new class of x86 processor that integrates CPUs and GPUs at the silicon level with a design initiative called “Fusion.” The new processors will target all computing platforms currently supported by AMD, including laptops, desktops, workstations and servers, as well as consumer electronics. According to the company, the first Fusion processors will come to market in late 2008 or early 2009. In that time frame, the use of 45nm process technology will allow enough room on the die for large GPUs and CPUs to co-mingle and do so within a reasonable thermal envelope.
Compared to separate CPU and GPU device configurations, integrating the two types of computing engines into one chip should yield much better performance and performance-per-watt for applications using 3D graphics, digital media processing and high performance computing. Application-wise, that's a pretty big tent. But it gives you a good sense of where AMD thinks IT growth is going to occur.
This presents an interesting challenge for rival Intel. Basically its choices are:
- Buy NVIDIA for their GPU technology. An increasingly unlikely event, given that neither of the two companies seems interested in such an arrangement.
Morph its own graphics division to produce higher-end devices. An expensive proposition, but cheaper than buying NVIDIA.
Beef up the native x86 Streaming SIMD Extensions (SSE) capability to compete with GPU capability. Maybe a more likely scenario, but a less flexible approach overall.
Ignore the trend and hope GPUs aren't the “next big thing” in general-purpose processing. The riskiest choice of all.
In attempting to side-step Intel, AMD is betting its future on this new vision of CPU-GPU computing. AMD's track record for redefining processor architectures is pretty impressive. When the company took the x86 into the 64-bit space in 2003, Intel was forced to follow. AMD's development and use of the HyperTransport technology and the on-chip memory controller provided a sound basis for multi-core scalabilty, and is expected to be duplicated by Intel with their CSI bus and their processor-based memory controller. Will history repeat itself once again?
As always, comments about HPCwire are welcomed and encouraged. Write to me, Michael Feldman, at [email protected].