The 22nd meeting of the IDC HPC User Forum, held in Manchester, UK, last week, brought together more than 80 UK, European and U.S. participants to discuss leading-edge research, market dynamics and vendor strategies. The local host for the meeting was the University of Manchester. Vendor sponsors included Cray, HP, IBM, INTEL, Panasas and Sun Microsystems. HPC User Forum meetings are co-sponsored by HPCwire.
Attendees were welcomed by IDC's Earl Joseph, executive director of the HPC User Forum; Steering Committee Chairman Paul Muzio, who is VP-Government Programs for Network Computing Services, Inc. and Support Infrastructure Director of the Army High Performance Computing Research Center (AHPCRC); and Terry Hewitt, Head of Supercomputing, Visualization and e-Science (SVE) and Director of the International AVS Centre at Manchester Computing. Other participating HPC User Forum Steering Committee members were Paul Buerger, OSC; Steve Finn, BAE Systems; Sharan Kalwani, General Motors; and Jim Kasdorf, PSC.
The two-day meeting began with an optional tour of the University of Manchester, showcasing Manchester's pioneering role in building the first computers.
Addison Snell presented IDC's HPC technical server market update, noting that the market has had aggregate revenue growth of 94 percent since 2002 and grew 24 percent in 2005 alone. Clusters represented close to half the overall $9.2 billion market revenue for 2005. The capability market has declined 13 percent since 2002, while strong growth at the lower end of the market has boosted revenue in the workgroup segment 200 percent, in the departmental segment 155 percent, and in the divisional segment 84 percent since 2002. The overall leaders by revenue share in 2005 were HP and IBM, with Dell third. The largest application/industry segments by revenue in 2005 were university/academic research, followed by bio-sciences. DCC (digital content and distribution) has been growing rapidly, mainly because of the rise of virtual movies and online gaming. This segment now totals nearly half a billion dollars. The economics/financial segment has been around a long time and, at less than 5 percent of the HPC market, is not as large as some HPC vendors imply. About one-third of all HPC users are already looking at accelerator processors, predominantly FPGAs.
Paul Muzio, AHPCRC/NCSI, reviewed the HPC User Forum's role in identifying and helping to address issues of concern to the user community. The User Forum formulates a technical agenda around these concerns, brings in noted speakers, involves vendors, and encourages government agencies and others to pursue the issues. The User Forum has made important contributions regarding issues in benchmarking, ISV software and other areas. The organization's Steering Committee in recent meetings encouraged members to participate directly in standards committees important for the HPC industry.
Terry Hewitt said Manchester, founded in 1851, is the largest civic university in the UK. Among Manchester's contributions to computing are the first stored computer program and the first memory, based on cathode ray tube technology. Manchester also has a strong history in applications, such as medicine and anthropology, and in computing services within and beyond the university, including the UK's national data service and access grid support center. Manchester operates a Cray T3E, SGI Altix and a 2000-processor Dell for particle physics.
Martyn Guest of CCLRC Daresbury Laboratory discussed the UK's £38 million, three-phase (2006-2008), coordinated procurement of a variety of HPC systems to support 20 universities. Funds for the HPC procurement, part of the £900 million SRIF3 (Science Research Investment Fund) budget for “research capital,” are entirely for equipment and infrastructure, with no funding for staff. Funds will be awarded to universities, which can then decide how much to spend on what (e.g., computers, networking, facilities). Daresbury got involved because the universities have limited expertise in procuring large HPC machines. Daresbury recommended, and helped assemble, a core set of benchmarks that combine synthetics and real applications.
Ben Ralston talked about the Atomic Weapons Establishment's (AWE) recent procurement that resulted in a win for a 40-teraflop Cray XT3 system. AWE's very demanding application helps maintain the UK's deterrent. The new system boosts sustained performance 25x, even though peak performance rose only 14x. The system will have 3,944 nodes of dual-core Opterons at 2.6 GHz. AWE expects to fully commission the system over the next few weeks. The benchmarks represented AWE users' codes (physics, engineering, material science) and results were weighted according to how heavily each codes is used at AWE. The tests were run on up to 4,096 processing elements.
Sharan Kalwani of General Motors, said he's looking at getting a 40-teraflop system soon. GM owns many other firms and needs to act in a global way, not as a collection of “islands.” HPC plays a key role in quality and touches many aspects of GM's business: customer satisfaction, crash safety, NVH and more. Using HPC, GM has reduced its Vehicle Development Process from 80 months in the early 1990s to under 18 months in 2004, with further reductions planned. He estimates HPC has saved GM $1 billion. The company plans to grow to 60 teraflops of capacity plus capability within two years.
According to Martin Walker at Hewlett Packard, processor manufacturers are responding to requirements for more performance, and devices such as Intel's teraflop processor will be very interesting for petascale computing. We have ten years to construct the petaflop ecosystem. Which applications will need this? One potential area is biomedical research. It would take a petaflop system three years to simulate the folding process of a single protein. Using an HP system, EPFL and several Swiss universities are working to develop a vaccine to stimulate the immune system to kill cancer cells, with promising results in human trials.
Intel's Stephen Wheat said hyper-threading will return, but many-core will progress rapidly. Intel has fabricated and tested 80-core already. The key to all this is what's happening with the thermals. Energy-per-instruction has increased. In 2006, the company will have a teraflop on a test chip (80 TF/square foot). Reaching petaflop application performance with 100,000 processors in 2010 is reasonable. Deploying multithreaded cores in Intel's quad cores could accelerate this. Intel is looking at bringing silicon photonics onto the silicon itself. In the power domain, Intel is looking at achieving 25-30 kilowatts per rack.
Jean-Francois Lavignon noted that although Bull is a newcomer in HPC (2001), the company has complex IT infrastructure experience, NovaScale servers, and OS competence with GDOS, AIX and Linux. The Bull system at CAE is Europe's largest and number five in the world, according to the Top500. Bull also provides smaller HPC systems and installed one this summer in Manchester. Academic and industrial customers include Dassault Aviation and multiple automotive firms.
Paul Muzio gave his colleague Andrew Johnson's presentation on dynamic mesh generation for fluid structure interaction applications. Problem statement: Can you design a very small UAV [Unmanned Aerial Vehicle] with flapping wings? AHPCRC developed new methodologies using partitioned global address space models. Muzio showed a video of a hummingbird in a wind tunnel, and a closely correlated 3D simulation of the hummingbird's wing motion using an unstructured tetrahedral mesh. He showed a simulation of a parachute opening, based on the same method. The method needs each processor to be able to reference any arbitrary element. MPI is not a good fit for this method, which requires very low latency. MPI is good for transferring large messages, not many small ones. Muzio reviewed the advantages of PGAS programming models such as CAF and UPC, along with the current issues (not available on many systems).
Sun's Michael Schulman updated the audience on Sun's recent win at TACC for a 400-teraflop Opteron-based system that will become part of the Teragrid, along with wins at TIGR and Paramount Pictures. Sun has expanded its Opteron line with lower entry pricing and remains a finalist for Phase 3 of the DARPA HPCS program.
Steve Finn, BAE Systems and DoD HPCMP User Advocacy Group member, is also on the HPC User Forum Steering Committee. Finn summarized the panel session on processor options from the September HPC User Forum meeting in Denver, starting with Richard Walsh's (AHPCRC/NCSI) canonical program for evaluating the attributes of processor types and instruction sets in relation to application requirements. Using Kiviat charts and these attributes, you can get a signature for each processor type and compare it with the “typical” Top500 list processor. Finn summarized the pluses and minuses of each type of processor offered by HPC vendors and also summarized the Denver talks by NCI's Jack Collins, Utah State University's Thomas Hauser, and NASA Langley's Robert Singleterry.
Terry Hewitt reviewed the latest developments at the University of Manchester, including write-only memory boards being developed through a strategic alliance with multiple vendors. According to Hewitt, these boards “will support every type of memory known to man, with a new transport interface to calm you down.”
Paul Buerger, Ohio Supercomputer Center and an HPC User Forum Steering Committee member, reviewed the Denver session on petascale initiatives:
- Paul Muzio stressed the need for balanced systems, global addressing and ease-of-programming.
- David Probst, Concordia University/Montreal, said our programming models are homogeneous but our computer systems are heterogeneous, so we need heavyweight threads and lightweight threads.
- Doug Kothe said ORNL has identified a long list of science applications that would benefit from petascale performance.
- Makoto Taiji, RIKEN, discussed the current MDGrape3 system, the 2008 GRAPE-DR project (2 PF), and the 2012 NexGen project (10 PF).
- Zeng Yu said the current Dawning 5000A system scales to 100 TF peak performance and Dawning plans a petascale computer.
- John Morrison reviewed LANL's plans to scale the IBM “Roadrunner” to petascale Linpack performance in “a couple of years.”
- Dolores Shaffer reviewed the DARPA HPCS program.
- Horst Simon discussed challenges in moving toward the petascale era and NERSC's purchase of a 100-teraflop Cray “Hood” system, with optional upgrades to the petaflop level.
- Argonne National Laboratory has a 100-teraflop Blue Gene/L and intends to advance to a peak petaflop in a few years.
According to Christine Kitchen, Daresbury's Distributed Computing Group assists the UK's academic community with cluster procurements, providing advice and courses that include assessments of the capabilities of integrators. Integrators play a major role in cluster purchasing within the UK. The role of Tier 1 vendors versus integrators is ambiguous. Daresbury's 17th Machine Evaluation Workshop will be offered December 5-6, 2006.
Cray's Andy Mason said AWE is going through acceptance testing for its Cray XT3 system. CSC Finland recently ordered a next-generation XT3 that will have more than 70 TF peak performance by 2008. NERSC's 102 “Hood” cabinets will finish delivery in first-quarter 2007.
Chris Wheaton described Panasas as the leader in object storage for scalable Linux clusters. The storage market hasn't moved at the same pace as other cluster technologies. Panasas Storage Cluster allows you to treat metadata separately from the data. DOE has a 5-year, $11 million petascale project to find new ways to manage mountains of data coming from future-generation supercomputers.
Steve Noyes explained how the UK Met Office creates a forecast. UK Met spends £40 million every five years for new HPC systems, with the next operational system procurement due in 2009. Noyes discussed findings and expectations for climate change. Climate models have become more complex since the 1970s, with many more dimensions. Carbon, hydrogen and nitrogen cycles are things people are beginning to add in. The resolution of the models is also increasing.
Jim Kasdorf gave an update on the Pittsburgh Supercomputing Center. The PSC Biomedical Initiative, funded by NIH since 1987, is now called the National Resource for Biomedical Supercomputing. Its mission remains biomedical research and outreach to the national biomedical community. The FY07 budget request for the NSF Office of Cyberinfrastructure is almost $600 million. NSF plans a petascale computer in 2010. There will be four chunks of $50 million each in funding for this.
Andy Grant said IBM is starting to see accelerators in procurements. IBM is installing a large Opteron cluster with ClearSpeed boards at the University of Bristol. Sites are also showing interest in Microsoft-based clusters. The Blue Gene/L successor will be Blue Gene/P (for petaflop), followed by Blue Gene/Q (10 petaflops). Power6 is due out in about one year.
John Gurd, Manchester, said the number of processors required (generally agreed to exceed 100,000) for petascale computing may require a change in software architecture. Explicit programming has to go at some point. We need to abstract the programs away from the hardware. This means creating languages and tools together. Auto-parallelizers working dynamically could help. Rule-of-thumb: a problem needs at least one order of magnitude more parallel tasks than the number of processors. For example, you need 1 million tasks available to keep 100,000 processors busy.
Manchester's Andrew Jones chaired a panel on whether programming model changes are needed for petaflops computing. Jones noted that scaling to 1,000 processors on homogeneous architectures is difficult today. Petascale and exascale computing will involve many more threads than today, and possibly heterogeneous architectures. We may need a new programming paradigm.
Ben Ralston, AWE, said HPC has to find emerging technologies, such as the lightweight kernel on the XT3, that allow scaling but are not disruptive and don't change the programming paradigm. Reprogramming software typically takes many person-years. Users won't undergo this unless they're certain of the new direction. “I don't think we're ready for a new software paradigm because don't know where the hardware is going yet.”
Paul Muzio, AHPCRC/NCSI, stressed that GM, Dassault and many other major companies are using Fortran. People won't throw out these huge investments. The applications proposed for petascale computing are not the ones companies or the defense establishment will invest in. There are opportunities for languages like Fortran to evolve, such as Co-Array Fortran. Muzio emphasized we have to get back to the scientific/engineering results, not how many petaflops can be bought. The human cost in developing the apps is far greater than the cost of the hardware.
Ian Reid said Fortran is still NAG's core technology. The days of the single-core treadmill are over, and multi-core is here to stay. This creates major software issues that will force us at least to hybrid hardware architectures. We also need to enhance the software stacks, but in a way that excites the HPC community. There must be portability. There is considerable concern about whether the HPCS languages will deliver on their promises.
Stephen Wheat, Intel, stated that it is clearly too late for programming model shifts before petaflop computing comes, because petaflop computing is coming in the next year or so. There may be enough time before volume petaflop systems arrive in 4-5 years. Even so, how do we get this new thinking done in a decade? We must conceive parallelism before we can represent it. We need to rationalize the problem first. To make this easier, we need architectural stability. “I don't think globally addressable memory will take hold in the volume space, although we may do this at the smaller SMP scale.”
Earl Joseph invited the HPC community to attend IDC's annual “Breakfast at Supercomputing” industry update on Wednesday, Nov. 15, during the SC06 conference in Tampa, Florida. For more information and to register, go to http://www.idc.com/getdoc.jsp?containerId=IDC_P14208.
Joseph also invited the HPC community to participate in IDC's upcoming HPC User Forum meetings in India (New Delhi and Bangalore, February 28-March 2, 2007) and Coeur d'Alene, Idaho (April 9-11, 2007).
The HPC User Forum (www.hpcuserforum.com) is directed by a steering committee consisting of users/buyers from government, industry and academia, and is operated for the users by market analyst firm IDC. Paul Muzio, Vice President-Government Programs for Network Computing Services, Inc. and Support Infrastructure Director of the Army High Performance Computing Research Center, is the current chairman of the steering committee.
The HPC User Forum was founded in 1999 to advance the state of high-performance computing through open discussions, information sharing and initiatives involving HPC users in industry, government and academia, along with HPC vendors and other interested parties. The organization has grown to more than 150 members.