The Software Challenges of Petascale Computing

By Nicole Hemsoth

November 10, 2006

In this HPCwire interview, Kathy Yelick, one of the world's leading performance evaluation experts, discusses software challenges related to petascale and other large-scale computing systems. Yelick is a professor of computer science at UC Berkeley, with a joint appointment in Lawrence Berkeley Lab's Computational Research Division, where she leads the Future Technologies Group and the Berkeley Institute for Performance Studies.

HPCwire: Are petascale initiatives putting enough emphasis on software?

Yelick: No. Unfortunately, the race for each major performance milestone, in this case petascale, has resulted in a de-emphasis on software. Procurement teams and system developers vying for the first petascale platform need to put as much money as possible into hardware in order to be first. This leaves less funding for software. The situation has gotten worse over the past decade, when multiple agencies were supporting HPC software development.

HPCwire: Assuming the important goal isn't peak or Linpack petaflops performance, but sustained petaflops performance across a spectrum of applications, what software challenges need to be addressed?

Yelick: The major software challenge facing the petascale efforts is the explosion in hardware parallelism, which will require a complete redesign of applications, libraries, and algorithms to reach the level of parallelism needed to fully utilize a petascale machine. This parallelism increase is coming from the introduction of multi-core processors within the compute nodes and the trend towards building machines out of a larger number of smaller compute nodes. Other challenges include the hierarchical nature of these machines, the use of hardware accelerators such as SIMD units within compute nodes, and the trend toward lower degree networks. Full crossbars for petascale machines are unaffordable. Software needs to adapt to these features, and I believe it will. The question is how general the solutions will be and therefore how large the set of petascale applications will be. The reliability of these systems is also a major concern, and one that I think represents the largest risk for specific machines. We need to have better methods for handling hardware and software failures throughout the software stack.

HPCwire: Which of these software challenges are hardest? How much can be accomplished by the 2010 timeframe?

Yelick: Reliability is probably the hardest, because so far we have written user-level software assuming that the lower level system is mostly reliable. Checkpointing is the only commonly used technique, and the Berkeley Lab Checkpoint/Restart project is developing software for petascale systems; but this model is useful only as long as failures are not too frequent. There are research efforts to develop new ways of writing fault-tolerant software, but the solution is not yet clear. In the meantime, we need to do a very good job of testing systems software, in particular operating systems, to reduce the frequency of failures.

HPCwire: With compilers, there is the challenge of scaling to petaflop architectures and also the challenge of handling heterogeneous architectures with multiple processor types that a number of vendors are talking about. Can you comment on these challenges?

Yelick: Heterogeneous processors represent a new compiler challenge, because, at the very least, they increase the optimization space for code generation, which is already very difficult to navigate. Automatically tuned libraries like Atlas, FFTW and our Berkeley OSKI library represent an approach for getting high quality code generated for specific numerical kernels. Heterogeneous processors can fit into this model, as small code snippets written in assembly language can be incorporated into the search space. And at least two of the SciDAC efforts, PERI and CScADS, are working on generalizing these ideas to a new type of compiler which uses search during code generation. To me, the challenge represented by these processors is not the heterogeneity per se, but the difficulty of explicitly managing the memory systems, which may have separate memory spaces or alignment rules for some of the processors. The Cell processor and BG/L double hummer are good examples. If moving data within the heterogeneous processor is too expensive, these systems may not be effective. If they are fast but hard to use, the problem will be putting sufficient resources into the development of compilers, libraries, and applications software to take advantage of them.

HPCwire: The DARPA HPCS program heavily stresses productivity, along with performance. How can programming languages help productivity?

Yelick: The commercial world has experienced tremendous increases in productivity from language features such as strong typing, which catches errors early, garbage collection and the heavy use of libraries or components, which are made easier through simple interfaces that come from good language support. For example, if a user is managing memory allocation and deallocation, and keeping track of complex data types manually by passing type flags in the code, this significantly complicates the application code, but also make it more difficult to package components with clean interfaces that others are likely to understand easily and use.

HPCwire: Can good programming languages and other software get around bad machines?

Yelick: No. There is nothing software can do to get around bad machine design. Global address space languages like UPC, CAF, and Titanium are in some sense giving good hardware an advantage over bad by trying to expose features such as low overhead communication or global address space support. That said, one of the goals of the Berkeley UPC compiler is to make UPC an effective language for a larger class of machines and for less sophisticated programmers. We have advocated language extensions such as non-blocking bulk data reads and writes to allow programmers to obtain the best possible performance on clusters, and are also working on compiler technology to automatically optimize programs written in a fine-grained style. This could make programs written for a global address space machine like the Cray X1E run reasonably well on generic clusters–not as well as on the X1E, but reasonably well.

HPCwire: What are the limits of MPI's usefulness? What would it be like relying on MPI for petascale computing?

Yelick: MPI is likely to be a very popular and effective programming model on petascale machines. There are two issues, one related to performance and the other to ease of use. For performance, the problem is that the two-sided protocol in MPI, which involves message matching, and the requirement of message ordering all slow down data transfer. The fastest mechanism on a machine with minimal RDMA support is to write data directly from one processor into another processor's memory. Fast implementations of MPI do use this mechanism, but it requires some protocol overhead, since the remote address is not known to the sending processor. As we've shown in our UPC work, one-sided communication can be used in bisection-limited problems, like global FFTs, to improve communication overlap and reduce running time. At a petascale, bisection bandwidth is going to be expensive, and MPI may not give the best utilization of the network or the best management of memory due to the need for buffering. From an ease-of-use standpoint, I think the issue with MPI is that the community of petascale programmers, like terascale programmers today, will be small, because the barrier to entry for an application code is high. There are many computational scientists today who are not using parallel machines at all. This will have to change with the shift towards multi-core, but the question is whether they will adopt a scalable programming model.

HPCwire: Talk about the importance of partitioned global address space, or PGAS, programming languages.

Yelick: Aside from my answers to the previous question, PGAS languages offer a real advantage over OpenMP for shared memory platforms, because they give programmers the opportunity to express locality properties of the data structures. This makes the PGAS models an alternative to the hybrid MPI/OpenMP model for hierarchical machines, which has proven difficult to use.

But aside from the specifics on PGAS languages, I think they represent an important step in HPC programming models, because they've demonstrated that new languages are still a viable option, in spite of the backlash that occurred when HPF failed to take hold. The PGAS languages are popular within some government agencies and labs, including the work at AHPCRC on CFD codes in UPC. We have also learned some important lessons in the UPC process: interoperability with other programming models (in particular MPI) and ubiquity across platforms are essential to success. We have new methods for analyzing and quantifying productivity; and found that performance is still critical to swaying the most elite of HPC programmers.

HPCwire: What's the status of these languages today, including Berkeley UPC?

Yelick: UPC has an active community consortium that meets regularly to work on language design issues, maintain the language spec, and exchange implementation and application experience. There is a UPC compiler of some form for nearly every serial and parallel platform, including vendor compilers from Cray, HP, and IBM, and open source compilers from Intrepid, Inc., Michigan Tech and Berkeley Lab. The Berkeley compiler has optimized implementations using native communication layers for the Cray XT3, Quadrics, Myrinet, Altix, and the IBM SP platforms. Co-Array Fortran is being adopted into the Fortran spec, and in addition to the Cray CAF compiler, there is an open source effort led by John Mellor-Crummey at Rice. That compiler is designed for portability; it uses a source-to-source translation model like Berkeley UPC, and there are plans to do work on porting and releases in the near future. Titanium is still primarily a Berkeley effort, but it is used outside Berkeley and the compiler runs on many parallel and serial platforms. Berkeley UPC, Intrepid's gcc-upc, Titanium, and at least one instance of the Rice CAF compiler all use our open source communication layer called GASNet, which helps leverage the porting effort. These three PGAS languages will all be represented at the UPC booth (#342) at SC06. We will have compilers to install on your laptops, as well as posters and papers showing application experience and benchmark results.

HPCwire: Some people say that if there's a lot of pain involved, they won't switch to a new programming language. How can you motivate people to migrate to a more efficient new language?

Yelick: The key is that, because of interoperability, full applications do not need to be rewritten. Instead, individual components can be written in these languages as new algorithms are developed for the increasing machine scale. I am working with Parry Husbands and Esmond Ng, for example, on a fast sparse direct linear solver written in UPC. This may end up in an application without rewriting the rest of the code. And if the performance gains of new languages are significant, some people who care deeply about performance will switch. The harder argument is productivity, because while the community as a whole might save significant amounts of time and money in the long run by rewriting some code in new languages, this is difficult to quantify up front; and from the short term perspective of a 3-year or 5-year project, it is difficult to justify.

HPCwire: Where do you see MATLAB fitting into HPC, versus languages like UPC and CAF?

Yelick: MATLAB is very important, because the computational science and engineering communities in general (outside of HPC) are sold on the productivity advantage of MATLAB. They have voted with their feet by using MATLAB instead of languages like Fortran, C, C++ and Java. The problem is moving MATLAB into the large scale, both machine scale and software scale. The array statements in MATLAB make it a natural data parallel language, but more general forms of parallelism will be needed for large machines and irregular applications. There are several efforts to include parallelism in MATLAB by calling parallel libraries, extending the language, or performing compiler analysis on the code, and I think these will help to make parallel machines more accessible. On the other hand, I'm afraid that the difference between programming-in-the-small and programming-in-the-large (with separate modules, large application teams, complicated data structures and interfaces) are sometimes overlooked–languages that are very good at small programming tasks are not the best for large ones.

HPCwire: Will Fortran continue to be the fastest language? What about C and Java?

Yelick: This is an interesting question. Most vendor-supplied Fortran compilers share the backend, including optimization and code generation, with the C/C++ compilers. So in principle, the performance for the same program should be identical. There are still semantic differences between the languages, which will require the use of features like “restrict” in C/C++ to get the equivalent programs, and more of these may be needed in the C spec when it comes to multidimensional arrays. And programs that use all of the features of object-orientation and pointer-based data structures are unlikely to be as fast as their stripped-down counterparts. But the investment in Fortran compilers is not likely to be as high as in C/C++. Java is a different point on the spectrum: on the one hand the higher level of abstraction and need for automatic memory management add overhead, but the use of just-in-time compiler technology opens the door to optimizations that are not possible in a statically compiled environment.

HPCwire: Do you want to say anything about scaling algorithms for petascale computing?

Yelick: I think we need to rethink our algorithms to look for all possible sources of parallelism, rather than the single-level view that we have used recently. An upcoming SC06 paper with Shan, Strohmaier, Qiang, and Bailey is a case study in scaling and performance modeling, which reflects our ability to understand application performance on large machines. We look at a beam interaction application from accelerator modeling and develop a series of performance models to predict performance of this application code. Performance modeling, and therefore a simple understanding of performance, becomes increasingly difficult as the machines scale, as they become more hierarchical, and as network contention increases. All of these will be serious issues on petascale machines. The SC06 paper will be presented by Erich Strohmaier on Tuesday, Nov. 14, 4:30-5:00 in 22-23. We will also have copies of the paper and some of the authors will be around for questions at the LBNL booth (#1812) on the exhibit floor.

HPCwire: Is there anything important that we missed talking about?

Yelick: I think the introduction of parallelism into mainstream computing is both a challenge and opportunity for the HPC community. We must be able to handle the increase in parallelism along with everyone else, but if ever there was a time to innovate in parallel hardware, languages, and software, this is it. There are very likely to be new languages and programming models for multi-core programming, and the HPC community has the chance to take advantage of that software revolution by both influencing and using these innovations.

—–

Kathy Yelick is a professor of computer science at UC Berkeley. She has a joint appointment in Berkeley Lab's Computational Research Division, where she is the lead for the Division's Future Technologies Group and the Berkeley Institute for Performance Studies. Kathy received her Bachelors, Masters, and PhD degrees in Electrical Engineering and Computer Science from the Massachusetts Institute of Technology. Her research interests include parallel computing, memory hierarchy optimizations, programming languages and compilers.

Subscribe to HPCwire's Weekly Update!

Be the most informed person in the room! Stay ahead of the tech trends with industy updates delivered to you every week!

Supercomputer Modeling Shows How COVID-19 Spreads Through Populations

May 30, 2020

As many states begin to loosen the lockdowns and stay-at-home orders that have forced most Americans inside for the past two months, researchers are poring over the data, looking for signs of the dreaded second peak of t Read more…

By Oliver Peckham

SODALITE: Towards Automated Optimization of HPC Application Deployment

May 29, 2020

Developing and deploying applications across heterogeneous infrastructures like HPC or Cloud with diverse hardware is a complex problem. Enabling developers to describe the application deployment and optimising runtime p Read more…

By the SODALITE Team

What’s New in HPC Research: Astronomy, Weather, Security & More

May 29, 2020

In this bimonthly feature, HPCwire highlights newly published research in the high-performance computing community and related domains. From parallel programming to exascale to quantum computing, the details are here. Read more…

By Oliver Peckham

DARPA Looks to Automate Secure Silicon Designs

May 28, 2020

The U.S. military is ramping up efforts to secure semiconductors and its electronics supply chain by embedding defenses during the chip design phase. The automation effort also addresses the high cost and complexity of s Read more…

By George Leopold

COVID-19 HPC Consortium Expands to Europe, Reports on Research Projects

May 28, 2020

The COVID-19 HPC Consortium, a public-private effort delivering free access to HPC processing for scientists pursuing coronavirus research – some utilizing AI-based techniques – has expanded to more than 56 research Read more…

By Doug Black

AWS Solution Channel

Computational Fluid Dynamics on AWS

Over the past 30 years Computational Fluid Dynamics (CFD) has grown to become a key part of many engineering design processes. From aircraft design to modelling the blood flow in our bodies, the ability to understand the behaviour of fluids has enabled countless innovations and improved the time to market for many products. Read more…

What’s New in Computing vs. COVID-19: IceCube, TACC, Watson & More

May 28, 2020

Supercomputing, big data and artificial intelligence are crucial tools in the fight against the coronavirus pandemic. Around the world, researchers, corporations and governments are urgently devoting their computing reso Read more…

By Oliver Peckham

COVID-19 HPC Consortium Expands to Europe, Reports on Research Projects

May 28, 2020

The COVID-19 HPC Consortium, a public-private effort delivering free access to HPC processing for scientists pursuing coronavirus research – some utilizing AI Read more…

By Doug Black

$100B Plan Submitted for Massive Remake and Expansion of NSF

May 27, 2020

Legislation to reshape, expand - and rename - the National Science Foundation has been submitted in both the U.S. House and Senate. The proposal, which seems to Read more…

By John Russell

IBM Boosts Deep Learning Accuracy on Memristive Chips

May 27, 2020

IBM researchers have taken another step towards making in-memory computing based on phase change (PCM) memory devices a reality. Papers in Nature and Frontiers Read more…

By John Russell

Hats Over Hearts: Remembering Rich Brueckner

May 26, 2020

HPCwire and all of the Tabor Communications family are saddened by last week’s passing of Rich Brueckner. He was the ever-optimistic man in the Red Hat presiding over the InsideHPC media portfolio for the past decade and a constant presence at HPC’s most important events. Read more…

Nvidia Q1 Earnings Top Expectations, Datacenter Revenue Breaks $1B

May 22, 2020

Nvidia’s seemingly endless roll continued in the first quarter with the company announcing blockbuster earnings that exceeded Wall Street expectations. Nvidia Read more…

By Doug Black

Microsoft’s Massive AI Supercomputer on Azure: 285k CPU Cores, 10k GPUs

May 20, 2020

Microsoft has unveiled a supercomputing monster – among the world’s five most powerful, according to the company – aimed at what is known in scientific an Read more…

By Doug Black

HPC in Life Sciences 2020 Part 1: Rise of AMD, Data Management’s Wild West, More 

May 20, 2020

Given the disruption caused by the COVID-19 pandemic and the massive enlistment of major HPC resources to fight the pandemic, it is especially appropriate to re Read more…

By John Russell

AMD Epyc Rome Picked for New Nvidia DGX, but HGX Preserves Intel Option

May 19, 2020

AMD continues to make inroads into the datacenter with its second-generation Epyc "Rome" processor, which last week scored a win with Nvidia's announcement that Read more…

By Tiffany Trader

Supercomputer Modeling Tests How COVID-19 Spreads in Grocery Stores

April 8, 2020

In the COVID-19 era, many people are treating simple activities like getting gas or groceries with caution as they try to heed social distancing mandates and protect their own health. Still, significant uncertainty surrounds the relative risk of different activities, and conflicting information is prevalent. A team of Finnish researchers set out to address some of these uncertainties by... Read more…

By Oliver Peckham

[email protected] Turns Its Massive Crowdsourced Computer Network Against COVID-19

March 16, 2020

For gamers, fighting against a global crisis is usually pure fantasy – but now, it’s looking more like a reality. As supercomputers around the world spin up Read more…

By Oliver Peckham

[email protected] Rallies a Legion of Computers Against the Coronavirus

March 24, 2020

Last week, we highlighted [email protected], a massive, crowdsourced computer network that has turned its resources against the coronavirus pandemic sweeping the globe – but [email protected] isn’t the only game in town. The internet is buzzing with crowdsourced computing... Read more…

By Oliver Peckham

Global Supercomputing Is Mobilizing Against COVID-19

March 12, 2020

Tech has been taking some heavy losses from the coronavirus pandemic. Global supply chains have been disrupted, virtually every major tech conference taking place over the next few months has been canceled... Read more…

By Oliver Peckham

Supercomputer Simulations Reveal the Fate of the Neanderthals

May 25, 2020

For hundreds of thousands of years, neanderthals roamed the planet, eventually (almost 50,000 years ago) giving way to homo sapiens, which quickly became the do Read more…

By Oliver Peckham

DoE Expands on Role of COVID-19 Supercomputing Consortium

March 25, 2020

After announcing the launch of the COVID-19 High Performance Computing Consortium on Sunday, the Department of Energy yesterday provided more details on its sco Read more…

By John Russell

Steve Scott Lays Out HPE-Cray Blended Product Roadmap

March 11, 2020

Last week, the day before the El Capitan processor disclosures were made at HPE's new headquarters in San Jose, Steve Scott (CTO for HPC & AI at HPE, and former Cray CTO) was on-hand at the Rice Oil & Gas HPC conference in Houston. He was there to discuss the HPE-Cray transition and blended roadmap, as well as his favorite topic, Cray's eighth-gen networking technology, Slingshot. Read more…

By Tiffany Trader

Honeywell’s Big Bet on Trapped Ion Quantum Computing

April 7, 2020

Honeywell doesn’t spring to mind when thinking of quantum computing pioneers, but a decade ago the high-tech conglomerate better known for its control systems waded deliberately into the then calmer quantum computing (QC) waters. Fast forward to March when Honeywell announced plans to introduce an ion trap-based quantum computer whose ‘performance’ would... Read more…

By John Russell

Leading Solution Providers

SC 2019 Virtual Booth Video Tour

AMD
AMD
ASROCK RACK
ASROCK RACK
AWS
AWS
CEJN
CJEN
CRAY
CRAY
DDN
DDN
DELL EMC
DELL EMC
IBM
IBM
MELLANOX
MELLANOX
ONE STOP SYSTEMS
ONE STOP SYSTEMS
PANASAS
PANASAS
SIX NINES IT
SIX NINES IT
VERNE GLOBAL
VERNE GLOBAL
WEKAIO
WEKAIO

Contributors

Fujitsu A64FX Supercomputer to Be Deployed at Nagoya University This Summer

February 3, 2020

Japanese tech giant Fujitsu announced today that it will supply Nagoya University Information Technology Center with the first commercial supercomputer powered Read more…

By Tiffany Trader

Tech Conferences Are Being Canceled Due to Coronavirus

March 3, 2020

Several conferences scheduled to take place in the coming weeks, including Nvidia’s GPU Technology Conference (GTC) and the Strata Data + AI conference, have Read more…

By Alex Woodie

Exascale Watch: El Capitan Will Use AMD CPUs & GPUs to Reach 2 Exaflops

March 4, 2020

HPE and its collaborators reported today that El Capitan, the forthcoming exascale supercomputer to be sited at Lawrence Livermore National Laboratory and serve Read more…

By John Russell

Cray to Provide NOAA with Two AMD-Powered Supercomputers

February 24, 2020

The United States’ National Oceanic and Atmospheric Administration (NOAA) last week announced plans for a major refresh of its operational weather forecasting supercomputers, part of a 10-year, $505.2 million program, which will secure two HPE-Cray systems for NOAA’s National Weather Service to be fielded later this year and put into production in early 2022. Read more…

By Tiffany Trader

‘Billion Molecules Against COVID-19’ Challenge to Launch with Massive Supercomputing Support

April 22, 2020

Around the world, supercomputing centers have spun up and opened their doors for COVID-19 research in what may be the most unified supercomputing effort in hist Read more…

By Oliver Peckham

Summit Supercomputer is Already Making its Mark on Science

September 20, 2018

Summit, now the fastest supercomputer in the world, is quickly making its mark in science – five of the six finalists just announced for the prestigious 2018 Read more…

By John Russell

15 Slides on Programming Aurora and Exascale Systems

May 7, 2020

Sometime in 2021, Aurora, the first planned U.S. exascale system, is scheduled to be fired up at Argonne National Laboratory. Cray (now HPE) and Intel are the k Read more…

By John Russell

TACC Supercomputers Run Simulations Illuminating COVID-19, DNA Replication

March 19, 2020

As supercomputers around the world spin up to combat the coronavirus, the Texas Advanced Computing Center (TACC) is announcing results that may help to illumina Read more…

By Staff report

  • arrow
  • Click Here for More Headlines
  • arrow
Do NOT follow this link or you will be banned from the site!
Share This