17th Machine Evaluation Workshop at Daresbury

By Christopher Lazou

December 15, 2006

On December 4th through 6th, 2006, about 250 people (around the same as last year) attended the 17th machine evaluation workshop at CCLRC Daresbury Laboratories, UK. This excellent workshop, in its seventeenth year, is a leading UK national event dedicated to distributed, high performance scientific computing. The principle objective is to encourage close contact between the research communities from the Mathematics, Chemistry, Physics, Engineering and Materials Programmes of EPSRC and the major vendors of mid-range computing systems, workstations, servers, software and peripherals. An increase in academic participation reflected a growing participation from researchers from the other communities, notably from the Natural Environment Research Council (NERC) and Particle Physics & Astronomy (PPARC) Research Council.

Most of the 25 presentations were from vendors, describing their own products on topics such as hardware, compilers, graphics, storage and networking. They focused on cluster solutions, based on commodity chips, interconnect networks and associated file storage systems. An important component of the workshop is the availability of systems for benchmarking evaluation purposes.

In addition, during this year's event there were three parallel, informal breakout sessions. These were focussed on special interest areas, with invited speakers to open the sessions, and have been designed to encourage lively debates, as well as highlight developments and showcase performance features of tools. The breakout sessions' themes were (1) novel architectures (e.g. FPGAs, Cell); (2) software developments enabling higher performance; and (3) Gigabit Ethernet as a high performance interconnect.

There were nineteen companies exhibiting, keen to promote their readymade products, including those based on AMD Opteron, Intel 'Woodcrest' and the Intel Itanium 2 processors. A strong presence of AMD Opteron and Intel 'Woodcrest', dual-core and early quad-core systems, as well as various models of blade products, were on display and available for demonstrations.

Of course other factors often dominate the selection of systems. For example, one trade-off is price/performance. Another is the type and size of application the system is purchased for. This is pertinent especially for commodity clusters and the selection of interconnect fabric. One suspects it depends on how the Total Cost of Ownership (TCO) integral is constructed.

Crispin Keable (IBM) gave a talk titled “And We Also Do Hardware,” describing the three strands IBM is currently pursuing under the Deep Computing umbrella. He reminded the audience that Deep Computing combines a number of techniques — advanced mathematics, domain specific knowledge and software specialisation — to solve extremely complex problems in this sea of digital data. He unconsciously invoked the sentiments from IBM's Quaker progeny by claiming that their strategy is good for the customer, good for the world and good for IBM.
 
Crispin was frank, recognising that sustained performance and scaling is not very high compared to Linpack. The challenge facing the industry is not only system design, for scalability, power consumption, weight and space, but also software — operating systems, compilers, tools, application porting and licensing.

IBM is tackling these issues with the realization that one size does not fit all. The Power based product line provides advanced systems based on loosely coupled clusters. With the recent $244 million HPCS award (equivalent to roughly 2,440 person years — some would say R&D subsidy) this line is expected to culminate in the Power7 to be used in the PERCS petaflops system.

Research collaborations on the Blue Gene/L architecture and the Cell BE multi-core system on a chip were also briefly described. These included the Blue Brain project, which is researching new insights into how the human brain works. The work could be important for the treatment of debilitating diseases such as schizophrenia, autism and Alzheimer's. Using the Cell BE for heart modelling was presented as another example of research collaboration. The Cell BE chip is also being used as the co-processor (accelerator) on the Roadrunner petaflops system at Los Alamos National Laboratory.

Both Blue Gene/L and Cell BE are examples of experimental technologies moving into niche domains and gradually becoming mainstream. IBM believes that next generation chip designs are focusing on high performance/power consumption ratios and that semiconductor power trends are driving future systems. With hundreds of thousands of processors, software development environments will be severely challenged. Issues such as reliability and fault tolerant management systems, to vitiate MTBF effects, represent additional challenges.

As in previous years, the Daresbury Benchmark results were of great interest. These consisted of a plethora of both serial and distributed memory benchmark results, compiled by Martyn Guest and his team from Daresbury. The benchmarks from many systems, including the latest products from vendors using their latest multi-core chips, were presented. The serial component of the benchmark suite, used to obtain these results, consists of many computational chemistry kernel codes, molecular dynamics, Quantum Monte Carlo, Jacobi Solver, STREAM — measured sustainable memory bandwidth in HPC (TRIAD), plus the ab initio molecular electronic structure package GAMESS-UK and the parallel molecular dynamics benchmark, DL_POLY. The results from SPECfp2000, SPECInt2000, HPC Challenge and other well-known benchmarks were also presented.

With the National HECToR capability computing procurement out of the way, Martyn Guest augmented his serial benchmark analysis from previous years by including a variety of parallel applications, measuring not only performance on a single CPU, but extending the analysis to include application performance on commodity clusters. This approach attempted to address the impact of cluster architectures on performance, a more relevant metric for small- and medium-sized university systems.
 
High-end systems such as IBM p690+ P5-575, SGI Altix, HP Superdome Itanium 2 and SD64000B Montecito/1600 and Cray XT3 were measured, but only used as points of reference. Martyn concentrated on capacity-based, modest-sized clusters built out of commodity chips, with a typical usage modality of 32 to 64 cores. Given that usage, it turns out that with a few exceptions (e.g. plane wave Car Parinello codes) an HPC low latency and high bandwidth interconnect is not essential, since the application problems tend to be modest, enabling a replicated data approach. A slower interconnect is cheaper and releases around 20 percent of the funds. With larger systems — 128 plus cores and above — a distributed data approach is often essential; and in this case, one needs a high performance interconnect to achieve efficiency.

Performance data presented included that from some 33 systems under evaluation. Most were commodity clusters, but also included high-end systems from SGI, IBM, HP and Cray. Application performance as a function of processor count included results from the disciplines of molecular simulation, using both replicated and distributed data versions of the DL_POLY code; from molecular electronic structure and materials simulation, using the GAMESS-UK and CPMD codes respectively); and from computational engineering with the DNS turbulence codes, ANGUS and PDNS3D.

With some 30 crowded PowerPoint slides of measurements in multicolour schemes, in the end, the real drama revolved around the comparable performance of clusters based on two chips, the Intel EM64T (3.0 GHz) 'Woodcrest' Xeon 5160 and the AMD 254/2218-F Socket (2.66 GHz) Opteron.

Some truisms never change. Martyn emphasised that single-processor benchmarks often provide misleading results given the complexity of current processors and their subsequent utilisation as the building blocks of n-way cluster nodes. If they are dual-core, use both cores, if four-way cores, use all four so that interactions of cache, memory and communications are accounted for in any performance measure. When more cores are added on a chip, the interconnect fabric for transfer rates (bandwidth) to L3 memory needs to be increased proportionately to handle the extra computational power from the extra cores. Otherwise the sharing of memory paths by the additional cores are likely to degrade overall system performance. This argues strongly for the use of “throughput” or “rate” benchmarks rather than the more traditional single processor metrics.

Looking at SPECfp2000 (Rate-4CPUs) relative to the Sun X4100 (Opteron 254/2.8 GHz, 1CPU), the Dell Power Edge 2950/Xeon 5080 (3.73 GHz) 'Bensley' rate is 2.44, the HP ProLiant BL480c Xeon 5160 (3.0 GHz) 'Woodcrest' rate is 3.16, the Sun X4500 (Opteron 285/2.6 GHz) rate is 3.79 and the Sun Fire X2200 (M2 Opteron 2218/2.6 GHz) rate is 4.3. No one at the meeting gave an adequate explanation for the super-scalar parallelism obtained on the Sun Fire X2200, but remember that these systems deliver less than 100 percent of their peak performance on the SPECfp2000 metric. An interesting table was presented showing application scaling performance when using multi-cores on a chip. In general they scaled reasonably well, although there were a few notable exceptions. One major bottleneck identified was the bandwidth imbalance from L2 to L3 memory, where the transfer rate was for one core, but had to deal with bandwidth requirements of two cores.

Christine Kitchen, of Daresbury Laboratory, focused on the benchmark and procurement support they provide to the academic community for purchasing commodity-based cluster systems affordable by academic departments. Attention focused on the core-benchmark suite provided by Daresbury in support of the on-going SRIF-3 exercise (Scientific Research Investment Fund). With an estimated total expenditure of some £38M on HPC systems, this coordinated procurement is dominating the changing cluster landscape across the UK University sector. Note that this procurement process is coordinated by Tony Newjem of Heriot-Watt University, who also presented at the workshop. Expanding on the results shown by Martyn Guest to include higher processor counts, Christine presented benchmarking statistics derived from some 25 systems of clusters reported by the SRIF-3 framework suppliers. These results reinforced the uncertainty of Gigabit Ethernet as the interconnect of choice, as discussed in the associated workshop break out session, while pointing to the wide range of technical competence and benchmarking prowess within the framework suppliers. Christine emphasised the difficulties in providing a comprehensive overview of all the results given the wide range of requirements that characterised the participating Universities in SRIF-3.

Daresbury's findings suggest that the impact of dual-core technologies on cluster performance is strongly dependent on application –- from negligible impact on molecular simulation codes such as DL-POLY to dramatic performance degradation on DNS engineering codes such as PDNS3D and ANGUS. Averaging across all the applications under consideration leads to the Opteron2218-F/2600 dual-core cluster with Infinipath interconnect delivering, on average, 72 percent of the HP SD64000B Superdome (Itanium2 9050 1.6GHz), and the Intel Xeon 5160 “Woodcrest” dual-core cluster with Infiniband delivering 82 percent of the HP SD64000B. Given the complexity of the chips and uncertainty of metrics, the difference in performance between these leading solutions from Intel and AMD was too close to call.

There are many qualifiers to be considered, not least of which was the nature of the parallel application in question. For example, the replicated data approach of DL-POLY-2 was fine for a small cluster of 32 processors, but a disaster for a 1,000-processor system given that global communication traffic was a killer at this level of processor utilisation. Finally, it should be stressed that the results given were not normalised on price/performance, so no specific value-for-money comparisons were made or implied.

The rest of the workshop consisted of presentations from vendors, with a strong contingent of users sharing their experience in installing clusters, and presentations from a number of companies specialising in providing tailored system solutions from commodity components on demand. Instead of buying pre-packaged products from traditional vendors, a contract is placed with a small computer integration company (e.g., ClusterVision, Streamline) to build a cluster from favoured chips and an interconnect network such as Gigabit Ethernet, InfiniBand or Myrinet. These systems vary in size with a few attaining Top500 status. For example the University of Cambridge cluster, built by ClusterVision, was number 20 in the November 2006 Top500 list.

There are some very positive trends in multi-core chip developments, but the workshop also had some surprises. These are too sensitive to be printed here. For those of you keen to add the latest 'gismos' to your facilities, remember the Latin adage: “caveat emptor”.

As the season of goodwill is upon us: Wishing you all, Seasons Greetings and a Peaceful Happy New Year, 2007.

—–

Copyright (c) Christopher Lazou, HiPerCom Consultants, Ltd., UK. December 2006. Brands and names are the property of their respective owners.

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