One of the more exciting aspects of high performance computing today is that there is no real consensus on what it's going to look like in the next several years or how are we going to get there. Multicore/manycore seems inevitable, yet the software technology is years behind the hardware. Clusters seem unstoppable, but manycore will essentially give you a cluster on a chip. Hardware accelerators and heterogeneous computing promises the ultimate in performance and efficiency, but there's that darn problem of software again.
It would be diplomatic to say that all the different computer architectures will share a place in the future, but that's not usually the way it works out. Commodity clusters effectively killed custom processor-based supercomputers. Multicore technology sent single-core processors into the history books. Clusters and multicore processors became big at the expense of the architectures they replaced. Apparently, diversity has its limits in the marketplace.
Right now, there's a lot of architectural experimentation going on — and not just in the labs. Vendors like Sun are fielding systems based on 8-core, 32-thread processors (T1 UltraSPARC); SiCortex is using MIPS cores and a novel interconnect topology to achieve impressive performance/watt numbers; SGI, Cray and others offer FPGA acceleration with some of their systems; and Cell processors, GPU cards and ClearSpeed boards are each being incorporated into commercial HPC systems to squeeze more FLOPS out of the machines.
For the future, Intel is prototyping 80-core processors for general-purpose computing, while AMD is making plans to integrate CPUs and GPUs on the same processor die.
What will the dominant HPC architecture be in the future and how will the software adapt? Or should the question be reversed? If you wonder about such things, this issue of HPCwire is worth a read. Each of our first three feature articles talks about how HPC hardware architectures and software could move forward — or fail to do so.
Wake up and smell the software
ClearSpeed's John Gustafson pitches the idea that HPC software developers need to rethink how to code their applications for modern architectures. His article talks about the new realities that effect how software should be developed. Briefly, these realites are: processors and memory are cheap; memory bandwidth and software developers are expensive.
His contention is that, unlike in the past, it makes perfect sense to “waste” the abundant RAM and processing resources if it makes the applications more productive or just easier to program. Gustafson wonders, for example, why we obsess so much about processor utilization, instead of focusing on programmer utilization. His basic message is that we need to develop our algorithms in line with the realities of our architectures and the economics of software development.
What could be simpler?
If as Leonardo DaVinci said, “Simplicity is the ultimate sophistication,” then Jud Leonard is on the right track. Our second feature article has Leonard, co-founder and CTO of SiCortex, arguing a different line of attack than Gustafson's. Leonard contends that rather than accepting the current limitations of today's hardware, we should be simplifying the system design to address those limitations. He says that for demanding HPC codes, we still need to be concerned with hardware efficiency, and we need to ensure that legacy codes run efficiently on our future systems.
The key to his approach is to simplify the system at every level (no heterogeneity here). This includes integrating the node's processing hardware as tightly as possible, flattening the inter-node communication network, and synchronizing the clocks of all the node processors. He disparages the current trend of using desktop-derived x86 processors in HPC, noting that this architecture is not well suited to technical computing.
What he describes is all very SiCortex-y, but the broader message is about how much system architects have compromised efficiency for the advantages of using commodity parts. According to Leonard, simplifying the architecture will not only make the machines more efficient, but will also provide a friendlier, more predictable environment for parallel programming.
Putting cores to work
A kinder, gentler parallel programming model is what our third feature article is about. PGI's Michael Wolfe wonders what we're going to do with all those cores that the hardware guys keep threatening us with. Wolfe recently attended two conferences, CGO (Code Generation and Optimization) and PPoPP (Principles and Practice of Parallel Programming), where multicore and parallel programming were understandably hot topics.
The conference discussions inspired him to share a few of his thoughts about the intersection between processor architectures and programming models. Some of the areas Wolfe talks about are transactional memory, GPGPU (which he seems to be lukewarm on), and parallel programming languages. As a compiler engineer, his bit-twiddling perspective provides some interesting insights on how different software approaches might deal with the coming core-quake.
Spring Break for HPCers
Finally, I'd be remiss if I didn't point out our special coverage of the High Performance Computing & Communications Conference (HPCC), which took place in Newport, Rhode Island this week. Our Newport HPCC Conference supplement section in this week's issue has a number of feature articles on the presentations as well as some other highlights from HPCwire contributing writer John E. West, who provided live play-by-play on the proceedings. Thanks John.
The HPCC Conference is in its 21st year and has established itself as the boutique HPC conference of the spring season. It's been held in Newport for so long that people just refer to it as the Newport Conference. John Miguel, the perennial conference organizer, has been heading the event ever since its inception in the 1980s. It's not a highly technical conference, nor is there a big emphasis on exhibitors — just 16 this year. The event is more about finding out what's going on in the industry and what direction the federal government is taking with high-end computing.
“If you want a techie or trade show conference, you go to Supercomputing (SC) in November,” Miguel told me. “Ours is more like a high-level retreat than a conference.”
Every year he tells himself that maybe this will be the last conference. But people always come up to him afterwards and let him know they want to do it again next year. So as long as he can figure out how to pay for it, he says he'll keep the conference going.
As always, comments about HPCwire are welcomed and encouraged. Write to me, Michael Feldman, at [email protected].