Compilers and More: What To Do With All Those Cores?

By Michael Wolfe

April 6, 2007

I just returned from two small conferences, CGO (Code Generation and Optimization, http://www.cgo.org/) and PPoPP (Principles and Practice of Parallel Programming, http://www.ppopp.org/). One of the key themes in both conferences, perhaps the dominating theme, was that multicore chips are here, are mainstream, and we’d better figure out how to use them.

One of the PPoPP attendees, Prof. Rudolf Eigenmann (Purdue Univ.) issued an indictment, saying that we in the parallel programming research community should be ashamed of ourselves. Single-processor systems have run out of steam, something the parallel programming community has been predicting since I was a college student. Now is the time to step up and reap the benefits of all our past work. We’ve had 30 years to study this problem and come up with a solution, but what’s the end result? Surprise! We still have no well-accepted method to generate parallel applications.

We had a similar discussion at one of the workshops before CGO, where someone said that the programming problem would finally get solved because “now we’re motivated!” This implies either that the past thirty years of investigation was being done by the wrong people, or that perhaps now with more people looking at the problem, someone will randomly stumble on a good solution. Science at its best?

Dr. Andrew Chien (Intel), one of the PPoPP keynote speakers, took issue with Eigenmann’s criticism. Chien said that in fact we’ve had a great deal of success in parallel programming: just look at all the massively parallel systems and the applications that run on them. However, halfway through his talk was the slide “Wanted: Breakthrough Innovations in Parallel Programming.” I asked how he could claim past success, then state that breakthrough innovations are needed; it sounded like a typical manager: “good job, now get back to work.” He replied that in the past, parallel programming meant high performance. Now, parallel programming means spreadsheets, games, email, and applications on your laptop. It’s a different target environment, with a different class of programmer, and different expectations.

So parallel programming is hard. Hey, sequential programming is hard too. Adding parallelism just makes it harder. Two of the major problems are expressing the parallelism and synchronizing or communicating between the parallel threads or activities.

An approach to the synchronization problem that is gaining lots of traction is transactional memory, or TM. This takes a page from the successful database community, which has long had to deal with many processes simultaneously accessing and modifying a shared database. Rather than letting a process lock the database, the process executes a transaction; the transaction may involve adding, removing, or modifying relations in the database. While in the middle of a transaction, no other process can see the modifications; at the end, the process commits the results. The database then atomically exposes all the updates to the other processes. In particular, this lets multiple processes modify disjoint parts of the database in parallel without conflict. If two processes try to update the same data at the same time, the first commit will succeed, and the second will fail. The application then has to restart its transaction from the start, since it may have made some decisions based on values that are now stale.

Moving transactions to the parallel programming world means rather than updating shared data in a critical section, the model is to enter a transaction, perform the updates, then commit the changes. The implementation must buffer the modifications until the commit, then atomically commit all the modifications at once. As in a database, if some other parallel thread had made changes to the same shared data, the commit will fail, and the transaction must restart and retry. The expected behavior is that most transactions will succeed, so the retry overhead is quite low.

However, it’s still open as to how to implement the transaction buffering and commit. Modified caches could be used to buffer stores, unless you run out of associativity on the cache line. A separate transactional store queue could be designed, but the size of the queue would limit the size of the transaction.

There are other problems as well. Imagine two transactions, A and B, reading and modifying the same shared data. Suppose transaction B finishes and commits while A is still working. If transaction A then reads some data that was modified by B, A’s commit is likely to fail (in fact, may be guaranteed to fail), since some of the data it read was before B’s commit and some was read after. In fact, the inconsistency may cause A to generate a fault (suppose B allocated or freed a pointer), or loop infinitely; one speaker termed A a “zombie transaction,” the walking dead. It can be important to detect and kill zombies before they get to the commit state, to avoid spurious faults.

In managed software environments (think Java or C#), these problems can be handled in software, and transactions are likely to be successful there. However, it remains unclear how long it will be before transactions can migrate into HPC.

The architectural trends for multicore processing are still in flux as well. One idea is to build an array of small, low-power cores on the chip. Each core is slower on a single thread, but the array of cores could provide a great deal of job throughput. Andrew Chien pointed out that the single stream performance of a core grows roughly relative to the square root of the area, whereas the aggregate performance of a multicore chip grows linearly with the number of cores — a strong argument.

The Sun UltraSPARC T1 (Niagara) processor uses this strategy, with eight cores, each core swapping between four threads (much like the PPUs of the Control Data 6600, back in the late 1960s), giving very high throughput with significant power savings. This sacrifices single-thread performance, and Amdahl’s Law says this will affect parallel applications performance as well.

To solve that problem, some proposed designs use one or two aggressive, out-of-order, deeply pipelined, superscalar (large, power-hungry) cores surrounded by a sea of more tame, in-order, (smaller, power-frugal) cores. A parallel application would run mostly on the sea of slower cores, with the larger cores powered down. When entering a large sequential region on the critical path, the program would shift to the more powerful core.

This idea is not new, I first heard something similar 15 years ago or more, from Samuel Ho, a young PhD candidate at the University of Washington. At that time, he was proposing an Intel 486 surrounded by a bunch of 386s (which gives you the time frame), mostly for reduced cost. Today’s reduced power arguments are more compelling.

In some arenas, multicore has a well-established history. High end graphics processing units (GPUs) in personal computers and workstations have for years exposed a great deal of parallelism, and now look more like a collection of programmable processors with additional functional units, data types, and instructions geared for graphics problems. There are new efforts to expose GPU programming to the more general-purpose high performance market — the so-called GPGPU programming.

However, there are some important caveats. For instance, today’s GPUs implement floating point arithmetic, but only 32-bit precision, and not all the IEEE rounding modes. Some of the operations are not precise to the last ULP (Unit in the Last Place). That much precision isn’t needed in the graphics world, and this simplifies the GPU, making it smaller and faster.

The hardest nut to swallow is the graphics memory, which right now doesn’t implement ECC (error correcting code). With close to a gigabyte of memory, transient single-bit errors are quite possible, but again, in the graphics world, that will likely correspond to a slightly off-shaded pixel somewhere on the screen for one frame, so who cares? In your numerical simulation, that one bit could be a little more important, so perhaps this isn’t quite ready for life-critical applications.

My summary of all the hype for GPGPUs is that processors or coprocessors unconstrained by compatibility requirements, with the freedom to redesign to the latest technology, can deliver higher performance than general purpose CPUs. This is something we’ve known since the days of Floating Point Systems, with its attached FP processors. There are other coprocessors specifically designed for the high performance market, such as the Clearspeed board. GPUs are convenient for the budget-minded, because the development cost is paid for by the consumer games market.

So that’s what we have, and it’s up to you to figure out how to use it. High performance computing, as usual, is left with the crumbs off the table of the mass market.

Right now, we mostly think of multicore chips with 2 or 4 cores, even as Sun prepares the UltraSPARC T2 with 8 cores for release this fall. The sweet spot of high performance parallel computing has been in the range of 4 to 32 processors. Many applications do scale up beyond that, but hardware becomes much more complex to deliver scalable communication bandwidth, and software must be restructured to take advantage of all the parallelism without spending all its time waiting on remote data.

David Callahan (Microsoft Research) pointed out that exponential grows really fast. If we plan on doubling the number of cores on a chip every year or 18 months, it won’t be long before we have hundreds or thousands of cores on a chip. Any software solution aimed at 16 or 32 cores will quickly become irrelevant. We’d better be looking at productive ways to use massively parallel systems, since these may well find their way into our workstations, and yes, even our laptops, before the end of the next decade.

At one CGO panel, the moderator asked the audience whether new languages were needed for multicore. The response was somewhat tepid. It’s not clear that multicore is the reason for developing new languages. There are several research projects looking at designing or modifying languages specifically for developing scalable parallel applications.

Several of these project involve the so-called PGAS (Partitioned Global Address Space) languages. The main idea is the data is explicitly and visibly partitioned across the parallel machine, but any thread running on any node can fetch or store remote data directly. This promotes MPI-style programming, with most of the computation on local data, but exposes the communication as a language primitive instead of using opaque library calls. They try to get the advantages of HPF (High Performance Fortran), such as global addressability, without relying on unproven compiler technology.

DARPA, as part of its High Productivity Computing Systems (HPCS) project, is sponsoring the development of three new languages; see the HPCwire Q&A with Rusty Lusk for a summary. Recently I took a tutorial of IBM’s HPCS language, X10. It includes some of the PGAS ideas for parallelism, and allows for several ways to express parallelism at multiple levels beyond just data parallelism. It will be quite interesting to watch the evolution of these languages, but if this tutorial is indicative of their maturity, we have years of development before they are ready for real users.

So what’s the answer to the question in this article’s title? What DO we do with all those cores? The gold standard which we would like to achieve is to make them invisible. Upgrading to a multicore processor should be as simple and as effective as upgrading to a faster processor was in years past.

Previously, improvements to microarchitectural elements, such as branch prediction, out-of-order execution control units and pipelined functional units, were, for the most part, invisible from software. Instruction-set architectural changes, such as the SSE and SSE2 registers and instructions, were visible to the compiler, but largely hidden from the programmer.

Some architectural enhancements are significant enough that changing the program to take advantage of them is worth the effort. The packed SSE instructions on x86 processors and the vector instructions of classical supercomputers fall into this category. If we can make multicore processors no harder to use than this, we will have succeeded. The biggest barrier is that the architecture and the OS today present the multicore processor as indistinguishable from a multiprocessor. We need hardware and software mechanisms to allow compilers and developers to take advantage of these multicore chips as powerful processors. That is the next short-term challenge and will be the subject of a future column.

—–

Michael Wolfe has developed compilers for over 30 years in both academia and industry, and is now a senior compiler engineer at The Portland Group, Inc. (www.pgroup.com), a wholly-owned subsidiary of STMicroelectronics, Inc. The opinions stated here are those of the author, and do not represent opinions of The Portland Group, Inc. or STMicroelectronics, Inc.

Subscribe to HPCwire's Weekly Update!

Be the most informed person in the room! Stay ahead of the tech trends with industy updates delivered to you every week!

European HPC Summit Week and PRACEdays 2018: Slaying Dragons and SHAPEing Futures One SME at a Time

June 20, 2018

The University of Ljubljana in Slovenia hosted the third annual EHPCSW18 and fifth annual PRACEdays18 events which opened May 29, 2018. The conference was chaired by PRACE Council Vice-Chair Sergi Girona (Barcelona Super Read more…

By Elizabeth Leake (STEM-Trek for HPCwire)

An Overview of ‘OpenACC for Programmers’ from the Book’s Editors

June 20, 2018

In an era of multicore processors coupled with manycore accelerators in all kinds of devices from smartphones all the way to supercomputers, it is important to train current and future computational scientists of all dom Read more…

By Sunita Chandrasekaran and Guido Juckeland

Cray Introduces All Flash Lustre Storage Solution Targeting HPC

June 19, 2018

Citing the rise of IOPS-intensive workflows and more affordable flash technology, Cray today introduced the L300F, a scalable all-flash storage solution whose primary use case is to support high IOPS rates to/from a scra Read more…

By John Russell

HPE Extreme Performance Solutions

HPC and AI Convergence is Accelerating New Levels of Intelligence

Data analytics is the most valuable tool in the digital marketplace – so much so that organizations are employing high performance computing (HPC) capabilities to rapidly collect, share, and analyze endless streams of data. Read more…

IBM Accelerated Insights

Preview the World’s Smartest Supercomputer at ISC 2018

Introducing an accelerated IT infrastructure for HPC & AI workloads Read more…

Lenovo to Debut ‘Neptune’ Cooling Technologies at ISC

June 19, 2018

Lenovo today announced a set of cooling technologies, dubbed Neptune, that include direct to node (DTN) warm water cooling, rear door heat exchanger (RDHX), and hybrid solutions that combine air and liquid cooling. Lenov Read more…

By John Russell

European HPC Summit Week and PRACEdays 2018: Slaying Dragons and SHAPEing Futures One SME at a Time

June 20, 2018

The University of Ljubljana in Slovenia hosted the third annual EHPCSW18 and fifth annual PRACEdays18 events which opened May 29, 2018. The conference was chair Read more…

By Elizabeth Leake (STEM-Trek for HPCwire)

Cray Introduces All Flash Lustre Storage Solution Targeting HPC

June 19, 2018

Citing the rise of IOPS-intensive workflows and more affordable flash technology, Cray today introduced the L300F, a scalable all-flash storage solution whose p Read more…

By John Russell

Sandia to Take Delivery of World’s Largest Arm System

June 18, 2018

While the enterprise remains circumspect on prospects for Arm servers in the datacenter, the leadership HPC community is taking a bolder, brighter view of the x86 server CPU alternative. Amongst current and planned Arm HPC installations – i.e., the innovative Mont-Blanc project, led by Bull/Atos, the 'Isambard’ Cray XC50 going into the University of Bristol, and commitments from both Japan and France among others -- HPE is announcing that it will be supply the United States National Nuclear Security Administration (NNSA) with a 2.3 petaflops peak Arm-based system, named Astra. Read more…

By Tiffany Trader

The Machine Learning Hype Cycle and HPC

June 14, 2018

Like many other HPC professionals I’m following the hype cycle around machine learning/deep learning with interest. I subscribe to the view that we’re probably approaching the ‘peak of inflated expectation’ but not quite yet starting the descent into the ‘trough of disillusionment. This still raises the probability that... Read more…

By Dairsie Latimer

Xiaoxiang Zhu Receives the 2018 PRACE Ada Lovelace Award for HPC

June 13, 2018

Xiaoxiang Zhu, who works for the German Aerospace Center (DLR) and Technical University of Munich (TUM), was awarded the 2018 PRACE Ada Lovelace Award for HPC for her outstanding contributions in the field of high performance computing (HPC) in Europe. Read more…

By Elizabeth Leake

U.S Considering Launch of National Quantum Initiative

June 11, 2018

Sometime this month the U.S. House Science Committee will introduce legislation to launch a 10-year National Quantum Initiative, according to a recent report by Read more…

By John Russell

ORNL Summit Supercomputer Is Officially Here

June 8, 2018

Oak Ridge National Laboratory (ORNL) together with IBM and Nvidia celebrated the official unveiling of the Department of Energy (DOE) Summit supercomputer toda Read more…

By Tiffany Trader

Exascale USA – Continuing to Move Forward

June 6, 2018

The end of May 2018, saw several important events that continue to advance the Department of Energy’s (DOE) Exascale Computing Initiative (ECI) for the United Read more…

By Alex R. Larzelere

MLPerf – Will New Machine Learning Benchmark Help Propel AI Forward?

May 2, 2018

Let the AI benchmarking wars begin. Today, a diverse group from academia and industry – Google, Baidu, Intel, AMD, Harvard, and Stanford among them – releas Read more…

By John Russell

How the Cloud Is Falling Short for HPC

March 15, 2018

The last couple of years have seen cloud computing gradually build some legitimacy within the HPC world, but still the HPC industry lies far behind enterprise I Read more…

By Chris Downing

US Plans $1.8 Billion Spend on DOE Exascale Supercomputing

April 11, 2018

On Monday, the United States Department of Energy announced its intention to procure up to three exascale supercomputers at a cost of up to $1.8 billion with th Read more…

By Tiffany Trader

Deep Learning at 15 PFlops Enables Training for Extreme Weather Identification at Scale

March 19, 2018

Petaflop per second deep learning training performance on the NERSC (National Energy Research Scientific Computing Center) Cori supercomputer has given climate Read more…

By Rob Farber

Lenovo Unveils Warm Water Cooled ThinkSystem SD650 in Rampup to LRZ Install

February 22, 2018

This week Lenovo took the wraps off the ThinkSystem SD650 high-density server with third-generation direct water cooling technology developed in tandem with par Read more…

By Tiffany Trader

ORNL Summit Supercomputer Is Officially Here

June 8, 2018

Oak Ridge National Laboratory (ORNL) together with IBM and Nvidia celebrated the official unveiling of the Department of Energy (DOE) Summit supercomputer toda Read more…

By Tiffany Trader

Nvidia Responds to Google TPU Benchmarking

April 10, 2017

Nvidia highlights strengths of its newest GPU silicon in response to Google's report on the performance and energy advantages of its custom tensor processor. Read more…

By Tiffany Trader

Hennessy & Patterson: A New Golden Age for Computer Architecture

April 17, 2018

On Monday June 4, 2018, 2017 A.M. Turing Award Winners John L. Hennessy and David A. Patterson will deliver the Turing Lecture at the 45th International Sympo Read more…

By Staff

Leading Solution Providers

SC17 Booth Video Tours Playlist

Altair @ SC17

Altair

AMD @ SC17

AMD

ASRock Rack @ SC17

ASRock Rack

CEJN @ SC17

CEJN

DDN Storage @ SC17

DDN Storage

Huawei @ SC17

Huawei

IBM @ SC17

IBM

IBM Power Systems @ SC17

IBM Power Systems

Intel @ SC17

Intel

Lenovo @ SC17

Lenovo

Mellanox Technologies @ SC17

Mellanox Technologies

Microsoft @ SC17

Microsoft

Penguin Computing @ SC17

Penguin Computing

Pure Storage @ SC17

Pure Storage

Supericro @ SC17

Supericro

Tyan @ SC17

Tyan

Univa @ SC17

Univa

Google Chases Quantum Supremacy with 72-Qubit Processor

March 7, 2018

Google pulled ahead of the pack this week in the race toward "quantum supremacy," with the introduction of a new 72-qubit quantum processor called Bristlecone. Read more…

By Tiffany Trader

Google I/O 2018: AI Everywhere; TPU 3.0 Delivers 100+ Petaflops but Requires Liquid Cooling

May 9, 2018

All things AI dominated discussion at yesterday’s opening of Google’s I/O 2018 developers meeting covering much of Google's near-term product roadmap. The e Read more…

By John Russell

Nvidia Ups Hardware Game with 16-GPU DGX-2 Server and 18-Port NVSwitch

March 27, 2018

Nvidia unveiled a raft of new products from its annual technology conference in San Jose today, and despite not offering up a new chip architecture, there were still a few surprises in store for HPC hardware aficionados. Read more…

By Tiffany Trader

Pattern Computer – Startup Claims Breakthrough in ‘Pattern Discovery’ Technology

May 23, 2018

If it weren’t for the heavy-hitter technology team behind start-up Pattern Computer, which emerged from stealth today in a live-streamed event from San Franci Read more…

By John Russell

HPE Wins $57 Million DoD Supercomputing Contract

February 20, 2018

Hewlett Packard Enterprise (HPE) today revealed details of its massive $57 million HPC contract with the U.S. Department of Defense (DoD). The deal calls for HP Read more…

By Tiffany Trader

Part One: Deep Dive into 2018 Trends in Life Sciences HPC

March 1, 2018

Life sciences is an interesting lens through which to see HPC. It is perhaps not an obvious choice, given life sciences’ relative newness as a heavy user of H Read more…

By John Russell

Intel Pledges First Commercial Nervana Product ‘Spring Crest’ in 2019

May 24, 2018

At its AI developer conference in San Francisco yesterday, Intel embraced a holistic approach to AI and showed off a broad AI portfolio that includes Xeon processors, Movidius technologies, FPGAs and Intel’s Nervana Neural Network Processors (NNPs), based on the technology it acquired in 2016. Read more…

By Tiffany Trader

Google Charts Two-Dimensional Quantum Course

April 26, 2018

Quantum error correction, essential for achieving universal fault-tolerant quantum computation, is one of the main challenges of the quantum computing field and it’s top of mind for Google’s John Martinis. At a presentation last week at the HPC User Forum in Tucson, Martinis, one of the world's foremost experts in quantum computing, emphasized... Read more…

By Tiffany Trader

  • arrow
  • Click Here for More Headlines
  • arrow
Do NOT follow this link or you will be banned from the site!
Share This