Bits and Bytes From IDF

By Michael Feldman

April 20, 2007

The semi-annual Intel Developer Forum (IDF) took place in Beijing, China this week, a venue chosen to signify the importance of China to Intel. Not only is the Chinese IT market one of the most rapidly growing in the world, but Intel also has very large business commitments there. Currently, the company employs over 6000 employees in the country and has substantial investments in R&D and microprocessor assembly and testing. Intel recently announced they're building a $2.5 billion 300mm wafer fab in Dalian, bringing the company's total stake in China to 3.8 billion. So yes, China is important to them.

The IDF event gives Intel the opportunity to keep its customers and partners happy and titillate industry watchers. For those of us with limited travel budgets, Intel supplied an analyst/press phone briefing of the Beijing proceedings, hosted by Sean Maloney, Intel's chief sales and marketing officer. Although no big announcements were forthcoming at IDF, the company managed to pique my interest in a few areas.

Since Intel is between its “tick-tock” product cycle, having released most of the Core 65nm “tock” offerings, a lot of the talk at IDF was looking at the upcoming “tick” products — the Penryn processor family. With initial product releases scheduled for the latter half of this year, the Penryn processors will be implemented on the companies recently announced 45nm High-K plus metal gate silicon process technology. And just in case anyone has forgotten about the importance of this technology in the past few months, Maloney reminded us:

“We believe we've achieved a significant breakthrough in transistor technology by developing the High-K metal gate transistors … the biggest breakthrough in transistor technology in the last 40 years.”

The shrink to 45nm will give the Penryn products twice the transistor budget of the 65nm products and support higher clock speeds, lower power, or some combination of the two. It looks like Intel will be pushing the clock whenever possible. The company provided some preliminary benchmarks with a pre-production 3.3 GHz processor with a 1600 MHz front side bus. For HPC and workstation systems running bandwidth-intensive applications they achieved a 45 percent performance increase compared to the current quad-core Intel Xeon X5355 processor. Not bad, but there was no mention of the benchmark being used.

The new cores will also support 47 new SSE4 instructions, which are designed to accelerate applications involving digital media processing, memory-intensive workloads, HPC workloads and text searching, to name a few. According to Intel, SSE4 is their largest ISA extension in terms of scope impact since SSE2. Jon Stokes details some of the new capabilities of the SSE4 technology in an article published in Ars Technica.

The new 45nm “tock” offerings, represented by the Nehalem processor family, is slated to start production in 2008. These chips will contain up to 8 cores. Simultaneous multi-threading, an evolution of Intel's Hyper-threading technology, will also be included in the Nehalem cores. At least some of the these processors will include a new system interconnect (presumably Intel's forthcoming Common System Interconnect) as well as on-chip memory controllers, an architecture that mimics AMD's Opteron processor.

Speaking of the Common System Interconnect (CSI), on Tuesday at the Gelato ICE conference in San Jose, Intel released a few details about how this technology will fit into their Itanium roadmap. According to Jim Fister in Intel's Digital Enterprise group, Tukwilla, the four-core Itanium processor slated for 2008, will be the first chip to incorporate CSI, replacing the front-side bus that has been the mainstay of Intel processors. EETimes has posted a nice article from Rick Merrit about this topic.

Back to Beijing. In another nod to AMD design, Intel outlined its QuickAssist technology, which appears to be an evolution of their Geneseo initiative. QuickAssist will work analogously to AMD's Torrenza technology, allowing third-party coprocessors to link to Intel processors. In Intel's version, their interconnect platform is based on PCI Express, rather than HyperTransport. QuickAssist is designed to be used for specialized accelerators that target math-intensive, graphics, or embedded content workloads.

Maybe the biggest non-announcement announcement of the IDF event was the admission of the Intel's Larrabee technology, something that had been rumored for months now. But during Intel's press briefing, Maloney refuse to give any details on the technology, dodging every question on the topic. Here's the minimalist quote from the press release:

“Intel has begun planning products based on a highly parallel, IA-based programmable architecture codenamed 'Larrabee.' It will be easily programmable using many existing software tools, and designed to scale to trillions of floating point operations per second (Teraflops) of performance. The Larrabee architecture will include enhancements to accelerate applications such as scientific computing, recognition, mining, synthesis, visualization, financial analytics and health applications.”

The only new factoid here is that the silicon would be compatible with current Intel products. Reports from IDF about Pat Gelsinger's comments on Larrabee revealed a few more tidbits. Gelsinger, the senior vice president and co-general manager of Intel's Digital Enterprise Group, said Larrabee products would support varying numbers of processing cores, depending on the targeted application, and will be based on the x86 ISA.

In the past, industry analysts had speculated that Larrabee referred to some kind of high-end GPU silicon that would go head-to-head with AMD and NVIDIA graphics processors that are aimed at GPGPU (general purpose processing with GPUs) workloads. But Gelsinger dismissed the GPGPU model, stating that graphics processors are not general purpose.

“[T]his will end the GPGPU debate,” wrote Gelsinger in a blog entry posted on Tuesday. “Solving the programmability of any such highly parallel machines is the key problem and IA programmability is the solution.”

In any case, the Larrabee technology may end up looking similar to the GPGPU platforms envisioned by AMD and NVIDIA, namely, processors that incorporate elements of CPUs with elements of GPUs. Reading between the lines, it looks like Intel could be thinking of a multicore streaming SIMD architecture based on their native SSE instruction set — think multiple SSE units. The SIMD cores could be isolated on their own die or mixed with non-SSE x86 silicon in some fashion. However it's implemented, Larrabee looks like the basis of a hardware platform designed to run RMS (Recognition, Mining, and Synthesis) applications, Intel's vision of next-generation workloads for 2010 and beyond.


As always, comments about HPCwire are welcomed and encouraged. Write to me, Michael Feldman, at [email protected].

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