TRIPS Processor Marches to a Different Drummer

By Michael Feldman

May 4, 2007

In the midst of the multicore frenzy that has enveloped processor design over the past several years, researchers at the University of Texas (UT) have been methodically working on a very different kind of chip architecture. With $20 million of funding, primarily from DARPA, the UT research team developed the Tera-op Reliable Intelligently adaptive Processing Systems (TRIPS) architecture. On Monday, the team, led by UT professors Doug Burger, Steve Keckler and Kathryn McKinley, unveiled the first TRIPS prototype.

Today, the commercial solution to high performance is to add more cores to general purpose processors (i.e., x86, Power, UltraSPARC) or use special processing units for acceleration (i.e., GPUs, the Cell processor, ClearSpeed boards). In contrast, TRIPS uses heavy-duty instruction-level concurrency to achieve high levels of performance. It does this via its EDGE ISA, which allows a compiler to specify the data dependencies during code generation. The rationale is that this frees the hardware from having to reconstruct these dependencies at runtime. More than that, a TRIPS processor is able to change its execution behavior based on the application profile, so that workloads requiring different levels of parallelism (instruction, data, and thread) may all be accommodated efficiently.

It is this polymorphic behavior that is of particular interest to DARPA. Currently the Department of Defense (DoD) builds numerous mobile computing systems that incorporate a vast range of custom ASICs, often alongside general-purpose commodity processors. In this type of environment, the workload is often volatile. The specialized and general-purpose processors become idle or stressed as the workload throttles up and down, reducing system efficiency. The DoD would love to find a solution that can approach the performance of a specialized processor, yet retain the ability to be used for many different types of applications.

This is not just a military notion. A polymorphic processor could be applied to any application that consisted of high performance heterogeneous workloads, embedded or otherwise. In HPC, the conventional answer to heterogeneity is to use different types of processors. For example, Cray's “Adaptive Supercomputing” strategy is to apply a variety of processors (vector, scalar, multithreading) that excel at different types of workloads. Other vendors are experimenting with hardware accelerators, like FPGAs or Cell processors, as add-ons to conventional HPC servers.

“We're trying to come up with a [common] substrate that would work well with many different types of applications — especially those without explicit concurrency built in,” explained Keckler.

The processor demonstrated at the University of Texas consisted of two TRIPS cores, each one capable of executing up to 16 instructions per clock cycle, from as many as 1024 in-flight instructions. The prototype was manufactured by IBM on 130nm technology and runs at 366 MHz. It achieves 12 gigaflops and consumes 45 watts at peak power.

A mere 12 gigaflops at 45 watts isn't going to turn many heads today. For comparison, a quad-core Xeon processor achieves 62 gigaflops at 120 watts. But the TRIPS prototype was implemented on process technology that's two generation behind the state-of-the-art and the TRIPS system design didn't bother to implement power saving circuitry such as clock gating, a common technology used to optimize processor power consumption.

On a 65nm process technology with appropriate clock gating, the TRIPS researchers expect much higher clock rates and lower power consumption. They believe that the performance per watt for this technology is going to be extremely competitive with current CISC and RISC offerings. Using the clock-neutral metric of instructions retired per clock cycle, the prototype has achieved between three and four times better performance than Intel's commercial Core 2 processors on a variety of application workloads, including signal processing, dense linear algebra, desktop and embedded.

“It is very promising,” said Burger. “If you can imagine a major company putting a full design team behind it, they could push it a lot further than we could. And where we are is already pretty good with a small academic team.”

One of the big advantages of exploiting instruction-level parallelism is a reduction of the memory wall problem — where processor performance overruns memory performance. Multicore, multithreading solutions exacerbate this problem by enabling more threads to compete for limited memory bandwidth. Typically each thread will access different data in the cache, putting more stress on the bandwidth of the memory system. Since TRIPS is able to keep up to 1024 instructions in flight, a lot of work can done while the next memory request completes. It's not that TRIPS has solved the memory wall problem, but speeding up the individual processors relieves some of pressure on the memory system.

“Our processor tends to be much more latency tolerant.” said Burger. “So if you have bandwidth burst issues, we can tolerate those and have fewer stalls, relative to more conventional architectures.”

The prototype demonstrated this week may be the first and last one developed without commercial involvement. Due to the economics of semiconductor manufacturing, it's become prohibitively expensive for an academic venture, even one backed by DARPA, to produce a lot of silicon. Thus the UT team is actively looking for commercial suitors. IBM, Intel, Sun and AMD would be the most likely candidates, although some of the embedded chip manufacturers may be tempted as well.

The hard-sell for TRIPS is going to be attracting chipmakers to take the technology into the commercial realm. Any company capable of introducing a new processor already has a large investment in their own architectures. And their customers have an even larger investment in the ISAs of those architectures. But the TRIPS researchers believe that a disruptive technology will be adopted if people feel enough pain. And in their view, multicore is going to be delivering that pain pretty quickly.

“What we're offering is a technology that requires an instruction set change,” said Burger. “And in a few generations, what the industry is going to be offering is a technology that requires a programming model and software change. Which is more painful?”

The UT team is already working on the next generation of the architecture. They say that the new version will be based on the EDGE ISA, but will be implemented with a new microarchitecture. One specific area the researchers are pursuing is scalable multithreading. What they would like to achieve is a processor with the flexibility to act like a fine-grained multithreaded architecture when you have lots of threads, and a really powerful single-threaded processor when you don't. With what they've learned with TRIPS, they believe they have a lot of room to explore some new approaches.

“As an architect, it's really exciting to be on the edge of the inflection point,” said Burger. “We're working on one approach; other people are working on others. It's a big fermenting stew right now and no one knows what's going to happen.”

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