TRIPS Processor Marches to a Different Drummer

By Michael Feldman

May 4, 2007

In the midst of the multicore frenzy that has enveloped processor design over the past several years, researchers at the University of Texas (UT) have been methodically working on a very different kind of chip architecture. With $20 million of funding, primarily from DARPA, the UT research team developed the Tera-op Reliable Intelligently adaptive Processing Systems (TRIPS) architecture. On Monday, the team, led by UT professors Doug Burger, Steve Keckler and Kathryn McKinley, unveiled the first TRIPS prototype.

Today, the commercial solution to high performance is to add more cores to general purpose processors (i.e., x86, Power, UltraSPARC) or use special processing units for acceleration (i.e., GPUs, the Cell processor, ClearSpeed boards). In contrast, TRIPS uses heavy-duty instruction-level concurrency to achieve high levels of performance. It does this via its EDGE ISA, which allows a compiler to specify the data dependencies during code generation. The rationale is that this frees the hardware from having to reconstruct these dependencies at runtime. More than that, a TRIPS processor is able to change its execution behavior based on the application profile, so that workloads requiring different levels of parallelism (instruction, data, and thread) may all be accommodated efficiently.

It is this polymorphic behavior that is of particular interest to DARPA. Currently the Department of Defense (DoD) builds numerous mobile computing systems that incorporate a vast range of custom ASICs, often alongside general-purpose commodity processors. In this type of environment, the workload is often volatile. The specialized and general-purpose processors become idle or stressed as the workload throttles up and down, reducing system efficiency. The DoD would love to find a solution that can approach the performance of a specialized processor, yet retain the ability to be used for many different types of applications.

This is not just a military notion. A polymorphic processor could be applied to any application that consisted of high performance heterogeneous workloads, embedded or otherwise. In HPC, the conventional answer to heterogeneity is to use different types of processors. For example, Cray's “Adaptive Supercomputing” strategy is to apply a variety of processors (vector, scalar, multithreading) that excel at different types of workloads. Other vendors are experimenting with hardware accelerators, like FPGAs or Cell processors, as add-ons to conventional HPC servers.

“We're trying to come up with a [common] substrate that would work well with many different types of applications — especially those without explicit concurrency built in,” explained Keckler.

The processor demonstrated at the University of Texas consisted of two TRIPS cores, each one capable of executing up to 16 instructions per clock cycle, from as many as 1024 in-flight instructions. The prototype was manufactured by IBM on 130nm technology and runs at 366 MHz. It achieves 12 gigaflops and consumes 45 watts at peak power.

A mere 12 gigaflops at 45 watts isn't going to turn many heads today. For comparison, a quad-core Xeon processor achieves 62 gigaflops at 120 watts. But the TRIPS prototype was implemented on process technology that's two generation behind the state-of-the-art and the TRIPS system design didn't bother to implement power saving circuitry such as clock gating, a common technology used to optimize processor power consumption.

On a 65nm process technology with appropriate clock gating, the TRIPS researchers expect much higher clock rates and lower power consumption. They believe that the performance per watt for this technology is going to be extremely competitive with current CISC and RISC offerings. Using the clock-neutral metric of instructions retired per clock cycle, the prototype has achieved between three and four times better performance than Intel's commercial Core 2 processors on a variety of application workloads, including signal processing, dense linear algebra, desktop and embedded.

“It is very promising,” said Burger. “If you can imagine a major company putting a full design team behind it, they could push it a lot further than we could. And where we are is already pretty good with a small academic team.”

One of the big advantages of exploiting instruction-level parallelism is a reduction of the memory wall problem — where processor performance overruns memory performance. Multicore, multithreading solutions exacerbate this problem by enabling more threads to compete for limited memory bandwidth. Typically each thread will access different data in the cache, putting more stress on the bandwidth of the memory system. Since TRIPS is able to keep up to 1024 instructions in flight, a lot of work can done while the next memory request completes. It's not that TRIPS has solved the memory wall problem, but speeding up the individual processors relieves some of pressure on the memory system.

“Our processor tends to be much more latency tolerant.” said Burger. “So if you have bandwidth burst issues, we can tolerate those and have fewer stalls, relative to more conventional architectures.”

The prototype demonstrated this week may be the first and last one developed without commercial involvement. Due to the economics of semiconductor manufacturing, it's become prohibitively expensive for an academic venture, even one backed by DARPA, to produce a lot of silicon. Thus the UT team is actively looking for commercial suitors. IBM, Intel, Sun and AMD would be the most likely candidates, although some of the embedded chip manufacturers may be tempted as well.

The hard-sell for TRIPS is going to be attracting chipmakers to take the technology into the commercial realm. Any company capable of introducing a new processor already has a large investment in their own architectures. And their customers have an even larger investment in the ISAs of those architectures. But the TRIPS researchers believe that a disruptive technology will be adopted if people feel enough pain. And in their view, multicore is going to be delivering that pain pretty quickly.

“What we're offering is a technology that requires an instruction set change,” said Burger. “And in a few generations, what the industry is going to be offering is a technology that requires a programming model and software change. Which is more painful?”

The UT team is already working on the next generation of the architecture. They say that the new version will be based on the EDGE ISA, but will be implemented with a new microarchitecture. One specific area the researchers are pursuing is scalable multithreading. What they would like to achieve is a processor with the flexibility to act like a fine-grained multithreaded architecture when you have lots of threads, and a really powerful single-threaded processor when you don't. With what they've learned with TRIPS, they believe they have a lot of room to explore some new approaches.

“As an architect, it's really exciting to be on the edge of the inflection point,” said Burger. “We're working on one approach; other people are working on others. It's a big fermenting stew right now and no one knows what's going to happen.”

Subscribe to HPCwire's Weekly Update!

Be the most informed person in the room! Stay ahead of the tech trends with industy updates delivered to you every week!

Supercomputers Take to the Solar Winds

June 5, 2020

The whims of the solar winds – charged particles flowing from the Sun’s atmosphere – can interfere with systems that are now crucial for modern life, such as satellites and GPS services – but these winds can be d Read more…

By Oliver Peckham

HPC in O&G: Deep Sea Drilling – What Happens Now   

June 4, 2020

At the beginning of March I attended the Rice Oil & Gas HPC conference in Houston. That seems a long time ago now. It’s a great event where oil and gas specialists join with compute veterans and the discussion tell Read more…

By Rosemary Francis

NCSA Wades into Post-Blue Waters Era with Delta Supercomputer

June 3, 2020

NSF has awarded the National Center for Supercomputing Applications (NCSA) $10 million for its next supercomputer - named Delta – “which will kick-start NCSA’s next generation of supercomputers post-Blue Waters,” Read more…

By John Russell

Dell Integrates Bitfusion for vHPC, GPU ‘Pools’

June 3, 2020

Dell Technologies advanced its hardware virtualization strategy to AI workloads this week with the introduction of capabilities aimed at expanding access to GPU and HPC services via its EMC, VMware and recently acquired Read more…

By George Leopold

Supercomputers Streamline Prediction of Dangerous Arrhythmia

June 2, 2020

Heart arrhythmia can prove deadly, contributing to the hundreds of thousands of deaths from cardiac arrest in the U.S. every year. Unfortunately, many of those arrhythmia are induced as side effects from various medicati Read more…

By Staff report

AWS Solution Channel

Join AWS, Univa and Intel for This Informative Session!

Event Date: June 18, 2020

More enterprises than ever are turning to HPC cloud computing. Whether you’re just getting started, or more mature in your use of cloud, this HPC Cloud webinar is an excellent opportunity to gain valuable insights and knowledge to help accelerate your HPC cloud projects. Read more…

Indiana University to Deploy Jetstream 2 Cloud with AMD, Nvidia Technology

June 2, 2020

Indiana University has been awarded a $10 million NSF grant to build ‘Jetstream 2,’ a cloud computing system that will provide 8 aggregate petaflops of computing capability in support of data analysis and AI workload Read more…

By Tiffany Trader

NCSA Wades into Post-Blue Waters Era with Delta Supercomputer

June 3, 2020

NSF has awarded the National Center for Supercomputing Applications (NCSA) $10 million for its next supercomputer - named Delta – “which will kick-start NCS Read more…

By John Russell

Indiana University to Deploy Jetstream 2 Cloud with AMD, Nvidia Technology

June 2, 2020

Indiana University has been awarded a $10 million NSF grant to build ‘Jetstream 2,’ a cloud computing system that will provide 8 aggregate petaflops of comp Read more…

By Tiffany Trader

10nm, 7nm, 5nm…. Should the Chip Nanometer Metric Be Replaced?

June 1, 2020

The biggest cool factor in server chips is the nanometer. AMD beating Intel to a CPU built on a 7nm process node* – with 5nm and 3nm on the way – has been i Read more…

By Doug Black

COVID-19 HPC Consortium Expands to Europe, Reports on Research Projects

May 28, 2020

The COVID-19 HPC Consortium, a public-private effort delivering free access to HPC processing for scientists pursuing coronavirus research – some utilizing AI Read more…

By Doug Black

$100B Plan Submitted for Massive Remake and Expansion of NSF

May 27, 2020

Legislation to reshape, expand - and rename - the National Science Foundation has been submitted in both the U.S. House and Senate. The proposal, which seems to Read more…

By John Russell

IBM Boosts Deep Learning Accuracy on Memristive Chips

May 27, 2020

IBM researchers have taken another step towards making in-memory computing based on phase change (PCM) memory devices a reality. Papers in Nature and Frontiers Read more…

By John Russell

Hats Over Hearts: Remembering Rich Brueckner

May 26, 2020

HPCwire and all of the Tabor Communications family are saddened by last week’s passing of Rich Brueckner. He was the ever-optimistic man in the Red Hat presiding over the InsideHPC media portfolio for the past decade and a constant presence at HPC’s most important events. Read more…

Nvidia Q1 Earnings Top Expectations, Datacenter Revenue Breaks $1B

May 22, 2020

Nvidia’s seemingly endless roll continued in the first quarter with the company announcing blockbuster earnings that exceeded Wall Street expectations. Nvidia Read more…

By Doug Black

Supercomputer Modeling Tests How COVID-19 Spreads in Grocery Stores

April 8, 2020

In the COVID-19 era, many people are treating simple activities like getting gas or groceries with caution as they try to heed social distancing mandates and protect their own health. Still, significant uncertainty surrounds the relative risk of different activities, and conflicting information is prevalent. A team of Finnish researchers set out to address some of these uncertainties by... Read more…

By Oliver Peckham

[email protected] Turns Its Massive Crowdsourced Computer Network Against COVID-19

March 16, 2020

For gamers, fighting against a global crisis is usually pure fantasy – but now, it’s looking more like a reality. As supercomputers around the world spin up Read more…

By Oliver Peckham

[email protected] Rallies a Legion of Computers Against the Coronavirus

March 24, 2020

Last week, we highlighted [email protected], a massive, crowdsourced computer network that has turned its resources against the coronavirus pandemic sweeping the globe – but [email protected] isn’t the only game in town. The internet is buzzing with crowdsourced computing... Read more…

By Oliver Peckham

Global Supercomputing Is Mobilizing Against COVID-19

March 12, 2020

Tech has been taking some heavy losses from the coronavirus pandemic. Global supply chains have been disrupted, virtually every major tech conference taking place over the next few months has been canceled... Read more…

By Oliver Peckham

Supercomputer Simulations Reveal the Fate of the Neanderthals

May 25, 2020

For hundreds of thousands of years, neanderthals roamed the planet, eventually (almost 50,000 years ago) giving way to homo sapiens, which quickly became the do Read more…

By Oliver Peckham

DoE Expands on Role of COVID-19 Supercomputing Consortium

March 25, 2020

After announcing the launch of the COVID-19 High Performance Computing Consortium on Sunday, the Department of Energy yesterday provided more details on its sco Read more…

By John Russell

Steve Scott Lays Out HPE-Cray Blended Product Roadmap

March 11, 2020

Last week, the day before the El Capitan processor disclosures were made at HPE's new headquarters in San Jose, Steve Scott (CTO for HPC & AI at HPE, and former Cray CTO) was on-hand at the Rice Oil & Gas HPC conference in Houston. He was there to discuss the HPE-Cray transition and blended roadmap, as well as his favorite topic, Cray's eighth-gen networking technology, Slingshot. Read more…

By Tiffany Trader

Honeywell’s Big Bet on Trapped Ion Quantum Computing

April 7, 2020

Honeywell doesn’t spring to mind when thinking of quantum computing pioneers, but a decade ago the high-tech conglomerate better known for its control systems waded deliberately into the then calmer quantum computing (QC) waters. Fast forward to March when Honeywell announced plans to introduce an ion trap-based quantum computer whose ‘performance’ would... Read more…

By John Russell

Leading Solution Providers

SC 2019 Virtual Booth Video Tour

AMD
AMD
ASROCK RACK
ASROCK RACK
AWS
AWS
CEJN
CJEN
CRAY
CRAY
DDN
DDN
DELL EMC
DELL EMC
IBM
IBM
MELLANOX
MELLANOX
ONE STOP SYSTEMS
ONE STOP SYSTEMS
PANASAS
PANASAS
SIX NINES IT
SIX NINES IT
VERNE GLOBAL
VERNE GLOBAL
WEKAIO
WEKAIO

Contributors

Tech Conferences Are Being Canceled Due to Coronavirus

March 3, 2020

Several conferences scheduled to take place in the coming weeks, including Nvidia’s GPU Technology Conference (GTC) and the Strata Data + AI conference, have Read more…

By Alex Woodie

Exascale Watch: El Capitan Will Use AMD CPUs & GPUs to Reach 2 Exaflops

March 4, 2020

HPE and its collaborators reported today that El Capitan, the forthcoming exascale supercomputer to be sited at Lawrence Livermore National Laboratory and serve Read more…

By John Russell

‘Billion Molecules Against COVID-19’ Challenge to Launch with Massive Supercomputing Support

April 22, 2020

Around the world, supercomputing centers have spun up and opened their doors for COVID-19 research in what may be the most unified supercomputing effort in hist Read more…

By Oliver Peckham

Cray to Provide NOAA with Two AMD-Powered Supercomputers

February 24, 2020

The United States’ National Oceanic and Atmospheric Administration (NOAA) last week announced plans for a major refresh of its operational weather forecasting supercomputers, part of a 10-year, $505.2 million program, which will secure two HPE-Cray systems for NOAA’s National Weather Service to be fielded later this year and put into production in early 2022. Read more…

By Tiffany Trader

15 Slides on Programming Aurora and Exascale Systems

May 7, 2020

Sometime in 2021, Aurora, the first planned U.S. exascale system, is scheduled to be fired up at Argonne National Laboratory. Cray (now HPE) and Intel are the k Read more…

By John Russell

Australian Researchers Break All-Time Internet Speed Record

May 26, 2020

If you’ve been stuck at home for the last few months, you’ve probably become more attuned to the quality (or lack thereof) of your internet connection. Even Read more…

By Oliver Peckham

Summit Supercomputer is Already Making its Mark on Science

September 20, 2018

Summit, now the fastest supercomputer in the world, is quickly making its mark in science – five of the six finalists just announced for the prestigious 2018 Read more…

By John Russell

Nvidia’s Ampere A100 GPU: Up to 2.5X the HPC, 20X the AI

May 14, 2020

Nvidia's first Ampere-based graphics card, the A100 GPU, packs a whopping 54 billion transistors on 826mm2 of silicon, making it the world's largest seven-nanom Read more…

By Tiffany Trader

  • arrow
  • Click Here for More Headlines
  • arrow
Do NOT follow this link or you will be banned from the site!
Share This