Here’s a collection of highlights, selected totally subjectively, from this week’s HPC news stream as reported at insideHPC.com and HPCwire.

>>10 words and a link

NCAR fires up a new 2048 core Blue Gene/L;
http://insidehpc.com/2007/08/12/ncar-fires-up-blue-genel/

AMD cranks up the clock on select dual core chips;
http://insidehpc.com/2007/08/13/amd-cranking-the-clock-on-dual-cores/

AMD creates entire website devoted to Intel’s evils;
http://insidehpc.com/2007/08/12/amd-ups-the-icky-ante/

Intel launches 2 new quad-core Xeons;
http://insidehpc.com/2007/08/14/intel-launches-2-quad-core-xeons/

TACC starts new international academic supercomputing consortium;
http://insidehpc.com/2007/08/14/tacc-starts-academic-hpc-consortium/

Mercury launches new visualization subsidiary;
http://insidehpc.com/2007/08/14/mercury-launches-new-visualization-subsidiary/

>>DARPA HPCS Phase III to shed research funding

Recently, it has come to light that funding for productivity evaluation research under HPCS is going away after the end of Phase II. When asked for public comment from DARPA on this subject, DARPA spokesman Jan Walker responded that “Phase III is not a phase that requires as much research as past phases — it is focused on development and building of a prototype. However, if Phase III contractors IBM and Cray want to fund researchers they certainly can.”

The good news is that productivity evaluations on the HPCS systems will continue, but according to Walker “Some [of them] will be done by the vendors themselves. These evaluations will be a self-evaluation to make sure they are on track for productivity gains.”

A cynical person might observe that, since the Phase III vendors IBM and Cray will be allowed to evaluate themselves, it would be a big surprise if they failed to reach the productivity goals in the contract. But not us…we’re not cynical. No sir.

Read more of insideHPC.com reporter Mike McCracken’s DARPA interview at http://insidehpc.com/2007/08/13/darpa-hpcs-phase-3-to-shed-research-funding/.

>>AMD releases spec for enabling real time optimization of apps

AMD released its Light-Weight Profiling spec this week, the first step in its Hardware Extensions for Software Parallelism initiative. From AMD (http://www.amd.com/us-en/Corporate/VirtualPressRoom/0,,51_104_543~118952,00.html):

LWP is designed to enable code to make dynamic and real-time decisions about how best to improve the performance of concurrently running tasks, using techniques such as memory organization and code layout, with very little overhead. These capabilities are particularly beneficial to runtime environments like Java and .NET, which can run multiple threads and are used to develop an increasingly large percentage of applications.

This step is targeted at the runtime, and the company is talking about it specifically in terms of “managed” runtime evinronments as in the Java and .NET examples cited above. But this is an interesting development, and ties in to research directions in the complier community where developers are beginning to explore schemes for using run time information to prove conditions on loops the compilers doesn’t know enough about to parallelize at compile time in order to get the best performance.

According to AMD, the Hardware Extensions for Software Parallelism program

…will encompass a broad set of innovations designed to improve software parallelism, and thus application performance, through new hardware features in future versions of AMD processors.

>>Intel’s Penryn set for November debut

The DailyTech is reporting (http://www.dailytech.com/article.aspx?newsid=8451) that Intel has set a launch date for Penryn, the next of the Core 2 line that currently includes Woodcrest and Conroe. Penryn is a process shrink, this time down to 45nm (we’ve talked about Penryn before; here and here) and those hi-k gates all the kids are talking about.

Intel has set the launch date for its Penryn based quad-core Xeon processor family. The company intends to launch seven new Harpertown based models ranging from 2.0-to-3.16 GHz on November 11, according to a posting on Intel’s reseller webpage. Standard “E” bin and performance “X” bin processors launch on November 11.

Intel Xeon processors carrying the “E” designation feature 80-watt TDP ratings while the “X” bin processors have higher 120-watt TDP ratings. Intel does not plan to launch the low-power “L” models until Q1’08, with two models in the pipeline.

DailyTech found this info on a public page for Intel’s resellers; no formal announcement has been made, which is odd for a company with an itchy press release finger.

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