Beyond Multicore

By Michael Feldman

August 24, 2007

If you thought computing was just getting interesting with four cores, what happens when the chipmakers start delivering 100-core chips with multiple types of processing units? In this week’s issue, the High End Crusader (HEC) returns, delivering the first of a three part series about the future of parallel computing and heterogeneous processing. For those of you not familiar with HEC, he’s an HPC insider who has been a regular contributor to HPCwire. He remains anonymous so he can speak freely in this public forum. Anonymous or not, HEC always has an interesting take on which way the cutting-edge of computing is slicing.

In part one, HEC describes the current state of affairs of high-end computing and gives us a glimpse of the road ahead. In parts two and three he will argue that the community needs to reconceptualize both parallel computing and heterogeneous processing as we move toward what he refers to as “nanocore” — that is, the point at which processors exceed 64 cores. This is the level at which HEC believes “wholly innovative microarchitectural strategies are required to scale further.” The 64-core inflection point he’s referring to applies to general-purpose processor architecture, not simpler GPU or DSP architectures, which already have core counts at this scale and above.

While increased core count will make systems much more powerful, heterogeneity will make them more intelligent. In truth, heterogeneous computing has come to mean many things. Traditionally it refers to matching different types of processor architectures — scalar, vector, multithreaded, etc. — to the types of workloads that are most suited to them. So, for example, an application that needs to do matrix multiplication along with some non-arithmetic control logic might best be served with a system that encompassed both GPUs and CPUs. Other forms of heterogeneity involve the architecture of the memory hierarchy and the programming mechanisms that tie the various hardware models together.

On the multicore front, we’re already starting to see some early attempts at nanocore. This week Tilera announced TILE64, a 64-core chip aimed at the high performance embedded computing market. With an architecture that is reminiscent of Intel’s 80-core terascale processor prototype, TILE64 has an 8×8 grid of general-purpose processing cores (tiles) connected via an on-chip network, called iMesh. Tilera’s press release claims that it has achieved a scalable architecture significantly beyond current multicore processors:

Because the aggregate bandwidth is orders of magnitude greater than a bus and the distance between cores is shorter, the iMesh technology can be leveraged to create grids as large or small as an application requires, creating a “computing-by-the-yard” scalability…

By including a communication switch on each core, the processor is able to achieve 27 terabits per second of aggregate on-chip bandwidth. At 1 GHz and just 300 milliwatts per core, the whole (32-bit) processor can reach 192 gigaops. This is just a fraction of Intel’s one-plus teraflop of performance for their 80-core terascale prototype, but to some extent that’s comparing apples to oranges. However, both vendors do take advantage of a tiled arrangement of relatively simple processing cores connected by a 2D mesh to achieve much higher levels of performance than the current crop of commodity processors.

As core count gets into the triple digit range, the on-chip network performance becomes relatively more important than the performance of the individual computational units. The result will be that more silicon logic and power consumption will be devoted to the internal interconnect and off-chip memory access. HEC, in particular, points out that we we’re going to have to start paying a lot more attention to power consumption associated with the communication elements as these components start to dominate the system architecture.

For its part, Intel has stated its plans to bring the x86 ISA into HEC’s nanocore world, not just with high core counts, but with some elements of heterogeneous computing thrown in as well. Nehalem, the company’s next-generation microarchitecture will have a heterogeneous-friendly architecture that will be able to put GPU cores or perhaps other types of acceleration units on-chip. But Nehalem will probably top out at 8 cores.

Intel’s terascale effort, which should be commercially viable in the 2010 timeframe, represents the company’s intention to place hundreds of cores on the same processor die. At least some of these cores will be x86 compatible. But Intel has also talked about incorporating “special-purpose” computational engines for workloads like signal processing, graphics or network security. It’s likely that Intel’s contribution to the PSC/Carnegie Mellon NSF petascale Track 1 bid involved some form of this terascale chip.

Cray, as the extreme example of the high performance system vendor, is fully committed to move beyond multicore in both core count and heterogeneity. So far, it has only proposed loosely coupled heterogeneous systems that encompass scalar, vector, multithreading and FGPA processors. It is also actively working on the all-important system software that makes heterogeneous processing accessible to the application developer.

But unless the economic model for processor manufacturing gets turned on its head, system vendors will need to rely on the big chipmakers (e.g., Intel, IBM, AMD, NVIDIA, Sun Microsystems) to supply heterogeneity at the chip level. The expense of microprocessor R&D and the cost of fabs has created a rather exclusive club of chip manufacturers. Of the big chip vendors, only Intel and AMD have shown an inclination to pursue the heterogeneous path — not counting IBM and its Cell processor, which wasn’t really intended to be used for hosting disparate workloads.

While it’s unlikely that processor manufacturing will get turned on its head anytime soon, it’s possible that nanocore will turn it on its side. Imagine a semiconductor manufacturing technology that allowed system vendors to order customized processors from chip manufacturers. So, for example, an OEM who had a contract with an oil & gas company to provide systems for seismic simulations could specify a chip with, say, 80 GPUs and 20 CPUs. Maybe even user-designed cores could be included. While a customized processor is likely to be more expensive than a standard one, the value proposition seems pretty compelling when you’re talking about a 100-core chip.

That’s just one example of how the next wave of parallel processing and heterogeneous computing could radically alter the IT ecosystem. Certainly both software vendors and hardware manufacturers will be in for some big changes in the years ahead. Get ready for an interesting ride.

—–

As always, comments about HPCwire are welcomed and encouraged. Write to me, Michael Feldman, at [email protected].

Subscribe to HPCwire's Weekly Update!

Be the most informed person in the room! Stay ahead of the tech trends with industry updates delivered to you every week!

MLPerf Inference 4.0 Results Showcase GenAI; Nvidia Still Dominates

March 28, 2024

There were no startling surprises in the latest MLPerf Inference benchmark (4.0) results released yesterday. Two new workloads — Llama 2 and Stable Diffusion XL — were added to the benchmark suite as MLPerf continues Read more…

Q&A with Nvidia’s Chief of DGX Systems on the DGX-GB200 Rack-scale System

March 27, 2024

Pictures of Nvidia's new flagship mega-server, the DGX GB200, on the GTC show floor got favorable reactions on social media for the sheer amount of computing power it brings to artificial intelligence.  Nvidia's DGX Read more…

Call for Participation in Workshop on Potential NSF CISE Quantum Initiative

March 26, 2024

Editor’s Note: Next month there will be a workshop to discuss what a quantum initiative led by NSF’s Computer, Information Science and Engineering (CISE) directorate could entail. The details are posted below in a Ca Read more…

Waseda U. Researchers Reports New Quantum Algorithm for Speeding Optimization

March 25, 2024

Optimization problems cover a wide range of applications and are often cited as good candidates for quantum computing. However, the execution time for constrained combinatorial optimization applications on quantum device Read more…

NVLink: Faster Interconnects and Switches to Help Relieve Data Bottlenecks

March 25, 2024

Nvidia’s new Blackwell architecture may have stolen the show this week at the GPU Technology Conference in San Jose, California. But an emerging bottleneck at the network layer threatens to make bigger and brawnier pro Read more…

Who is David Blackwell?

March 22, 2024

During GTC24, co-founder and president of NVIDIA Jensen Huang unveiled the Blackwell GPU. This GPU itself is heavily optimized for AI work, boasting 192GB of HBM3E memory as well as the the ability to train 1 trillion pa Read more…

MLPerf Inference 4.0 Results Showcase GenAI; Nvidia Still Dominates

March 28, 2024

There were no startling surprises in the latest MLPerf Inference benchmark (4.0) results released yesterday. Two new workloads — Llama 2 and Stable Diffusion Read more…

Q&A with Nvidia’s Chief of DGX Systems on the DGX-GB200 Rack-scale System

March 27, 2024

Pictures of Nvidia's new flagship mega-server, the DGX GB200, on the GTC show floor got favorable reactions on social media for the sheer amount of computing po Read more…

NVLink: Faster Interconnects and Switches to Help Relieve Data Bottlenecks

March 25, 2024

Nvidia’s new Blackwell architecture may have stolen the show this week at the GPU Technology Conference in San Jose, California. But an emerging bottleneck at Read more…

Who is David Blackwell?

March 22, 2024

During GTC24, co-founder and president of NVIDIA Jensen Huang unveiled the Blackwell GPU. This GPU itself is heavily optimized for AI work, boasting 192GB of HB Read more…

Nvidia Looks to Accelerate GenAI Adoption with NIM

March 19, 2024

Today at the GPU Technology Conference, Nvidia launched a new offering aimed at helping customers quickly deploy their generative AI applications in a secure, s Read more…

The Generative AI Future Is Now, Nvidia’s Huang Says

March 19, 2024

We are in the early days of a transformative shift in how business gets done thanks to the advent of generative AI, according to Nvidia CEO and cofounder Jensen Read more…

Nvidia’s New Blackwell GPU Can Train AI Models with Trillions of Parameters

March 18, 2024

Nvidia's latest and fastest GPU, codenamed Blackwell, is here and will underpin the company's AI plans this year. The chip offers performance improvements from Read more…

Nvidia Showcases Quantum Cloud, Expanding Quantum Portfolio at GTC24

March 18, 2024

Nvidia’s barrage of quantum news at GTC24 this week includes new products, signature collaborations, and a new Nvidia Quantum Cloud for quantum developers. Wh Read more…

Alibaba Shuts Down its Quantum Computing Effort

November 30, 2023

In case you missed it, China’s e-commerce giant Alibaba has shut down its quantum computing research effort. It’s not entirely clear what drove the change. Read more…

Nvidia H100: Are 550,000 GPUs Enough for This Year?

August 17, 2023

The GPU Squeeze continues to place a premium on Nvidia H100 GPUs. In a recent Financial Times article, Nvidia reports that it expects to ship 550,000 of its lat Read more…

Shutterstock 1285747942

AMD’s Horsepower-packed MI300X GPU Beats Nvidia’s Upcoming H200

December 7, 2023

AMD and Nvidia are locked in an AI performance battle – much like the gaming GPU performance clash the companies have waged for decades. AMD has claimed it Read more…

DoD Takes a Long View of Quantum Computing

December 19, 2023

Given the large sums tied to expensive weapon systems – think $100-million-plus per F-35 fighter – it’s easy to forget the U.S. Department of Defense is a Read more…

Synopsys Eats Ansys: Does HPC Get Indigestion?

February 8, 2024

Recently, it was announced that Synopsys is buying HPC tool developer Ansys. Started in Pittsburgh, Pa., in 1970 as Swanson Analysis Systems, Inc. (SASI) by John Swanson (and eventually renamed), Ansys serves the CAE (Computer Aided Engineering)/multiphysics engineering simulation market. Read more…

Choosing the Right GPU for LLM Inference and Training

December 11, 2023

Accelerating the training and inference processes of deep learning models is crucial for unleashing their true potential and NVIDIA GPUs have emerged as a game- Read more…

Intel’s Server and PC Chip Development Will Blur After 2025

January 15, 2024

Intel's dealing with much more than chip rivals breathing down its neck; it is simultaneously integrating a bevy of new technologies such as chiplets, artificia Read more…

Baidu Exits Quantum, Closely Following Alibaba’s Earlier Move

January 5, 2024

Reuters reported this week that Baidu, China’s giant e-commerce and services provider, is exiting the quantum computing development arena. Reuters reported � Read more…

Leading Solution Providers

Contributors

Comparing NVIDIA A100 and NVIDIA L40S: Which GPU is Ideal for AI and Graphics-Intensive Workloads?

October 30, 2023

With long lead times for the NVIDIA H100 and A100 GPUs, many organizations are looking at the new NVIDIA L40S GPU, which it’s a new GPU optimized for AI and g Read more…

Shutterstock 1179408610

Google Addresses the Mysteries of Its Hypercomputer 

December 28, 2023

When Google launched its Hypercomputer earlier this month (December 2023), the first reaction was, "Say what?" It turns out that the Hypercomputer is Google's t Read more…

AMD MI3000A

How AMD May Get Across the CUDA Moat

October 5, 2023

When discussing GenAI, the term "GPU" almost always enters the conversation and the topic often moves toward performance and access. Interestingly, the word "GPU" is assumed to mean "Nvidia" products. (As an aside, the popular Nvidia hardware used in GenAI are not technically... Read more…

Shutterstock 1606064203

Meta’s Zuckerberg Puts Its AI Future in the Hands of 600,000 GPUs

January 25, 2024

In under two minutes, Meta's CEO, Mark Zuckerberg, laid out the company's AI plans, which included a plan to build an artificial intelligence system with the eq Read more…

Google Introduces ‘Hypercomputer’ to Its AI Infrastructure

December 11, 2023

Google ran out of monikers to describe its new AI system released on December 7. Supercomputer perhaps wasn't an apt description, so it settled on Hypercomputer Read more…

China Is All In on a RISC-V Future

January 8, 2024

The state of RISC-V in China was discussed in a recent report released by the Jamestown Foundation, a Washington, D.C.-based think tank. The report, entitled "E Read more…

Intel Won’t Have a Xeon Max Chip with New Emerald Rapids CPU

December 14, 2023

As expected, Intel officially announced its 5th generation Xeon server chips codenamed Emerald Rapids at an event in New York City, where the focus was really o Read more…

IBM Quantum Summit: Two New QPUs, Upgraded Qiskit, 10-year Roadmap and More

December 4, 2023

IBM kicks off its annual Quantum Summit today and will announce a broad range of advances including its much-anticipated 1121-qubit Condor QPU, a smaller 133-qu Read more…

  • arrow
  • Click Here for More Headlines
  • arrow
HPCwire