As the Chip Turns

By Michael Feldman

September 7, 2007

Will AMD find true happiness in Barcelona? Will Xeon break Opteron’s heart? What evil lurks beneath the Front Side Bus? If this sounds like the premise for some weird, high-tech soap opera, that’s because it is. The Intel-AMD feud has been going on for over 20 years and the participants show no signs of reconciliation. Since 1987, the two chipmakers have tangled each other in litigation, verbally attacked one another in public, and just expressed a genuine distaste for each other’s existence.

The level of animosity has ebbed and flowed over the years, but their tolerance for each other seems to be inversely proportional to one another’s success. As the September 10th coming-out party for AMD’s Barcelona processor approaches, industry watchers are being treated to almost daily episodes of Intel and AMD exchanging barbs.

As expected, this week Intel launched its new quad-core Xeon MP chips for multiprocessor servers. The Xeon 7300 series, code-named “Tigerton,” represents the last Intel product line to receive the new Core microarchitecture. The chips are targeted for high-end x86 servers that use four or more processors per box. Intel also delivered two dual-core Tigertons, the 2.93GHz E7220 and the 2.4GHz E7210. As I discussed last week, the Intel announcement seems to be timed to upstage AMD’s launch of its new Barcelona processors next Monday.

AMD immediately shot back with a public response to the Tigerton announcement, sent out to a number of media outlets, including HPCwire. Here’s an excerpt:

… Intel falls short yet again with “Tigerton” at the high-end of the x86 server industry.

The AMD Direct Connect Architecture, introduced in 2003, and the record-breaking scalability and energy-efficient performance it enables in AMD Opteron, has shown the industry that an integrated memory controller and high-speed direct connections between processor cores, memory, and I/O is the gold standard for x86 processor design. Intel will finally transition to its version of this architecture in late 2008 according to its public statements — five years after AMD introduced this x86 design. Thus, “Tigerton” has the unfortunate distinction of being near last in a line of a dying architecture based on a Front Side Bus bottleneck. Nowhere are the limitations of a Front Side Bus architecture more keenly felt than in the high-end Multi-Processor server market. So while Intel may publicly “celebrate” the arrival of Tigerton, it is in fact the final inadequate attempt by Intel to make the Front Side Bus architecture scale.

Tigerton is still a dual-core processor design, just as “Penryn” will be. Intel won’t offer a quad-core processor design until late 2008, more than a year after AMD. To achieve full performance scaling on real world multi-threaded workloads, real design work is needed. Packaging dual-cores together into quad-cores is insufficient, as clearly Intel itself understands. Why else transition to native quad-core in late 2008?

Multi-processor servers are memory intensive machines, which mean more DIMMs of memory. And while AMD continues to utilize DDR2 memory technology, Intel relies on FB-DIMM memory, which consume an average of 4-6 watts more power per memory DIMM. Independent reviewers like Neal Nelson, AnandTech and InfoWorld all show AMD with a significant advantage in energy efficiency.

This scales proportionately to the number of processors and attending increase in memory modules With a rating of 130 Watts typical for each processor, plus the FBDIMM and memory controller power penalties, power consumption and thermals go up dramatically from Intel dual core processors with Tigerton; this is not the direction customers want to head. AMD “Barcelona” offers the same power/thermals as our current dual-core processors.

There is no clean upgrade path for existing Intel “Tulsa” MP systems, meaning customers continue to face greater disruption and complexity from Intel processor roadmaps. And additional platform disruption looms ahead for 2008 as Intel finally scraps the Front Side Bus.

Virtualization is perhaps the world’s most memory-intensive application, meaning the Front Side Bus bottleneck is a liability. And because virtualization loves memory, any “Tigerton” based system will be loaded with power-hungry FB DIMMs. “Tigerton” for virtualization means more money to power, more money to cool, with a memory bottleneck.

The level of rhetoric reflects the stakes for AMD. The success of its new quad-core products are central to the company’s ability to become profitable once again and regain lost market share. And it’s important that AMD do so this year, since in 2008 Intel will introduce the Common System Interface (CSI) — Intel’s answer to HyperTransport. As I suggested last week, CSI will be the real challenge for AMD in 2008 and 2009. Until then, the company will need to string together some strong quarters of financial growth so that it can invest in new technology to be used to differentiate their products in the years ahead.

What may not be so intuitive is the importance of AMD’s success to the wider industry. Not only has AMD served as a counterweight to Intel’s dominance, but it has also spurred true innovation in x86 technology. Prior to the invention of 64-bit x86 computing in 2003 by AMD, Intel was content to focus its 64-bit efforts on the Itanium. As a response to the success of the 64-bit Opteron and Athlon, Intel was forced to follow its rival’s lead and develop its own 64-bit x86 architecture. Without AMD, a 64-bit version of x86 might never have happened. I’ll leave it to the reader to decide if this was a leap forward or not.

AMD went on to develop a new system architecture around the x86 core, adding HyperTransport as a high performance system interconnect and integrated memory controllers to improve system performance. Playing catch-up, Intel redesigned the microarchitecture, which debuted in 2006 under the Core moniker, and is in the process of redesigning the system architecture with CSI. The competition also compelled Intel to establish an aggressive “tick-tock” cycle for its x86 products: shrinking the process technology one year, followed by a new microarchitecture design the following year. Neither the Itanium nor other Intel chips are on such a fast-paced development schedule. It’s difficult to imagine the server landscape today without multicore 64-bit x86 processors, especially in the high performance computing space.

It should be no surprise that when multiple companies have access to the same processor architecture, customers have better choices and the processor ecosystem expands for everyone. This has certainly happened for x86 users. Other examples are PowerPC and MIPS. Both architectures are licensed across a variety of vendors and this has resulted in two of the most widely used processor families today. It’s doubtful this would have occurred if those two architectures were each being productized by a single vendor. Along those lines, Sun Microsystems has created an open source hardware project for its multicore UltraSPARC T1 and T2 processors in an effort to rapidly expand the ecosystem around those architectures.

For companies like Intel and AMD, whose chips go head-to-head against each other, they must find a way to advance their products at the expense of their competitor. As a result, Intel and AMD are relatively more concerned about expanding market share than they are about expanding the market. Companies like Sun and IBM, who combine chipmaking with servermaking, are more motivated to stimulate the ecosystem around their processor architectures since these companies sell unique, high-value systems and services based on those architectures. In that respect, the AMD-Intel relationship is unique and creates the special conditions for the kind of knock-down-drag-out fight that we’ve become accustomed to.

—–

As always, comments about HPCwire are welcomed and encouraged. Write to me, Michael Feldman, at [email protected].

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