High Performance 3D Image Reconstruction Platforms

By Nicole Hemsoth

October 26, 2007

by Prof. Dr. Marc Kachelrieß, Professor for Medical Imaging, Institute of Medical Physics (IMP), University of Erlangen-Nuremberg, Germany and Olivier Bockenbach, Systems Engineer, Mercury Computer Systems, Berlin, Germany

High-resolution tomographic scanners and other 3D technologies provide a number of compelling advantages for diagnostic medical imaging. However, 3D modalities such as Computed Tomography (CT) and Magnetic Resonance Imaging (MRI) are creating ever larger volumes of data, increasing the need for faster and bigger servers, higher network bandwidth, workstations with large memory and fast graphics, as well as advanced diagnostic software.

Advanced 3D Multi-Slice CT scanners generate up to more than 2000 projections per second, thus increasing the need for high-performance platforms that allow for the reconstruction and processing of medical imaging data nearly in real-time. High-performance systems, such as those based on the Cell Broadband Engine processor technology, allow for the implementation of advanced analytical and statistical CT reconstruction algorithms (and more specifically backprojection algorithms), thus enhancing image quality while keeping the X-Ray exposure of the patient as low as possible.


Tomographic image reconstruction is computationally very demanding. In all cases the backprojection represents the performance bottleneck due to the high operational count and due to the high demand placed on the memory subsystem. In the past, solving this problem has led to the use of digital signal processors and the implementation of specific architectures, connecting Application Specific Integrated Circuits (ASICs) or Field Programmable Gate Arrays (FPGAs) to the memory through dedicated high-speed busses. More recently, attempts have also been made to use Graphic Processing Units (GPUs) and the Cell processor.

However much these architectures differ, they all share common properties that make them attractive for the implementation of backprojection algorithms: the relative balance of high memory bandwidth and processing capabilities. On the other hand, harnessing the power of such devices necessarily also involves decision making with regard to the computational precision, the handling of the signal dynamics and the allowed approximations one can consider for making efficient use of the processing power of these devices.

Once a valid solution for the implementation of a 3D backprojection algorithm has been found for the device under consideration, there are major tasks to be addressed before the algorithm-device pair can be successfully deployed in a medical Image Reconstruction System (IRS).

The backprojection is a considerable processing step, but a 3D image reconstruction algorithm also includes pre-processing, filtering and post-processing steps. Various devices considered for accelerating the backprojection reveal themselves to be more or less usable for other tasks, requiring more or less assistance from other co-processing units. The implementation of the complete reconstruction pipeline may require the combination of several different devices, influencing the design, implementation and maintenance costs. However broad the spectrum of possible solutions may be, clinical and hospital operating conditions place another constraint on the IRS. These requirements are mainly directed towards processing speed, in order to match the hospital workflow. Nevertheless, the operating environment also includes processing density, as well as power and cooling requirements. The expected level of availability also places another constraint on the IRS.

Finally, more and more attention is being paid to the costs of the IRS, not only during the design but also over the complete life cycle of the IRS. Hence, there are multiple aspects that need to be taken into consideration, such as the life cycle of the underlying technology, the rate at which new devices are introduced and the end of life, together with the level of compatibility that is offered among devices from the same vendor or product family.

Hardware platforms

The aim of this investigation is to implement a 3D cone-beam perspective backprojection algorithm for the Cell processor and to benchmark its performance against other alternatives, such as PC-, FPGA- or GPU-based implementations. Four different platforms were selected:

  • the reference platform for image quality is on a standard PC with a single Xeon processor clocked at 3.06 GHz and a front bus side with 533 MHz
  • the PCI Express Cell Accelerator Board from Mercury Computer Systems
  • the PCI VantageRT-FCN board from Mercury Computer Systems
  • the G70 GPU from NVIDIA.

Implementation principles

The reconstruction of the volume can be implemented in many different ways. For instance, one could choose processing of the voxels following x, y or z as the primary processing axis. The z direction offers the most interesting properties in terms of optimization of processing and was therefore chosen as the primary processing axis. Similarly, processing the projections to reconstruct the global volume makes best use of the hardware resources (e.g. registers for processors, BlockRAM for FPGAs) when it is carried out on sub-volumes of regular shape, such as the cube. For the above mentioned reasons, the overall reconstruction method is based on the division of the volume to be reconstructed into slabs, each slab being processed as a small cube.

The complete reconstruction of a slab requires all projections. However, each slab does not require complete full-sized projections. The surface needed to reconstruct a slab is contained in a rectangular shape. When the side of the reconstruction volume is parallel to the detector plane, the projection of the slab of these slices is a rectangle. At other projection angles, the projection of the slab is a hexagon. The height of the hexagon is greatest when the diagonal of the slices is perpendicular to the detector plane. The height of the hexagon is also greatest at the top and bottom of the reconstruction volume. The software has been designed to take advantage of these properties for the reconstruction of the complete volume.

Rectification-based or hybrid methods are in use to speed up the backprojection process [1]. These have demonstrated significant performance gains over direct methods. The advantage consists in utilizing the re-sampling and bilinear interpolation of the projection data to realign to an ideal detector geometry, in order to use only a nearest neighbor approach during the backprojection and thus save a significant number of cycles per point.

PC reference platform

The PC-based code implementation is of the hybrid type in regard to first performing a detector alignment, based on up-sampling and bilinear interpolation, followed by a voxel-driven backprojection based on a nearest neighbor interpolation. The proposed platform is capable of backprojecting 512 projections onto a 512^3 volume in 3.21 minutes.

FPGA platform

A complete description of the first implementation can be found in [3]. This platform performs the reconstruction in fixed point mathematics and is capable of backprojecting 512 projections onto a 512^3 volume in about 25 seconds.

GPU platform

Graphical image processing requires extraordinary data re-sampling capabilities. Therefore, most modern GPUs assist the processing elements with specialized circuitry for performing interpolations. It thus makes little sense to attempt to accelerate the backprojection through the use of hybrid methods. This platform performs the reconstruction in floating point mathematics and can backproject 512 projections onto a 512^3 volume in about 37 seconds [4].

Cell platform

Implementing a Feldkamp backprojection on the Cell processor consists in distributing the tasks between the processing elements of the processor [2]. Using the PPE as a manager of the reconstruction process while the SPEs are dedicated to performing the real reconstruction task is the approach that was selected for this investigation. This platform is capable of backprojecting 512 projections onto a 512^3 volume in about 17 seconds.

Image quality

The different implementations were tested using the same data set and the reconstructed clinical quality volumes obtained for each of these. For this investigation, a mouse scanned with a TomoScope 30s micro-CT scanner (VAMP GmbH, Erlangen, Germany) was used.

All implementations give images of clinical quality. However, slight differences were observed between the different reconstructed volumes. The deviations from the reference results have different origins.

FPGA implementations suffer from the lack of floating point support. In traditional implementations on earlier FPGAs, all of the computation has to use a fixed point representation with the inherent limit imposed by the width of the multipliers; 18 bits for the Virtex-2 Pro. Attempts for using floating point on FPGAs [5] have given interesting results, but the required accuracy has still to be demonstrated for the backprojection.

However close this may be to IEEE standards, the floating point processing on an NVIDIA GPU still shows some deviations with respect to the standard. The effect on the reconstruction results takes the form of incorrect handling of exceptional cases, such as Not A Number (NaN).

The Cell implementation suffers to a certain extent from inaccuracies related to the computations of estimates instead of real values for operators such as divide, square root and exponential. The estimates turn out to be accurate, up to the 6th digit after the floating point. However small the difference with exact results may be, the end effect is seen in the reconstructed volume.

However, image quality takes on a different meaning when it is evaluated in connection with reconstruction speed. For example, it takes approximately the same time for a Cell processor to reconstruct a 1024^3 volume as for a PC to reconstruct a 512^3 volume. Provided that the detector allows for this increased resolution, high performance can offer better resolution of the volume and in any case better image quality.


The Cell processor offers the best performance when compared with all other designed architectures. The Cell processor and the GPU we have selected are among the most recent technologies available on the market. The Virtex-II is not among the most recent FPGA packages, and the PC reference platform has more powerful successors with the dual-core and quad-core processors.

The newest Virtex-4 and Virtex-5 versions can run at clock speeds of around 500MHz, almost five times faster than the version we have investigated. Furthermore, Xilinx proposes designs to implement DDR-2 interfaces on the Virtex-4 and Virtex-5 chips, thus giving the same increase of 5x in performance for the memory subsystem. Without considering the improvements in the current state of the newest FPGAs, an increase in the performance factor of 5x is the absolute minimum to be expected.

The improvement in performance obtained with the newest dual-core and quad-core architectures is more difficult to estimate. The way in which the I/O and memory access resources are shared and distributed depends on the design of the processor. Nevertheless, with even the best case of a 4x performance improvement, a quad-core system does not come close to the performance of a Cell processor or a GPU, not to mention the newest FPGAs, considering that the reconstruction a standard quad-core system is at least three times slower than a Cell processor and 6 times slower than a modern GPU.

Software complexity

As pointed out in the software implementation section of this article, the most obvious and stable implementation has been realized using a PC. The Cell processor offers a multi-computing platform which is altogether comparable to multi-computers, such as those developed by Mercury Computer Systems with RACEWay, RACE++ and RapidIO. Even though all GPU boards support OpenGL and DirectX, the level of efficiency for different GPU boards varies considerably, even when these are from the same manufacturer. The result is that performance is not predictable across GPU board generations. The implementation section also shows that the coding of reconstruction algorithms is very much more difficult on FPGAs, mainly because these do not offer floating point operators and operators such as multiply, divide, sine and cosine. These functions must be coded as application-dependent Look-up Tables (LUTs).

System integration

The GPUs are intended as the graphical processor companion in every PC. Therefore, most modern PCs can accommodate the presence of a modern GPU, with respect to power supply and cooling. Consequently, all reconstruction hardware that fits in the same (cooling, power supply) envelope can be hosted in the same host PC. The Cell Accelerator Board – a high performance accelerator card based on the Cell BE processor – has been designed to fit into this envelope and can be hosted in any modern PC. FPGA-based boards are subject to the concept of the designer. FPGAs traditionally draw less power than high-clocked devices, such as a GPU or the Cell processor, and are in any case easier to cool.


All basic building blocks, i.e., GPU, FPGA and the Cell processor, are available and can deliver the appropriate image quality, however with varying degrees of effort. Depending on the evaluation criteria, the optimal choice between FPGAs, GPUs, multi-core based PCs and the Cell processor may differ. However, the Cell processor offers a fully programmable architecture, accessible from high-level programming languages such as C. Its application in the gaming industry suggests long-term availability of the parts for realistic field deployment and maintenance also in hospitals.


[1] Riddell, Cyril and Trousset, Yves, Rectification for Cone–Beam Projection and Backprojection, IEEE Transactions on Medical Imaging 25(7): 950-962, July 2006

[2] H.P. Hofstee. Power efficient processor architecture and the Cell processor. Proceedings of the 11th International Symposium on High-performance Computer Architecture, Feb. 2005

[3] I. Goddard, M. Trepanier. High Speed cone-beam reconstruction: an embedded system approach. SPIE Medical Imaging Proc., 4681:483-491, 2002.

[4] K. Müller, F. Xu. Accelerating popular tomographic reconstruction algorithms on commodity PC graphics hardware. IEEE Transactions on Nuclear Science, (3):654-663, 2005.

[5] R. Andraka, F. Xu. Hybrid Floating Techniques Yields 1.2 Gigasample Per Second 32 to 2048 point Floating Point FFT in a single FPGA. HPEC Proceedings, 2006.

Subscribe to HPCwire's Weekly Update!

Be the most informed person in the room! Stay ahead of the tech trends with industy updates delivered to you every week!

Researchers Scale COSMO Climate Code to 4888 GPUs on Piz Daint

October 17, 2017

Effective global climate simulation, sorely needed to anticipate and cope with global warming, has long been computationally challenging. Two of the major obstacles are the needed resolution and prolonged time to compute Read more…

By John Russell

Student Cluster Competition Coverage New Home

October 16, 2017

Hello computer sports fans! This is the first of many (many!) articles covering the world-wide phenomenon of Student Cluster Competitions. Finally, the Student Cluster Competition coverage has come to its natural home: H Read more…

By Dan Olds

UCSD Web-based Tool Tracking CA Wildfires Generates 1.5M Views

October 16, 2017

Tracking the wildfires raging in northern CA is an unpleasant but necessary part of guiding efforts to fight the fires and safely evacuate affected residents. One such tool – Firemap – is a web-based tool developed b Read more…

By John Russell

HPE Extreme Performance Solutions

Transforming Genomic Analytics with HPC-Accelerated Insights

Advancements in the field of genomics are revolutionizing our understanding of human biology, rapidly accelerating the discovery and treatment of genetic diseases, and dramatically improving human health. Read more…

Exascale Imperative: New Movie from HPE Makes a Compelling Case

October 13, 2017

Why is pursuing exascale computing so important? In a new video – Hewlett Packard Enterprise: Eighteen Zeros – four HPE executives, a prominent national lab HPC researcher, and HPCwire managing editor Tiffany Trader Read more…

By John Russell

Student Cluster Competition Coverage New Home

October 16, 2017

Hello computer sports fans! This is the first of many (many!) articles covering the world-wide phenomenon of Student Cluster Competitions. Finally, the Student Read more…

By Dan Olds

Intel Delivers 17-Qubit Quantum Chip to European Research Partner

October 10, 2017

On Tuesday, Intel delivered a 17-qubit superconducting test chip to research partner QuTech, the quantum research institute of Delft University of Technology (TU Delft) in the Netherlands. The announcement marks a major milestone in the 10-year, $50-million collaborative relationship with TU Delft and TNO, the Dutch Organization for Applied Research, to accelerate advancements in quantum computing. Read more…

By Tiffany Trader

Fujitsu Tapped to Build 37-Petaflops ABCI System for AIST

October 10, 2017

Fujitsu announced today it will build the long-planned AI Bridging Cloud Infrastructure (ABCI) which is set to become the fastest supercomputer system in Japan Read more…

By John Russell

HPC Chips – A Veritable Smorgasbord?

October 10, 2017

For the first time since AMD's ill-fated launch of Bulldozer the answer to the question, 'Which CPU will be in my next HPC system?' doesn't have to be 'Whichever variety of Intel Xeon E5 they are selling when we procure'. Read more…

By Dairsie Latimer

Delays, Smoke, Records & Markets – A Candid Conversation with Cray CEO Peter Ungaro

October 5, 2017

Earlier this month, Tom Tabor, publisher of HPCwire and I had a very personal conversation with Cray CEO Peter Ungaro. Cray has been on something of a Cinderell Read more…

By Tiffany Trader & Tom Tabor

Intel Debuts Programmable Acceleration Card

October 5, 2017

With a view toward supporting complex, data-intensive applications, such as AI inference, video streaming analytics, database acceleration and genomics, Intel i Read more…

By Doug Black

OLCF’s 200 Petaflops Summit Machine Still Slated for 2018 Start-up

October 3, 2017

The Department of Energy’s planned 200 petaflops Summit computer, which is currently being installed at Oak Ridge Leadership Computing Facility, is on track t Read more…

By John Russell

US Exascale Program – Some Additional Clarity

September 28, 2017

The last time we left the Department of Energy’s exascale computing program in July, things were looking very positive. Both the U.S. House and Senate had pas Read more…

By Alex R. Larzelere

How ‘Knights Mill’ Gets Its Deep Learning Flops

June 22, 2017

Intel, the subject of much speculation regarding the delayed, rewritten or potentially canceled “Aurora” contract (the Argonne Lab part of the CORAL “ Read more…

By Tiffany Trader

Reinders: “AVX-512 May Be a Hidden Gem” in Intel Xeon Scalable Processors

June 29, 2017

Imagine if we could use vector processing on something other than just floating point problems.  Today, GPUs and CPUs work tirelessly to accelerate algorithms Read more…

By James Reinders

NERSC Scales Scientific Deep Learning to 15 Petaflops

August 28, 2017

A collaborative effort between Intel, NERSC and Stanford has delivered the first 15-petaflops deep learning software running on HPC platforms and is, according Read more…

By Rob Farber

Oracle Layoffs Reportedly Hit SPARC and Solaris Hard

September 7, 2017

Oracle’s latest layoffs have many wondering if this is the end of the line for the SPARC processor and Solaris OS development. As reported by multiple sources Read more…

By John Russell

US Coalesces Plans for First Exascale Supercomputer: Aurora in 2021

September 27, 2017

At the Advanced Scientific Computing Advisory Committee (ASCAC) meeting, in Arlington, Va., yesterday (Sept. 26), it was revealed that the "Aurora" supercompute Read more…

By Tiffany Trader

Google Releases Deeplearn.js to Further Democratize Machine Learning

August 17, 2017

Spreading the use of machine learning tools is one of the goals of Google’s PAIR (People + AI Research) initiative, which was introduced in early July. Last w Read more…

By John Russell

GlobalFoundries Puts Wind in AMD’s Sails with 12nm FinFET

September 24, 2017

From its annual tech conference last week (Sept. 20), where GlobalFoundries welcomed more than 600 semiconductor professionals (reaching the Santa Clara venue Read more…

By Tiffany Trader

Graphcore Readies Launch of 16nm Colossus-IPU Chip

July 20, 2017

A second $30 million funding round for U.K. AI chip developer Graphcore sets up the company to go to market with its “intelligent processing unit” (IPU) in Read more…

By Tiffany Trader

Leading Solution Providers

Amazon Debuts New AMD-based GPU Instances for Graphics Acceleration

September 12, 2017

Last week Amazon Web Services (AWS) streaming service, AppStream 2.0, introduced a new GPU instance called Graphics Design intended to accelerate graphics. The Read more…

By John Russell

Nvidia Responds to Google TPU Benchmarking

April 10, 2017

Nvidia highlights strengths of its newest GPU silicon in response to Google's report on the performance and energy advantages of its custom tensor processor. Read more…

By Tiffany Trader

EU Funds 20 Million Euro ARM+FPGA Exascale Project

September 7, 2017

At the Barcelona Supercomputer Centre on Wednesday (Sept. 6), 16 partners gathered to launch the EuroEXA project, which invests €20 million over three-and-a-half years into exascale-focused research and development. Led by the Horizon 2020 program, EuroEXA picks up the banner of a triad of partner projects — ExaNeSt, EcoScale and ExaNoDe — building on their work... Read more…

By Tiffany Trader

Delays, Smoke, Records & Markets – A Candid Conversation with Cray CEO Peter Ungaro

October 5, 2017

Earlier this month, Tom Tabor, publisher of HPCwire and I had a very personal conversation with Cray CEO Peter Ungaro. Cray has been on something of a Cinderell Read more…

By Tiffany Trader & Tom Tabor

Cray Moves to Acquire the Seagate ClusterStor Line

July 28, 2017

This week Cray announced that it is picking up Seagate's ClusterStor HPC storage array business for an undisclosed sum. "In short we're effectively transitioning the bulk of the ClusterStor product line to Cray," said CEO Peter Ungaro. Read more…

By Tiffany Trader

Intel Launches Software Tools to Ease FPGA Programming

September 5, 2017

Field Programmable Gate Arrays (FPGAs) have a reputation for being difficult to program, requiring expertise in specialty languages, like Verilog or VHDL. Easin Read more…

By Tiffany Trader

IBM Advances Web-based Quantum Programming

September 5, 2017

IBM Research is pairing its Jupyter-based Data Science Experience notebook environment with its cloud-based quantum computer, IBM Q, in hopes of encouraging a new class of entrepreneurial user to solve intractable problems that even exceed the capabilities of the best AI systems. Read more…

By Alex Woodie

Intel, NERSC and University Partners Launch New Big Data Center

August 17, 2017

A collaboration between the Department of Energy’s National Energy Research Scientific Computing Center (NERSC), Intel and five Intel Parallel Computing Cente Read more…

By Linda Barney

  • arrow
  • Click Here for More Headlines
  • arrow
Share This