by Prof. Dr. Marc Kachelrieß, Professor for Medical Imaging, Institute of Medical Physics (IMP), University of Erlangen-Nuremberg, Germany and Olivier Bockenbach, Systems Engineer, Mercury Computer Systems, Berlin, Germany
High-resolution tomographic scanners and other 3D technologies provide a number of compelling advantages for diagnostic medical imaging. However, 3D modalities such as Computed Tomography (CT) and Magnetic Resonance Imaging (MRI) are creating ever larger volumes of data, increasing the need for faster and bigger servers, higher network bandwidth, workstations with large memory and fast graphics, as well as advanced diagnostic software.
Advanced 3D Multi-Slice CT scanners generate up to more than 2000 projections per second, thus increasing the need for high-performance platforms that allow for the reconstruction and processing of medical imaging data nearly in real-time. High-performance systems, such as those based on the Cell Broadband Engine processor technology, allow for the implementation of advanced analytical and statistical CT reconstruction algorithms (and more specifically backprojection algorithms), thus enhancing image quality while keeping the X-Ray exposure of the patient as low as possible.
Tomographic image reconstruction is computationally very demanding. In all cases the backprojection represents the performance bottleneck due to the high operational count and due to the high demand placed on the memory subsystem. In the past, solving this problem has led to the use of digital signal processors and the implementation of specific architectures, connecting Application Specific Integrated Circuits (ASICs) or Field Programmable Gate Arrays (FPGAs) to the memory through dedicated high-speed busses. More recently, attempts have also been made to use Graphic Processing Units (GPUs) and the Cell processor.
However much these architectures differ, they all share common properties that make them attractive for the implementation of backprojection algorithms: the relative balance of high memory bandwidth and processing capabilities. On the other hand, harnessing the power of such devices necessarily also involves decision making with regard to the computational precision, the handling of the signal dynamics and the allowed approximations one can consider for making efficient use of the processing power of these devices.
Once a valid solution for the implementation of a 3D backprojection algorithm has been found for the device under consideration, there are major tasks to be addressed before the algorithm-device pair can be successfully deployed in a medical Image Reconstruction System (IRS).
The backprojection is a considerable processing step, but a 3D image reconstruction algorithm also includes pre-processing, filtering and post-processing steps. Various devices considered for accelerating the backprojection reveal themselves to be more or less usable for other tasks, requiring more or less assistance from other co-processing units. The implementation of the complete reconstruction pipeline may require the combination of several different devices, influencing the design, implementation and maintenance costs. However broad the spectrum of possible solutions may be, clinical and hospital operating conditions place another constraint on the IRS. These requirements are mainly directed towards processing speed, in order to match the hospital workflow. Nevertheless, the operating environment also includes processing density, as well as power and cooling requirements. The expected level of availability also places another constraint on the IRS.
Finally, more and more attention is being paid to the costs of the IRS, not only during the design but also over the complete life cycle of the IRS. Hence, there are multiple aspects that need to be taken into consideration, such as the life cycle of the underlying technology, the rate at which new devices are introduced and the end of life, together with the level of compatibility that is offered among devices from the same vendor or product family.
The aim of this investigation is to implement a 3D cone-beam perspective backprojection algorithm for the Cell processor and to benchmark its performance against other alternatives, such as PC-, FPGA- or GPU-based implementations. Four different platforms were selected:
- the reference platform for image quality is on a standard PC with a single Xeon processor clocked at 3.06 GHz and a front bus side with 533 MHz
- the PCI Express Cell Accelerator Board from Mercury Computer Systems
- the PCI VantageRT-FCN board from Mercury Computer Systems
- the G70 GPU from NVIDIA.
The reconstruction of the volume can be implemented in many different ways. For instance, one could choose processing of the voxels following x, y or z as the primary processing axis. The z direction offers the most interesting properties in terms of optimization of processing and was therefore chosen as the primary processing axis. Similarly, processing the projections to reconstruct the global volume makes best use of the hardware resources (e.g. registers for processors, BlockRAM for FPGAs) when it is carried out on sub-volumes of regular shape, such as the cube. For the above mentioned reasons, the overall reconstruction method is based on the division of the volume to be reconstructed into slabs, each slab being processed as a small cube.
The complete reconstruction of a slab requires all projections. However, each slab does not require complete full-sized projections. The surface needed to reconstruct a slab is contained in a rectangular shape. When the side of the reconstruction volume is parallel to the detector plane, the projection of the slab of these slices is a rectangle. At other projection angles, the projection of the slab is a hexagon. The height of the hexagon is greatest when the diagonal of the slices is perpendicular to the detector plane. The height of the hexagon is also greatest at the top and bottom of the reconstruction volume. The software has been designed to take advantage of these properties for the reconstruction of the complete volume.
Rectification-based or hybrid methods are in use to speed up the backprojection process . These have demonstrated significant performance gains over direct methods. The advantage consists in utilizing the re-sampling and bilinear interpolation of the projection data to realign to an ideal detector geometry, in order to use only a nearest neighbor approach during the backprojection and thus save a significant number of cycles per point.
PC reference platform
The PC-based code implementation is of the hybrid type in regard to first performing a detector alignment, based on up-sampling and bilinear interpolation, followed by a voxel-driven backprojection based on a nearest neighbor interpolation. The proposed platform is capable of backprojecting 512 projections onto a 512^3 volume in 3.21 minutes.
A complete description of the first implementation can be found in . This platform performs the reconstruction in fixed point mathematics and is capable of backprojecting 512 projections onto a 512^3 volume in about 25 seconds.
Graphical image processing requires extraordinary data re-sampling capabilities. Therefore, most modern GPUs assist the processing elements with specialized circuitry for performing interpolations. It thus makes little sense to attempt to accelerate the backprojection through the use of hybrid methods. This platform performs the reconstruction in floating point mathematics and can backproject 512 projections onto a 512^3 volume in about 37 seconds .
Implementing a Feldkamp backprojection on the Cell processor consists in distributing the tasks between the processing elements of the processor . Using the PPE as a manager of the reconstruction process while the SPEs are dedicated to performing the real reconstruction task is the approach that was selected for this investigation. This platform is capable of backprojecting 512 projections onto a 512^3 volume in about 17 seconds.
The different implementations were tested using the same data set and the reconstructed clinical quality volumes obtained for each of these. For this investigation, a mouse scanned with a TomoScope 30s micro-CT scanner (VAMP GmbH, Erlangen, Germany) was used.
All implementations give images of clinical quality. However, slight differences were observed between the different reconstructed volumes. The deviations from the reference results have different origins.
FPGA implementations suffer from the lack of floating point support. In traditional implementations on earlier FPGAs, all of the computation has to use a fixed point representation with the inherent limit imposed by the width of the multipliers; 18 bits for the Virtex-2 Pro. Attempts for using floating point on FPGAs  have given interesting results, but the required accuracy has still to be demonstrated for the backprojection.
However close this may be to IEEE standards, the floating point processing on an NVIDIA GPU still shows some deviations with respect to the standard. The effect on the reconstruction results takes the form of incorrect handling of exceptional cases, such as Not A Number (NaN).
The Cell implementation suffers to a certain extent from inaccuracies related to the computations of estimates instead of real values for operators such as divide, square root and exponential. The estimates turn out to be accurate, up to the 6th digit after the floating point. However small the difference with exact results may be, the end effect is seen in the reconstructed volume.
However, image quality takes on a different meaning when it is evaluated in connection with reconstruction speed. For example, it takes approximately the same time for a Cell processor to reconstruct a 1024^3 volume as for a PC to reconstruct a 512^3 volume. Provided that the detector allows for this increased resolution, high performance can offer better resolution of the volume and in any case better image quality.
The Cell processor offers the best performance when compared with all other designed architectures. The Cell processor and the GPU we have selected are among the most recent technologies available on the market. The Virtex-II is not among the most recent FPGA packages, and the PC reference platform has more powerful successors with the dual-core and quad-core processors.
The newest Virtex-4 and Virtex-5 versions can run at clock speeds of around 500MHz, almost five times faster than the version we have investigated. Furthermore, Xilinx proposes designs to implement DDR-2 interfaces on the Virtex-4 and Virtex-5 chips, thus giving the same increase of 5x in performance for the memory subsystem. Without considering the improvements in the current state of the newest FPGAs, an increase in the performance factor of 5x is the absolute minimum to be expected.
The improvement in performance obtained with the newest dual-core and quad-core architectures is more difficult to estimate. The way in which the I/O and memory access resources are shared and distributed depends on the design of the processor. Nevertheless, with even the best case of a 4x performance improvement, a quad-core system does not come close to the performance of a Cell processor or a GPU, not to mention the newest FPGAs, considering that the reconstruction a standard quad-core system is at least three times slower than a Cell processor and 6 times slower than a modern GPU.
As pointed out in the software implementation section of this article, the most obvious and stable implementation has been realized using a PC. The Cell processor offers a multi-computing platform which is altogether comparable to multi-computers, such as those developed by Mercury Computer Systems with RACEWay, RACE++ and RapidIO. Even though all GPU boards support OpenGL and DirectX, the level of efficiency for different GPU boards varies considerably, even when these are from the same manufacturer. The result is that performance is not predictable across GPU board generations. The implementation section also shows that the coding of reconstruction algorithms is very much more difficult on FPGAs, mainly because these do not offer floating point operators and operators such as multiply, divide, sine and cosine. These functions must be coded as application-dependent Look-up Tables (LUTs).
The GPUs are intended as the graphical processor companion in every PC. Therefore, most modern PCs can accommodate the presence of a modern GPU, with respect to power supply and cooling. Consequently, all reconstruction hardware that fits in the same (cooling, power supply) envelope can be hosted in the same host PC. The Cell Accelerator Board – a high performance accelerator card based on the Cell BE processor – has been designed to fit into this envelope and can be hosted in any modern PC. FPGA-based boards are subject to the concept of the designer. FPGAs traditionally draw less power than high-clocked devices, such as a GPU or the Cell processor, and are in any case easier to cool.
All basic building blocks, i.e., GPU, FPGA and the Cell processor, are available and can deliver the appropriate image quality, however with varying degrees of effort. Depending on the evaluation criteria, the optimal choice between FPGAs, GPUs, multi-core based PCs and the Cell processor may differ. However, the Cell processor offers a fully programmable architecture, accessible from high-level programming languages such as C. Its application in the gaming industry suggests long-term availability of the parts for realistic field deployment and maintenance also in hospitals.
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