Compilers and More: Gloptimizations

By Michael Wolfe

November 9, 2007

In my last column, I discussed the performance improvements on one of the SPEC CPU2000 floating point benchmarks, 172.mgrid, between 1999 and 2006, and introduced an optimization (which we call Loop-Carried Redundancy Elimination) that improves mgrid significantly. The SPEC CPU committee has been quite careful with benchmarks that are sensitive to compiler tricks. The original SPEC ’89 benchmark suite included 030.matrix300 (dense matrix multiplication). Since matrix multiplication is one of a set of core operations performed in many numerical applications, it was considered a good candidate for a benchmark. But, to quote Reinhold Weicker from the SPEC Newsletter (December 1995): “However, if a program becomes a benchmark, compiler authors can become very creative.”

In this case, compilers were modified to aggressively tile the loops; in each tile, the program performs a sub-matrix multiplication where the submatrices fit into the cache memory, improving the total performance by up to a factor of eight. (The term “loop tiling” or “iteration space tiling” was actually suggested by my wife in 1986; I was looking for a better term to use in a paper, she was looking at the kitchen floor.) Since this one optimization had such a big impact, and didn’t apply to the other benchmarks, the SPEC committee decided that it was not a fair contributor to an overall performance metric, and matrix300 was retired in 1992.

I noted last time that Dell had published a SPEC CPU2000 run in November 1999 on a 733 MHz Pentium III Precision Workstation 420, and another in October 2006 on a 2.66 GHz Core 2 Extreme Precision Workstation 390. I chose to compare these two runs simply because they were from the same vendor seven years apart. The base CFP2000 proved from 242 to 2679, a factor of just over 11. The big winner was 179.art, which improved from a ratio of 313 to 9306, almost a factor of 30 speedup. What accounts for this factor of 30? Can we expect similar improvements for any other program?

One way to achieve great speedups is to make the base case really slow; then, even simple optimizations can deliver a nice improvement. Sometimes, the program is written in a way that seems intentionally aimed at making it run slowly. Such a case appears in ART.

The ART benchmark (Adaptive Resonance Theory neural network for image ecognition) is written in C, and the critical loop is:

    struct{
double *I; double W, X, V, U, P, Q, R;
} * f1_layer;
double **bus;
....
for( tj = 0; tj < numf2s; tj++ ){
Y[tj].y = 0;
if( !Y[tj].reset )
for( ti = 0; ti < numf1s; ti++ )
Y[tj].y += f1_layer[ti].P * bus[ti][tj];
}

This loop appears in several places in the program, and much of the time of the program is spent in it; speed up this loop and the program runs fast.

However, there are several problems here. The struct f1_layer has 8 members, each 8 bytes long (assuming 64-bit pointers). That means each element of f1_layer takes up a whole 64-byte cache line. So while we’re traversing the array f1_layer in the inner loop, we only use one value out of each cache line. Even worse, the two-dimensional array bus is dynamically allocated, and we are traversing down the columns; that means two memory accesses (to get the row pointer bus[ti], then the value bus[ti][tj]). In both cases, the program abuses memory bandwidth in the inner loop, unless the whole dataset fits in the cache.

A few more comments: it turns out the inner loop has a trip count of about 10,000, while the outer loop has only 6 iterations, and the conditional around the inner loop never trips (reset is always 0), at least not in the benchmark datasets, so the inner loop is always executed. These facts are known only at runtime, however.

I’ve seen three ways to make this loop run much faster.  Some compilers implement what has been called the ART hack, reorganizing the data for the struct f1_layer. The array-of-struct is reorganized to become a struct of arrays. It takes the same amount of space, but now each element f1_layer[ti].P become f1_layer.P[ti], so consecutive elements are adjacent in the cache, and the performance of the cache and the whole program improves greatly.

    struct{
double **I; double *W, *X, *V, *U, *P, *Q, *R;
} f1_layer;
double **bus;
....
for( tj = 0; tj < numf2s; tj++ ){
Y[tj].y = 0;
if( !Y[tj].reset )
for( ti = 0; ti < numf1s; ti++ )
Y[tj].y += f1_layer.P[ti] * bus[ti][tj];
}

I did this by hand on an older Intel 3.4GHz EM64T Xeon, using the PGI compilers, and measured a 49% performance improvement. You can imagine what kind of whole program analysis would allow or disallow this reorganization, and it is very rarely feasible. However, this benchmark is so important that some compilers take this step. Here’s an optimization (to abuse the term) that would never have been invented if not for this particular benchmark.

A different trick is to interchange the two loops. The problem being solved is the accesses to the array bus, which are non-adjacent, have no locality, and require two loads per iteration, problems which go away if the two loops are interchanged. However, after interchanging, the new inner loop has a very short trip count (though the compiler probably doesn’t know that). The other more serious problem is that interchanging the loops brings the conditional inside both loops.

    struct{
double *I; double W, X, V, U, P, Q, R;
} * f1_layer;
double **bus;
....
for( tj = 0; tj < numf2s; tj++ )
Y[tj].y = 0;
for( ti = 0; ti < numf1s; ti++ ){
for( tj = 0; tj < numf2s; tj++ )
if( !Y[tj].reset )
Y[tj].y += f1_layer[ti].P * bus[ti][tj];
}

On the same Xeon, I measured a speedup of 2.33. However, this is quite dangerous, from a performance standpoint; instead of ‘numf2s’ conditional tests, there are now ‘numf1s*numf2s’ tests. If the test tripped at all, the modified version could execute quite a bit slower than the original. Yet, at least one compiler implements this and gets more than a factor of two improvement in the whole program, mostly due to this loop transformation.

The third trick, not implemented by any compiler (yet, that I know of), is to leave the loops the way they are and to transpose the array bus (and a similarly accessed array, tds). It turns out these arrays are dynamically allocated, but accessed in the wrong dimension. If we transpose the dimensions, the performance of this loop and the whole program really screams. On that same Xeon, I measured a speedup of 4.3.

This last is somewhat harder to implement automatically. The most severe problem is that C doesn’t really have two-dimensional arrays; to get a two-dimensional dynamic array, the program has to first allocate a one-dimensional vector of pointers. To transpose an array, the program has to allocate a vector of a different size. Purists argue that the modified program might allocate more space, and hence might run out of memory for some large datasets.

Moreover, the performance improvements are not very stable. The speedups I measured on the EM64T were 1.49 for array-of-struct reorganization, 2.3 for loop interchange, and 4.3 for for array transposition. Last month, I compared performance using an older 733MHz Intel Pentium III and a 2.66GHz Intel Core 2 Extreme. The speedups for these three optimizations on these two machines (and the EM64T) are summarized here:

       EM64T   PIII      Core2
        1.49       1.64      1.08    array-of-struct reorganization
        2.33       1.00      1.03    loop interchange
        4.34       1.19      1.48    array transpose

I am guessing that these optimizations have much less effect on the latest Core 2 because the data all fits in the much larger cache.

So, last month I discussed compiler tuning for 172.mgrid, where a new optimization improved its performance about 20%; happily, we’ve found this new feature applies in many other user applications as well. This month, I presented compiler tuning for 179.art, where aggressive optimization can improve the performance by factors (on some machines). I won’t go into the hacks, tricks, and other tuning for the other SPEC CPU2000 benchmarks; the number of compiler tricks is linearly related to the number of benchmarks.

With the increased importance of benchmark performance, compiler development teams are encouraged to aggressive (or even heroic) efforts to optimize performance on these programs. The only reason they do so is that vendors and users (and compiler product managers) place artificial importance on certain benchmark results. Yet, these optimizations, while impressive, may be of little value, or no value, or even negative value among the more general user domain, or even on the same program with different inputs. As shown here for ART, the value of the optimization may decrease to essentially zero as the architecture progresses.

Therefore, in the spirit of the Golden Raspberry award (http://www.razzies.com/) and the Ig Nobel Prizes (http://www.improbable.com/ig), I propose that we honor the most outrageous, benchmark-specific optimization with an award of its own, the Gloptimization award, or Gloppy for short. The award itself would be a pile of glop (or representation thereof), defined in my American Heritage Dictionary as “n. 1. A messy mixture, as of food. 2. Something, as writing, that is worthless. v. 1. To cover with glop. 2. To put glop on.” The award, at least, is appropriate. More credit should be given to an optimization that applies to a single benchmark; extra credit if it measureably slows down other benchmarks or applications. Posthumous awards can be proposed for optimizations that are actually removed from compilers as the targeted benchmarks are themselves retired. The optimizations mentioned above would certainly be candidates for a Gloppy, though perhaps not winners.

The lesson for customers is that standard benchmarks are valuable tools, but should not be the only or primary means of comparing system performance. The best measure is always the performance of your own applications, to which the systems and accompanying software are not specifically tuned.

SPEC (R) is a registered trademark of the Standard Performance Evaluation Corporation (http://www.spec.org/).

—–

Michael Wolfe has developed compilers for over 30 years in both academia and industry, and is now a senior compiler engineer at The Portland Group, Inc. (www.pgroup.com), a wholly-owned subsidiary of STMicroelectronics, Inc. The opinions stated here are those of the author, and do not represent opinions of The Portland Group, Inc. or STMicroelectronics, Inc.

Subscribe to HPCwire's Weekly Update!

Be the most informed person in the room! Stay ahead of the tech trends with industy updates delivered to you every week!

HPE Wins $57 Million DoD Supercomputing Contract

February 20, 2018

Hewlett Packard Enterprise (HPE) today revealed details of its massive $57 million HPC contract with the U.S. Department of Defense (DoD). The deal calls for HPE to provide the DoD High Performance Computing Modernizatio Read more…

By Tiffany Trader

Topological Quantum Superconductor Progress Reported

February 20, 2018

Overcoming sensitivity to decoherence is a persistent stumbling block in efforts to build effective quantum computers. Now, a group of researchers from Chalmers University of Technology (Sweden) report progress in devisi Read more…

By John Russell

Fluid HPC: How Extreme-Scale Computing Should Respond to Meltdown and Spectre

February 15, 2018

The Meltdown and Spectre vulnerabilities are proving difficult to fix, and initial experiments suggest security patches will cause significant performance penalties to HPC applications. Even as these patches are rolled o Read more…

By Pete Beckman

HPE Extreme Performance Solutions

Safeguard Your HPC Environment with the World’s Most Secure Industry Standard Servers

Today’s organizations operate in an environment with ever-evolving threats, and in order to protect themselves they must continuously bolster their security strategy. Hewlett Packard Enterprise (HPE) and Intel® are addressing modern security challenges with the world’s most secure industry standard servers powered by the latest generation of Intel® Xeon® Scalable processors. Read more…

Intel Touts Silicon Spin Qubits for Quantum Computing

February 14, 2018

Debate around what makes a good qubit and how best to manufacture them is a sprawling topic. There are many insistent voices favoring one or another approach. Referencing a paper published today in Nature, Intel has offe Read more…

By John Russell

Fluid HPC: How Extreme-Scale Computing Should Respond to Meltdown and Spectre

February 15, 2018

The Meltdown and Spectre vulnerabilities are proving difficult to fix, and initial experiments suggest security patches will cause significant performance penal Read more…

By Pete Beckman

Brookhaven Ramps Up Computing for National Security Effort

February 14, 2018

Last week, Dan Coats, the director of Director of National Intelligence for the U.S., warned the Senate Intelligence Committee that Russia was likely to meddle in the 2018 mid-term U.S. elections, much as it stands accused of doing in the 2016 Presidential election. Read more…

By John Russell

AI Cloud Competition Heats Up: Google’s TPUs, Amazon Building AI Chip

February 12, 2018

Competition in the white hot AI (and public cloud) market pits Google against Amazon this week, with Google offering AI hardware on its cloud platform intended Read more…

By Doug Black

Russian Nuclear Engineers Caught Cryptomining on Lab Supercomputer

February 12, 2018

Nuclear scientists working at the All-Russian Research Institute of Experimental Physics (RFNC-VNIIEF) have been arrested for using lab supercomputing resources to mine crypto-currency, according to a report in Russia’s Interfax News Agency. Read more…

By Tiffany Trader

The Food Industry’s Next Journey — from Mars to Exascale

February 12, 2018

Global food producer and one of the world's leading chocolate companies Mars Inc. has a unique perspective on the impact that exascale computing will have on the food industry. Read more…

By Scott Gibson, Oak Ridge National Laboratory

Singularity HPC Container Start-Up – Sylabs – Emerges from Stealth

February 8, 2018

The driving force behind Singularity, the popular HPC container technology, is bringing the open source platform to the enterprise with the launch of a new vent Read more…

By George Leopold

Dell EMC Debuts PowerEdge Servers with AMD EPYC Chips

February 6, 2018

AMD notched another EPYC processor win today with Dell EMC’s introduction of three PowerEdge servers (R6415, R7415, and R7425) based on the EPYC 7000-series p Read more…

By John Russell

‘Next Generation’ Universe Simulation Is Most Advanced Yet

February 5, 2018

The research group that gave us the most detailed time-lapse simulation of the universe’s evolution in 2014, spanning 13.8 billion years of cosmic evolution, is back in the spotlight with an even more advanced cosmological model that is providing new insights into how black holes influence the distribution of dark matter, how heavy elements are produced and distributed, and where magnetic fields originate. Read more…

By Tiffany Trader

Inventor Claims to Have Solved Floating Point Error Problem

January 17, 2018

"The decades-old floating point error problem has been solved," proclaims a press release from inventor Alan Jorgensen. The computer scientist has filed for and Read more…

By Tiffany Trader

Japan Unveils Quantum Neural Network

November 22, 2017

The U.S. and China are leading the race toward productive quantum computing, but it's early enough that ultimate leadership is still something of an open questi Read more…

By Tiffany Trader

AMD Showcases Growing Portfolio of EPYC and Radeon-based Systems at SC17

November 13, 2017

AMD’s charge back into HPC and the datacenter is on full display at SC17. Having launched the EPYC processor line in June along with its MI25 GPU the focus he Read more…

By John Russell

Researchers Measure Impact of ‘Meltdown’ and ‘Spectre’ Patches on HPC Workloads

January 17, 2018

Computer scientists from the Center for Computational Research, State University of New York (SUNY), University at Buffalo have examined the effect of Meltdown Read more…

By Tiffany Trader

IBM Begins Power9 Rollout with Backing from DOE, Google

December 6, 2017

After over a year of buildup, IBM is unveiling its first Power9 system based on the same architecture as the Department of Energy CORAL supercomputers, Summit a Read more…

By Tiffany Trader

Nvidia Responds to Google TPU Benchmarking

April 10, 2017

Nvidia highlights strengths of its newest GPU silicon in response to Google's report on the performance and energy advantages of its custom tensor processor. Read more…

By Tiffany Trader

Fast Forward: Five HPC Predictions for 2018

December 21, 2017

What’s on your list of high (and low) lights for 2017? Volta 100’s arrival on the heels of the P100? Appearance, albeit late in the year, of IBM’s Power9? Read more…

By John Russell

Russian Nuclear Engineers Caught Cryptomining on Lab Supercomputer

February 12, 2018

Nuclear scientists working at the All-Russian Research Institute of Experimental Physics (RFNC-VNIIEF) have been arrested for using lab supercomputing resources to mine crypto-currency, according to a report in Russia’s Interfax News Agency. Read more…

By Tiffany Trader

Leading Solution Providers

Chip Flaws ‘Meltdown’ and ‘Spectre’ Loom Large

January 4, 2018

The HPC and wider tech community have been abuzz this week over the discovery of critical design flaws that impact virtually all contemporary microprocessors. T Read more…

By Tiffany Trader

Perspective: What Really Happened at SC17?

November 22, 2017

SC is over. Now comes the myriad of follow-ups. Inboxes are filled with templated emails from vendors and other exhibitors hoping to win a place in the post-SC thinking of booth visitors. Attendees of tutorials, workshops and other technical sessions will be inundated with requests for feedback. Read more…

By Andrew Jones

How Meltdown and Spectre Patches Will Affect HPC Workloads

January 10, 2018

There have been claims that the fixes for the Meltdown and Spectre security vulnerabilities, named the KPTI (aka KAISER) patches, are going to affect applicatio Read more…

By Rosemary Francis

GlobalFoundries, Ayar Labs Team Up to Commercialize Optical I/O

December 4, 2017

GlobalFoundries (GF) and Ayar Labs, a startup focused on using light, instead of electricity, to transfer data between chips, today announced they've entered in Read more…

By Tiffany Trader

Tensors Come of Age: Why the AI Revolution Will Help HPC

November 13, 2017

Thirty years ago, parallel computing was coming of age. A bitter battle began between stalwart vector computing supporters and advocates of various approaches to parallel computing. IBM skeptic Alan Karp, reacting to announcements of nCUBE’s 1024-microprocessor system and Thinking Machines’ 65,536-element array, made a public $100 wager that no one could get a parallel speedup of over 200 on real HPC workloads. Read more…

By John Gustafson & Lenore Mullin

Flipping the Flops and Reading the Top500 Tea Leaves

November 13, 2017

The 50th edition of the Top500 list, the biannual publication of the world’s fastest supercomputers based on public Linpack benchmarking results, was released Read more…

By Tiffany Trader

V100 Good but not Great on Select Deep Learning Aps, Says Xcelerit

November 27, 2017

Wringing optimum performance from hardware to accelerate deep learning applications is a challenge that often depends on the specific application in use. A benc Read more…

By John Russell

SC17: Singularity Preps Version 3.0, Nears 1M Containers Served Daily

November 1, 2017

Just a few months ago about half a million jobs were being run daily using Singularity containers, the LBNL-founded container platform intended for HPC. That wa Read more…

By John Russell

  • arrow
  • Click Here for More Headlines
  • arrow
Share This