Compilers and More: Gloptimizations

By Michael Wolfe

November 9, 2007

In my last column, I discussed the performance improvements on one of the SPEC CPU2000 floating point benchmarks, 172.mgrid, between 1999 and 2006, and introduced an optimization (which we call Loop-Carried Redundancy Elimination) that improves mgrid significantly. The SPEC CPU committee has been quite careful with benchmarks that are sensitive to compiler tricks. The original SPEC ’89 benchmark suite included 030.matrix300 (dense matrix multiplication). Since matrix multiplication is one of a set of core operations performed in many numerical applications, it was considered a good candidate for a benchmark. But, to quote Reinhold Weicker from the SPEC Newsletter (December 1995): “However, if a program becomes a benchmark, compiler authors can become very creative.”

In this case, compilers were modified to aggressively tile the loops; in each tile, the program performs a sub-matrix multiplication where the submatrices fit into the cache memory, improving the total performance by up to a factor of eight. (The term “loop tiling” or “iteration space tiling” was actually suggested by my wife in 1986; I was looking for a better term to use in a paper, she was looking at the kitchen floor.) Since this one optimization had such a big impact, and didn’t apply to the other benchmarks, the SPEC committee decided that it was not a fair contributor to an overall performance metric, and matrix300 was retired in 1992.

I noted last time that Dell had published a SPEC CPU2000 run in November 1999 on a 733 MHz Pentium III Precision Workstation 420, and another in October 2006 on a 2.66 GHz Core 2 Extreme Precision Workstation 390. I chose to compare these two runs simply because they were from the same vendor seven years apart. The base CFP2000 proved from 242 to 2679, a factor of just over 11. The big winner was 179.art, which improved from a ratio of 313 to 9306, almost a factor of 30 speedup. What accounts for this factor of 30? Can we expect similar improvements for any other program?

One way to achieve great speedups is to make the base case really slow; then, even simple optimizations can deliver a nice improvement. Sometimes, the program is written in a way that seems intentionally aimed at making it run slowly. Such a case appears in ART.

The ART benchmark (Adaptive Resonance Theory neural network for image ecognition) is written in C, and the critical loop is:

    struct{
double *I; double W, X, V, U, P, Q, R;
} * f1_layer;
double **bus;
....
for( tj = 0; tj < numf2s; tj++ ){
Y[tj].y = 0;
if( !Y[tj].reset )
for( ti = 0; ti < numf1s; ti++ )
Y[tj].y += f1_layer[ti].P * bus[ti][tj];
}

This loop appears in several places in the program, and much of the time of the program is spent in it; speed up this loop and the program runs fast.

However, there are several problems here. The struct f1_layer has 8 members, each 8 bytes long (assuming 64-bit pointers). That means each element of f1_layer takes up a whole 64-byte cache line. So while we’re traversing the array f1_layer in the inner loop, we only use one value out of each cache line. Even worse, the two-dimensional array bus is dynamically allocated, and we are traversing down the columns; that means two memory accesses (to get the row pointer bus[ti], then the value bus[ti][tj]). In both cases, the program abuses memory bandwidth in the inner loop, unless the whole dataset fits in the cache.

A few more comments: it turns out the inner loop has a trip count of about 10,000, while the outer loop has only 6 iterations, and the conditional around the inner loop never trips (reset is always 0), at least not in the benchmark datasets, so the inner loop is always executed. These facts are known only at runtime, however.

I’ve seen three ways to make this loop run much faster.  Some compilers implement what has been called the ART hack, reorganizing the data for the struct f1_layer. The array-of-struct is reorganized to become a struct of arrays. It takes the same amount of space, but now each element f1_layer[ti].P become f1_layer.P[ti], so consecutive elements are adjacent in the cache, and the performance of the cache and the whole program improves greatly.

    struct{
double **I; double *W, *X, *V, *U, *P, *Q, *R;
} f1_layer;
double **bus;
....
for( tj = 0; tj < numf2s; tj++ ){
Y[tj].y = 0;
if( !Y[tj].reset )
for( ti = 0; ti < numf1s; ti++ )
Y[tj].y += f1_layer.P[ti] * bus[ti][tj];
}

I did this by hand on an older Intel 3.4GHz EM64T Xeon, using the PGI compilers, and measured a 49% performance improvement. You can imagine what kind of whole program analysis would allow or disallow this reorganization, and it is very rarely feasible. However, this benchmark is so important that some compilers take this step. Here’s an optimization (to abuse the term) that would never have been invented if not for this particular benchmark.

A different trick is to interchange the two loops. The problem being solved is the accesses to the array bus, which are non-adjacent, have no locality, and require two loads per iteration, problems which go away if the two loops are interchanged. However, after interchanging, the new inner loop has a very short trip count (though the compiler probably doesn’t know that). The other more serious problem is that interchanging the loops brings the conditional inside both loops.

    struct{
double *I; double W, X, V, U, P, Q, R;
} * f1_layer;
double **bus;
....
for( tj = 0; tj < numf2s; tj++ )
Y[tj].y = 0;
for( ti = 0; ti < numf1s; ti++ ){
for( tj = 0; tj < numf2s; tj++ )
if( !Y[tj].reset )
Y[tj].y += f1_layer[ti].P * bus[ti][tj];
}

On the same Xeon, I measured a speedup of 2.33. However, this is quite dangerous, from a performance standpoint; instead of ‘numf2s’ conditional tests, there are now ‘numf1s*numf2s’ tests. If the test tripped at all, the modified version could execute quite a bit slower than the original. Yet, at least one compiler implements this and gets more than a factor of two improvement in the whole program, mostly due to this loop transformation.

The third trick, not implemented by any compiler (yet, that I know of), is to leave the loops the way they are and to transpose the array bus (and a similarly accessed array, tds). It turns out these arrays are dynamically allocated, but accessed in the wrong dimension. If we transpose the dimensions, the performance of this loop and the whole program really screams. On that same Xeon, I measured a speedup of 4.3.

This last is somewhat harder to implement automatically. The most severe problem is that C doesn’t really have two-dimensional arrays; to get a two-dimensional dynamic array, the program has to first allocate a one-dimensional vector of pointers. To transpose an array, the program has to allocate a vector of a different size. Purists argue that the modified program might allocate more space, and hence might run out of memory for some large datasets.

Moreover, the performance improvements are not very stable. The speedups I measured on the EM64T were 1.49 for array-of-struct reorganization, 2.3 for loop interchange, and 4.3 for for array transposition. Last month, I compared performance using an older 733MHz Intel Pentium III and a 2.66GHz Intel Core 2 Extreme. The speedups for these three optimizations on these two machines (and the EM64T) are summarized here:

       EM64T   PIII      Core2
        1.49       1.64      1.08    array-of-struct reorganization
        2.33       1.00      1.03    loop interchange
        4.34       1.19      1.48    array transpose

I am guessing that these optimizations have much less effect on the latest Core 2 because the data all fits in the much larger cache.

So, last month I discussed compiler tuning for 172.mgrid, where a new optimization improved its performance about 20%; happily, we’ve found this new feature applies in many other user applications as well. This month, I presented compiler tuning for 179.art, where aggressive optimization can improve the performance by factors (on some machines). I won’t go into the hacks, tricks, and other tuning for the other SPEC CPU2000 benchmarks; the number of compiler tricks is linearly related to the number of benchmarks.

With the increased importance of benchmark performance, compiler development teams are encouraged to aggressive (or even heroic) efforts to optimize performance on these programs. The only reason they do so is that vendors and users (and compiler product managers) place artificial importance on certain benchmark results. Yet, these optimizations, while impressive, may be of little value, or no value, or even negative value among the more general user domain, or even on the same program with different inputs. As shown here for ART, the value of the optimization may decrease to essentially zero as the architecture progresses.

Therefore, in the spirit of the Golden Raspberry award (http://www.razzies.com/) and the Ig Nobel Prizes (http://www.improbable.com/ig), I propose that we honor the most outrageous, benchmark-specific optimization with an award of its own, the Gloptimization award, or Gloppy for short. The award itself would be a pile of glop (or representation thereof), defined in my American Heritage Dictionary as “n. 1. A messy mixture, as of food. 2. Something, as writing, that is worthless. v. 1. To cover with glop. 2. To put glop on.” The award, at least, is appropriate. More credit should be given to an optimization that applies to a single benchmark; extra credit if it measureably slows down other benchmarks or applications. Posthumous awards can be proposed for optimizations that are actually removed from compilers as the targeted benchmarks are themselves retired. The optimizations mentioned above would certainly be candidates for a Gloppy, though perhaps not winners.

The lesson for customers is that standard benchmarks are valuable tools, but should not be the only or primary means of comparing system performance. The best measure is always the performance of your own applications, to which the systems and accompanying software are not specifically tuned.

SPEC (R) is a registered trademark of the Standard Performance Evaluation Corporation (http://www.spec.org/).

—–

Michael Wolfe has developed compilers for over 30 years in both academia and industry, and is now a senior compiler engineer at The Portland Group, Inc. (www.pgroup.com), a wholly-owned subsidiary of STMicroelectronics, Inc. The opinions stated here are those of the author, and do not represent opinions of The Portland Group, Inc. or STMicroelectronics, Inc.

Subscribe to HPCwire's Weekly Update!

Be the most informed person in the room! Stay ahead of the tech trends with industy updates delivered to you every week!

Long Flights to Cluster Fights: Meet the Asian Student Cluster Teams

November 22, 2017

Five teams from Asia traveled thousands of miles to compete at the SC17 Student Cluster Competition in Denver. Our cameras were there to meet ‘em, greet ‘em, and grill ‘em about their clusters and how they’re doi Read more…

By Dan Olds

Japan Unveils Quantum Neural Network

November 22, 2017

The U.S. and China are leading the race toward productive quantum computing, but it's early enough that ultimate leadership is still something of an open question. The latest geo-region to throw its hat in the quantum co Read more…

By Tiffany Trader

Perspective: What Really Happened at SC17?

November 22, 2017

SC is over. Now comes the myriad of follow-ups. Inboxes are filled with templated emails from vendors and other exhibitors hoping to win a place in the post-SC thinking of booth visitors. Attendees of tutorials, workshop Read more…

By Andrew Jones

HPE Extreme Performance Solutions

HPE Wins “Best HPC Server” for the Apollo 6000 Gen10 System

Hewlett Packard Enterprise (HPE) was nominated for 14 HPCwire Readers’ and Editors’ Choice Awards—including “Best High Performance Computing (HPC) Server Product or Technology” and “Top Supercomputing Achievement.” The HPE Apollo 6000 Gen10 was named “Best HPC Server” of 2017. Read more…

Turnaround Complete, HPE’s Whitman Departs

November 22, 2017

Having turned around the aircraft carrier the Silicon Valley icon had become, Meg Whitman is leaving the helm of a restructured Hewlett Packard. Her successor, technologist Antonio Neri will now guide what Whitman assert Read more…

By George Leopold

Long Flights to Cluster Fights: Meet the Asian Student Cluster Teams

November 22, 2017

Five teams from Asia traveled thousands of miles to compete at the SC17 Student Cluster Competition in Denver. Our cameras were there to meet ‘em, greet ‘em Read more…

By Dan Olds

Perspective: What Really Happened at SC17?

November 22, 2017

SC is over. Now comes the myriad of follow-ups. Inboxes are filled with templated emails from vendors and other exhibitors hoping to win a place in the post-SC Read more…

By Andrew Jones

SC Bids Farewell to Denver, Heads to Dallas for 30th Anniversary

November 17, 2017

After a jam-packed four-day expo and intensive six-day technical program, SC17 has wrapped up another successful event that brought together nearly 13,000 visit Read more…

By Tiffany Trader

SC17 Keynote – HPC Powers SKA Efforts to Peer Deep into the Cosmos

November 17, 2017

This week’s SC17 keynote – Life, the Universe and Computing: The Story of the SKA Telescope – was a powerful pitch for the potential of Big Science projects that also showcased the foundational role of high performance computing in modern science. It was also visually stunning. Read more…

By John Russell

How Cities Use HPC at the Edge to Get Smarter

November 17, 2017

Cities are sensoring up, collecting vast troves of data that they’re running through predictive models and using the insights to solve problems that, in some Read more…

By Doug Black

Student Cluster LINPACK Record Shattered! More LINs Packed Than Ever before!

November 16, 2017

Nanyang Technological University, the pride of Singapore, utterly destroyed the Student Cluster Competition LINPACK record by posting a score of 51.77 TFlop/s a Read more…

By Dan Olds

Hyperion Market Update: ‘Decent’ Growth Led by HPE; AI Transparency a Risk Issue

November 15, 2017

The HPC market update from Hyperion Research (formerly IDC) at the annual SC conference is a business and social “must,” and this year’s presentation at S Read more…

By Doug Black

Nvidia Focuses Its Cloud Containers on HPC Applications

November 14, 2017

Having migrated its top-of-the-line datacenter GPU to the largest cloud vendors, Nvidia is touting its Volta architecture for a range of scientific computing ta Read more…

By George Leopold

US Coalesces Plans for First Exascale Supercomputer: Aurora in 2021

September 27, 2017

At the Advanced Scientific Computing Advisory Committee (ASCAC) meeting, in Arlington, Va., yesterday (Sept. 26), it was revealed that the "Aurora" supercompute Read more…

By Tiffany Trader

NERSC Scales Scientific Deep Learning to 15 Petaflops

August 28, 2017

A collaborative effort between Intel, NERSC and Stanford has delivered the first 15-petaflops deep learning software running on HPC platforms and is, according Read more…

By Rob Farber

Oracle Layoffs Reportedly Hit SPARC and Solaris Hard

September 7, 2017

Oracle’s latest layoffs have many wondering if this is the end of the line for the SPARC processor and Solaris OS development. As reported by multiple sources Read more…

By John Russell

AMD Showcases Growing Portfolio of EPYC and Radeon-based Systems at SC17

November 13, 2017

AMD’s charge back into HPC and the datacenter is on full display at SC17. Having launched the EPYC processor line in June along with its MI25 GPU the focus he Read more…

By John Russell

Nvidia Responds to Google TPU Benchmarking

April 10, 2017

Nvidia highlights strengths of its newest GPU silicon in response to Google's report on the performance and energy advantages of its custom tensor processor. Read more…

By Tiffany Trader

Google Releases Deeplearn.js to Further Democratize Machine Learning

August 17, 2017

Spreading the use of machine learning tools is one of the goals of Google’s PAIR (People + AI Research) initiative, which was introduced in early July. Last w Read more…

By John Russell

GlobalFoundries Puts Wind in AMD’s Sails with 12nm FinFET

September 24, 2017

From its annual tech conference last week (Sept. 20), where GlobalFoundries welcomed more than 600 semiconductor professionals (reaching the Santa Clara venue Read more…

By Tiffany Trader

Amazon Debuts New AMD-based GPU Instances for Graphics Acceleration

September 12, 2017

Last week Amazon Web Services (AWS) streaming service, AppStream 2.0, introduced a new GPU instance called Graphics Design intended to accelerate graphics. The Read more…

By John Russell

Leading Solution Providers

SC17 Booth Video Tours

EU Funds 20 Million Euro ARM+FPGA Exascale Project

September 7, 2017

At the Barcelona Supercomputer Centre on Wednesday (Sept. 6), 16 partners gathered to launch the EuroEXA project, which invests €20 million over three-and-a-half years into exascale-focused research and development. Led by the Horizon 2020 program, EuroEXA picks up the banner of a triad of partner projects — ExaNeSt, EcoScale and ExaNoDe — building on their work... Read more…

By Tiffany Trader

Delays, Smoke, Records & Markets – A Candid Conversation with Cray CEO Peter Ungaro

October 5, 2017

Earlier this month, Tom Tabor, publisher of HPCwire and I had a very personal conversation with Cray CEO Peter Ungaro. Cray has been on something of a Cinderell Read more…

By Tiffany Trader & Tom Tabor

Cray Moves to Acquire the Seagate ClusterStor Line

July 28, 2017

This week Cray announced that it is picking up Seagate's ClusterStor HPC storage array business for an undisclosed sum. "In short we're effectively transitioning the bulk of the ClusterStor product line to Cray," said CEO Peter Ungaro. Read more…

By Tiffany Trader

Reinders: “AVX-512 May Be a Hidden Gem” in Intel Xeon Scalable Processors

June 29, 2017

Imagine if we could use vector processing on something other than just floating point problems.  Today, GPUs and CPUs work tirelessly to accelerate algorithms Read more…

By James Reinders

Intel Launches Software Tools to Ease FPGA Programming

September 5, 2017

Field Programmable Gate Arrays (FPGAs) have a reputation for being difficult to program, requiring expertise in specialty languages, like Verilog or VHDL. Easin Read more…

By Tiffany Trader

HPC Chips – A Veritable Smorgasbord?

October 10, 2017

For the first time since AMD's ill-fated launch of Bulldozer the answer to the question, 'Which CPU will be in my next HPC system?' doesn't have to be 'Whichever variety of Intel Xeon E5 they are selling when we procure'. Read more…

By Dairsie Latimer

Flipping the Flops and Reading the Top500 Tea Leaves

November 13, 2017

The 50th edition of the Top500 list, the biannual publication of the world’s fastest supercomputers based on public Linpack benchmarking results, was released Read more…

By Tiffany Trader

IBM Advances Web-based Quantum Programming

September 5, 2017

IBM Research is pairing its Jupyter-based Data Science Experience notebook environment with its cloud-based quantum computer, IBM Q, in hopes of encouraging a new class of entrepreneurial user to solve intractable problems that even exceed the capabilities of the best AI systems. Read more…

By Alex Woodie

Share This