Because of the volume of news in this, the week before SC, I’ve shortened the entries somewhat in an attempt to keep this summary shorter than book 7 of the Harry Potter series. You can always find more detail by following the links for each story.
As always, I present a collection of highlights, selected totally subjectively, from this week’s HPC news stream as reported at insideHPC.com and HPCwire.
>>10 words and a link
IBM fails to ship Barcelona systems, benchmark results labeled “non-compliant;
HPC startup SiCortex announces deskside supercomputer;
Intel announces revved multicore development products, compilers;
Terascala intros new Lustre-based storage device;
NSF awards NCSA $18M;
Purdue named NSF HPC center;
New Mexico makes investment in 172 TFLOP SGI;
Evergrid readies novel load management solutions;
>>Cray announces XT5 line of supers
Cray announced the latest installment in the XT series of scalable supercomputers, the XT5 family. The new Cray XT5 massively parallel processor (MPP) system incorporates a new compute blade that will quadruple local memory capacity, double processor density and improve energy efficiency. The XT5 family also includes the first hybrid supercomputer, the XT5h, with support for vector and FPGA blades alongside the Opteron blades in a single system fabric. More at http://insidehpc.com/2007/11/06/cray-announces-xt5-series-supercomputers/, and elsewhere in this edition of HPCwire.
>>HP announces Accelerator and Multi-Core Optimization programs
HP has announced two new HPC performance programs. The new HPC Accelerator program gives accelerator vendors a path to qualify their offerings with ProLiant and BladeSystem hardware. Current partners include ClearSpeed, Celoxica, NVIDIA, AMD, RapidMind and Mitrionics.
The Multi-Core Optimization Program (MCOP) was announced in June, and has been expanded. From the press release (http://www.hp.com/hpinfo/newsroom/press/2007/071101a.html):
The program brings together developments from HP and its partners to provide open, non-proprietary solutions that enhance multi-core performance across a variety of industry-standard HPC architectures, platforms and operating environments. By optimizing multi-core solutions, customers can maximize application performance on multi-core systems, enabling larger simulations and more data analysis that is necessary to achieve their engineering, science and analytical goals.
New members of the program include: Allinea, Interactive Supercomputing, The Portland Group, RapidMind, Stanford Pervasive Parallelism Lab and Visual Numerics.
More information on both programs at http://insidehpc.com/2007/11/05/hps-accelerator-and-multicore-optimization-programs/.
>>RapidMind revs multicore development platform
RapidMind announced this week that they’ve released version 3.0 of their Multi-core Development Platform, an application development suite designed to help coders get the most performance out of multicore platforms from Intel and AMD as well as GPGPUs and the Cell.
>>Allinea’s DDT available on the XT
This week they’ve announced that their flagship parallel debugging tool, the Distributed Debugging Tool (DDT), is now available for the Cray XT4 and 5.
>>TotalView previews reverse debugging
TotalView announced this week they’ll be previewing “reverse debugging” at SC07 next week. The press release (http://www.totalviewtech.com/press_release.htm?id=90) states that the new reverse debugging features will allow developers to:
- Capture and replay the exact behavior of the program from any point in the past during a single debugging session.
- Step backward from crashes and out of functions to see what went wrong.
- Jump forward and backward to examine and compare any set of points along the captured execution sequence.
- Replay thread context switches exactly as they happened.
- Seamlessly and clearly switch between record mode and replay mode.