Tis the Season

By Michael Feldman

November 9, 2007

The supercomputing conference season is merging into the holiday shopping season and both are starting earlier every year. The International Conference for High Performance Computing, Networking and Storage (SC07) in Reno, Nevada doesn’t officially begin until next week, but a bunch of vendors decided to get a jump on the festivities by pre-announcing some of their upcoming offerings. Here’s a few products to consider as you assemble your HPC holiday shopping list:

From Cray: For the Supercomputing Center that Has Everything

On Monday, Cray announced its new XT5 supercomputing family. In a nutshell, the new architecture represents an upgrade to the XT4 plus a hybrid computing variant, the XT5h. The XT5h incorporates FPGAs and new vector hardware into the XT5 architecture. As such, the new family represents a big step toward Cray’s unified adaptive computing vision.

A vanilla quad-core Opteron-based XT5 cabinet achieves about a very respectable 7 teraflops. But Cray barely mentions peak performance anymore. To them it’s like discussing the machine’s weight — impolite and not very relevant. And once you start adding vector and FPGA blades into the system, the peak performance metrics become even less significant. Cray would much prefer the conversation focus on sustained applications performance and scalability. That becomes a more intimate discussion, but when you’re selling multi-million dollar systems, your bound to have it.

Even though the XT5 make multiple architectures available in a single system, the software developer still needs to know how to divvy up the code and apply it across the different types of hardware. Cray’s next step is to implement an adaptive software layer that can automagically split up the code and map it to the most appropriate architecture. This set of compiler and runtime technologies will be crafted as part of the DARPA-funded HPCS program, which will result in Cray’s Cascade system by the end of the decade.

The commercial successor to the XT5 family in 2010 is “Baker,” which will introduce a number of advanced features, including a brand new high performance interconnect, as well as global memory across the entire machine. Beyond that, the post-2010 “Granite” machine will integrate vector processing and Cray’s XMT multithreaded technology. If Cray’s complete vision of adaptive computing is realized, these systems will enable a whole new generation of supercomputing applications.

To delve a little deeper into the XT5, read our feature article in this week’s issue.

From RapidMind: Gift-Wrapped Multicore Development

Initially supporting GPU and Cell processor hardware, RapidMind has now included support for x86 multicore processors in version 3.0 of its software development platform. The RapidMind platform is designed so that developers can program in standard C++, building parallel applications that are portable across a variety of processor architectures. The multicore x86 support is such that the application binaries transparently adapt as users move them to processors with different core counts, cache sizes, and SSE instruction sets.

Under the covers, the runtime is exploiting multiple parallelism mechanisms including instruction pipelining, SIMD instructions, overlapping memory access with computation, multithreading within a core, multicore workload distribution, multiprocessor workload distribution, and asynchronous host and accelerator execution. Because the software digs deep into its parallel computing bag of tricks, x86 applications are often accelerated beyond what one might expect just from utilizing more cores. The company has demonstrated an 8X speedup on quad-core processors versus a single-core processor using vanilla C++.

The overall goal of the platform is to provide a high-level programming environment for some the most popular high performance computing processors — GPUs, the Cell BE processor, and now with version 3.0, multicore x86 processors from AMD and Intel. There’s a lot of exotic processor technology still trying to get traction in the marketplace, but the folks at RapidMind surmised that multicore commodity processors have the most assured path to marketplace acceptance. Now that they’ve closed the loop with x86 support, the platform offers a pretty complete solution, hardware-wise.

As readers of this publication are well-aware, writing software for multicore processors has been viewed as somewhat of a crisis by the software community. But it’s a slow-motion crisis. Multicore has infiltrated hardware platforms gradually over the past few years, which has encouraged many developers to procrastinate. Dual-core systems have been relatively easy to accommodate, both in the consumer space and the enterprise. Having an extra core meant the application or OS just had to find one additional task for the extra core. Now that processors with four cores are becoming mainstream (with eight-core systems on the way), the approach must be more general. It’s the difference between finding something for your assistant to do and managing a whole staff. The level of developer angst is about to ratchet up as hardware moves into quad territory.

“A lot of people view this as a threat,” says RapidMind CEO Ray DePaul. “If you look at it another way, this is a pretty major disruption that can generate a lot of opportunity for software companies, platform companies, HPC companies, IT companies and end users.”

The general consensus is that developing software for multiple cores is difficult, and in-house resources are not equipped to deal with this change. Programmers writing seismic analysis code or financial analytics generally don’t have the expertise or inclination to deal with multithreading, low-level data parallelism, etc. RapidMind is positioning its solution to fill that gap.

The platform has attracted the attention of IBM and HP, who are helping RapidMind get the word out. Both of these system vendors have a huge stake in lightening the software development load on their respective HPC server products. Although no reseller arrangements have been announced, both IBM and HP are helping to educate their customers and potential customers about the benefits of the RapidMind platform.

Version 3.0 of the RapidMind platform will be generally available in December. Pricing is based on a runtime license model.

From Intel: A Shiny New Toolset

On Wednesday, Intel announced a refresh of its HPC-applicable software development offerings, a product set that seems to be growing larger with each passing year. The market penetration of cluster computing and multicore processors are the two big trends that continue to shape the evolution of the toolset. Here’s a list of the offerings announced this week:

  • Intel Cluster Toolkit v3.1
  • Intel Cluster Toolkit Compiler Edition v3.1
  • Intel Trace Collector and Trace Analyzer v7.1
  • Intel MPI Library v3.1
  • Intel Math Kernel Library (MKL) v10.0
  • Intel C++ and Fortran Compilers v10.1
  • Intel Integrated Performance Primitives (IPP) v5.3

The Cluster Toolkit bundles the Trace Analyzer and Collector, Math Kernel Library (MKL), MPI Library, and MPI Benchmarks into a single package. The Cluster Toolkit Compiler Edition adds Intel’s C++ and Fortran compiler and their debugger, as well as the ability to automatically install the compilers across the cluster nodes.

“It’s a little bit more than just a bundle of products,” explains James Reinders, director of Marketing, Intel Software Development Products. “What’s happening is that as clusters get more and more standardized, it turns out people are looking for more turnkey solutions.”

They also now have complete support for Windows Compute Cluster Solution (CCS) across the toolset, adding that support in the MPI analysis tools and the MPI library. All the new products also provide optimized support for Penryn processors, including support for the new SSE4 instruction set. The Penryns are the company’s new 45nm processors set to officially launch next week.

The latest version of Intel’s Math Kernel Library represents a major release with lots of new goodies for the high performance computing crowd. As with the compiler products, they’ve included optimizations for the Penryn processor to take advantage of SSE4. As a nod to the mainstream status MPI has achieved, Intel has also included ScaLAPACK & Distributed Memory FFTs in the standard MKL product. In addition, an out-of-core memory solver (Parallel Direct Sparse Solver) has been included to enable users to tackle much larger problems using smaller memory footprints. The upgrades give the MKL a more HPC flavor, exploiting all the dimensions of parallelism: SIMD (through Penryn SSE4), multicore and MPI for clusters.

Additional OpenMP support has been added in the new tools, including compatibility between Intel’s OpenMP implementation and those from Microsoft and GNU implementations. This lets users mix software modules and libraries compiled with different environments and still maintain OpenMP functionality. Intel has also added support for its OpenMP on clusters software to their Trace Analyzer and Trace Collector tools.

Ironically, AMD also gets a bump when Intel upgrades its tools. All the Intel compiler and analysis tools listed above work on “the other guy’s” hardware too. And this is by design, not by accident.

“Not only do they work on AMD processors, but we work very, very hard to perform better on AMD processors than any competing products,” says Reinders. “It’s very important for our customers who build products based on our tools that they’re able to deploy a solution and feel comfortable that it will work really well on Intel and AMD hardware.”

The relationship may seem contradictory, but unlike Intel’s chip customers, the companies who buy Intel’s compilers demand that the product be vendor neutral. To be taken seriously as a software provider, Reinders says, they can’t be “playing any games.” According to him, they’ve done a really good job at getting the most out of AMD’s hardware. But he admits that kind of devotion occasionally creates some “discussion” inside Intel. I’ll bet.

From SiCortex: An HPC Doll

SiCortex has unveiled a 72-processor cluster machine that can fit in a deskside cabinet. The SC072 “Catapult” is priced at under $15,000, and is mainly intended as a development platform for the larger SiCortex systems. The company has also seen interest from people looking for a dedicated workstation for the development of high processor count codes.

According to SiCortex, the internal architecture is identical to its larger siblings, the SC5832 and SC648. It uses the same node chips, and the interconnect uses the same Kautz graph topology. As with the larger systems, I/O is via PCI Express slots connected to a subset of the nodes. The system draws less than 200 watts of power and fits in a standard PC chassis. Peak performance is 70 gigaflops. Cute.

From SGI: A New Set of Blades

Not to be left out of the hybrid supercomputing trend, SGI announced its new FPGA blade, the RC200. Unlike its previous FPGA technology for Itanium-based systems, the RC200 is targeted for the Altix XE and Altix ICE Xeon-based clusters and blade servers. The FPGA blades were built in conjunction with XtremeData, a supplier of FPGA technology for HPC. In September, the company announced modules based on Altera Stratix III FPGAs that could be latched on the Xeon front-side-bus.

Bringing FPGAs into x86 clusters could be real shot in the arm for reconfigurable computing in HPC. Up until now, it’s been difficult for cluster computing users to get access to this technology without a roll-your-own kind of approach.

From AMD: Double Precision GPU Goodies

After NVIDIA beat it to the punch with theTesla GPU computing products, AMD is fighting back. On Thursday, the company announced the AMD FireStream 9170, a GPU-based stream computing processor with double precision floating point capabilities. The processor is intended to be used to accelerate the usual litany of HPC applications: seismic processing, financial analysis, bioinformatics, etc. AMD says the chip will provide 500 gigaflops of single precision, but didn’t provide any metrics for double precision performance. It’s built with 55nm process technology and consumes less than 150 watts of power. All the specs are described here.

Although AMD is claiming the 9170 as the first double precision stream GPU, the product and the supporting software development kit won’t be available until Q1 2008. NVIDIA is also planning to release a double precision GPU computing product during the same timeframe. Let the games begin.

And Some Stocking Stuffers…

Fulcrum announced its new low-latency router switch chip, and startup Arastra unveiled a new high density switch box, based on the new Fulcrum silicon. We dig a little deeper into the story in our feature piece.

Another startup, Scalable Servers Corporation, exited from stealth mode this week and announced its flexBLADE technical workgroup computing platform for SMB customers. The company spun off from Tyan’s personal supercomputing group, following MiTAC’s acquisition of Tyan Computer Corporation earlier this year.

And finally, SGI was awarded an $11 million contract to build a 172 teraflop supercomputer for the New Mexico Computing Applications Center. Governor Bill Richardson took time out of his busy schedule running for Hillary’s vice-president to announce the deal.

SC07 Next Week!

Almost forgot. We’ll be providing special live coverage of the Supercomputer Conference in Reno next week with our three LIVEwire issues on Monday, Tuesday and Thursday evenings. I’ll be at the event all week, helping to bring you the best news coverage possible by a sleep-deprived individual. Stop by our HPCwire booth and have Ana explain why I’m not there.


As always, comments about HPCwire are welcomed and encouraged. Write to me, Michael Feldman, at [email protected].

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