Since 1987 - Covering the Fastest Computers in the World and the People Who Run Them

December 7, 2007

The Week in Review

by John E. West

Here is this week’s collection of highlights, selected totally subjectively, from the HPC news stream as reported at and HPCwire.

>>10 words and a link

IBM working on optical transfer of data between cores;

AMD drops off preliminary list of top 10 chip makers;

Cray receives first XT5 order;

BLS: jobs in computer fields and math growing fastest;

IDC: HPC server market grew to $3.0 billion in Q3;

DailyTech’s leaked memos on where Intel and AMD are going;

XtreemOS coming to a grid near you;

Star-P gets R, Vista support, and more;


AMD has announced that it has revised its plan to ramp-up production (and subsequent availability) of the quad-core Barcelona chips from Q4 of 2007 to Q1 of 2008. In October, the company stated that Barcelona silicon would be “widely available” by the end of the year.

There has been widespread speculation that the major delay in rollout is due to an erratum in the translation lookaside buffer [TLB]. The issue was made public by AMD some time ago and can be fixed with a BIOS update, but at the supposed cost of 10-20 percent of performance.

Impact on HPC? Unclear. From the DailyTech, we do know that Cray was allowed its allotment (

AMD partners tell DailyTech that all bulk Barcelona shipments have been halted pending application screening based on the customer. Cray, for example, was allowed its latest allocation for machines that will not use these nested virtualization techniques. Other AMD corporate customers were told to use Revision F3 (K8) processors in the meantime.

The language is a little muddled, since Cray is using Budapest, not Barcelona, but it seems likely that the TLB issue applies in the core part of the platform, not in the externals that differ between Barcelona and Budapest. It does appear that if you’re intending to run virtualization software on the chips, you aren’t going to be getting Barcelona for a while.

The Register is also covering the fun (, and I’m of a similar mind regarding AMD’s evasion of responsibility with the language here. The company is denying this is a “stop ship”:

“We haven’t changed the shipping pattern,” AMD man Phil Hughes told InternetNews. “It’s only a stop ship if it’s shipping in volume, and we’re only shipping Barcelona for specific customer commitments, like larger volume deployments.” AMD seems to be fiddling with language, as far as we’re concerned.

As far as I’m concerned, too. Dear AMD: take it like a man, fix the problem, and try to stop shooting your own feet for crying out loud.

>>Red Hat announces distributed computing capabilities

This week Linux vendor Red Hat announced a new package that adds distributed computing features based on Condor to its enterprise toolbox. From the release (

Red Hat today announced Red Hat Enterprise MRG (Messaging, Realtime, Grid), offering new capabilities for deployment on Red Hat Enterprise Linux and third-party operating platforms that further strengthen Red Hat’s position as the strategic supplier for critical enterprise applications in highly demanding environments, such as Financial Services and Government agencies. Red Hat Enterprise MRG is a revolutionary distributed computing platform that provides exceptional performance through reliable enterprise messaging, realtime capabilities and advanced grid and high-throughput computing technologies.

With specific regard to the distributed computing features:

Distributed Computing: Red Hat Enterprise MRG enables customers to leverage the full power of distributed computing with commercial- strength grid capabilities, based on the University of Wisconsin’s highly respected Condor high-throughput computing project. These capabilities provide customers with a practical means of using their total compute capacity with maximum efficiency and flexibility, while improving the speed and availability of any application. Additionally, Red Hat and the University of Wisconsin have signed a strategic agreement to make Condor’s source code available under an OSI-approved license and jointly fund ongoing co-development at the University of Wisconsin.

Seems like the wrong time of year, but there were many beginnings celebrated this week. Here are a few that caught my eye.

First up, the Army High Performance Computing Research Center (AHPCRC) cut a ribbon or two at Stanford University as they looked ahead to five years of contract bliss, and a new 1,600 core Dell cluster.

Next we have See3D, a new state-of-the-art visualization center (or centre) in Wales. Mechdyne announced this week they have installed some heavy duty immersive vis gear at See3D, including a 15-ft custom dome display and a PowerWall.

Not to be outdone, the Holland Computer Center is having opening ceremonies at the end of the week to celebrate the installation of its new 1,150 node AMD quadcore cluster in the Peter Kiewit Institute.

Then there was Argonne. Governor Rod R. Blagojevich announced this week that the State of Illinois has floated $70M in bonds to build a new 200,000 square foot facility. The new Theory and Computing Sciences Building will be located on Argonne’s campus in DuPage County, and will hold over 600 lab employees, an 18,000 square foot research library, labs, and a conference center.

>>Community resource: scholarships, fellowships and postdocs at insideHPC

I’ve created a special page to serve as the permanent home for all the information we can scrape together on scholarships, fellowships, and postdocs for students and recent graduates with an emphasis in HPC. You can find it at If you have more details on the ones I’ve posted, of if you know about one that I’ve missed, please drop me a line at


John West is part of the team that summarizes the headlines in HPC news every day at You can contact him at

Share This