Core Economics

By Michael Feldman

January 11, 2008

With all major chipmakers committed to the multicore path, it seems only a matter of time before manycore (processors with greater than 8 cores) becomes the standard architecture across all computing sectors. The 128-core NVIDIA GPUs, the Cisco’s 188-core Metro network processor, and the 64-core Tilera TILE64 processor are three early examples of this trend. The 80-core prototype demonstrated by Intel is an indication that even the most mainstream segments of the computer industry are looking to enter the manycore realm.

While most discussions of manycore tend to focus on software development challenges or memory bandwidth limitations, an even more fundamental issue is the economic model that will drive these products into the marketplace. This is the topic that researchers Joseph Sloan and Rakesh Kumar at the University of Illinois at Urbana-Champaign addressed recently in a paper titled, Hardware/System Support for Four Economic Models for Many Core Computing (http://passat.crhc.uiuc.edu/rakeshk/techrep_economic.pdf).

In the current model, customers buy systems containing processors that satisfy the average or worst-case computation needs of their applications. This means when the application requirements change, either the user has to live with the pain of a performance mismatch or go through the expense of purchasing new systems (or new chips) to realign system performance with the applications. Sloan and Rakesh argue that as the number of cores increase, matching the performance needs with applications becomes increasingly difficult and the associated cost of buying unused computing power becomes more prohibitive.

The chip vendors are effected as well. As the number of cores increase, chipmakers must decide on the number of processor configurations to apply to a given market segment. If one can fit 100 cores on a die, how many different variations can be rationalized? Certainly not 100. Intel will have to deal with a smaller version of this problem in its upcoming 45nm Nehalem microarchitecture. So far, the company has described only 2-, 4- and 8-core processor designs for Nehalem. But with the combination of different cache sizes, memory controller architectures and clock speeds, the new processor family will probably end up being the largest Intel has ever supported. When tens or hundreds of cores are the norm, practical considerations will limit the number of unique designs to a very small subset of possible core layouts.

In their paper, Sloan and Kumar propose four related economic models (five actually) for manycore computing. The overall approach is that the customer will usually need fewer cores than are physically present on the chip, but at times may want to use more of them. The authors suggest that chips be developed in such a way as to allow users to pay only for the computing power they need, rather than the peak computing power that is physically present. This can be accomplished with small pieces of logic incorporated into the processor that enables the vendor to disable/enable individual cores. (Presumably, disabled cores would draw little, if any, power.) Enabling or disabling cores involves contacting the vendor, who authenticates the chip and sends activation codes that are used to unlock or lock the specified cores. The user ends up paying only for the desired computing power.

Of the models proposed, the most restrictive approach, the IntelligentBaseline model, forces the user to make a onetime decision about the number of cores needed. In this model, the vendor enables the user-selected subset of cores on the chip before shipping. Each of the other four models — UpgradesOnly, Limited Up/Downgrade, CoresOnRent and PayPerUse — offers a way to change the available processing power of the chip dynamically:

  • The UpgradesOnly model is based on the fact that computation requirements tend to increase over time. The user initially purchases enough cores to satisfy their current processing requirements. Additional cores can be enabled anytime during the processor lifetime, avoiding a system upgrade until the user needs more processing power than is physically available on the chip.
  • The Limited Up/Downgrade model recognizes the fact that average computational needs may sometimes increase temporarily. This allows the user to scale up and down as computational needs warrant. Downgrades involve disabling the number of selected cores and providing some sort of refund to the user.
  • The CoresOnRent model recognizes that there are environments where computational requirements change a lot even over a short periods of time (months). In this case, it may be more reasonable for the user to rent cores rather than own them. In this model, the user contacts the vendor to get access to a specific number of cores for a specific lease period. When the lease expires, the user has the option to renew the lease — with more or less cores.
  • The PayPerUse model is the most unrestricted model. It frees the user from estimating computing requirements at all and just bills the user based on actual core usage over a specified lease period. Like the CoresOnRent model, the user never owns the cores.

The underlying assumption to all this is that the cost of manufacturing the processor does not rise linearly with the number of cores on the die, which allows the chip vendor to sell underutilized processors at a profit. According to Kumar, this is indeed the case. His assumption is that the factors that determine the cost of manufacturing often have nothing to do with the number of cores on a die.

“Going from a one-core chip to a manycore chip may often represent increased costs — due to higher design/verification overhead,” explains Kumar. “But, multiplying the number of cores on a manycore chip will increase costs only marginally [since] the same design can be stamped multiple times to multiply the number of cores on a die. In fact, one of the main reasons for going to many cores is the high degree of IP reuse, i.e., the computational power can be multiplied without much increased cost.”

Kumar admits that chip costs are dependent upon the die area, and if the number of cores increased that area, costs would increase linearly as well. But his contention is the die area is usually fixed because of yield considerations, so the cost does not change much.

Another issue is the strong coupling of the memory system with the peak performance of the processor. Sloan and Kumar suggest that the memory architecture should be composable to support system balance.

“Designing a composable memory hierarchy may not be a big technical challenge,” contends Kumar. “It is just that a strong need was not there in the desktop and mobile domains. Composable memory hierarchies have often been designed in server systems. For example, Capacity on Demand for IBM System i offer clients the ability to non-disruptively activate (no IPL required) processors and memory. Same for Unisys as well as Sun systems too. You can simply have a middleware or microcode that allows/disallows access to certain regions of memory. Alternatively, some the techniques that we developed for supporting and enforcing the proposed models can also be used for memory hierarchies. Composability can also be attained by physically modifying the memory controller or disk controller to decouple memory regions.”

However, the authors admit that in some cases composability may be difficult to achieve because system architectures may require memory hierarchies that are closely coupled with the core count. They also point out a number of other areas of concern, including compatibility with software licensing models (already an area of contention for multicore processors) and privacy/security issues related to vendors having access to customers’ hardware.

“I think that there is no clear answer as to what are the new economic models that we need or whether we need new economic models at all,” says Kumar. “But now may be the time when a discussion needs to start among academics, industry people, and everyone else who has a stake in it. At least an awareness of the issues is needed.”

Subscribe to HPCwire's Weekly Update!

Be the most informed person in the room! Stay ahead of the tech trends with industy updates delivered to you every week!

Pattern Computer – Startup Claims Breakthrough in ‘Pattern Discovery’ Technology

May 23, 2018

If it weren’t for the heavy-hitter technology team behind start-up Pattern Computer, which emerged from stealth today in a live-streamed event from San Francisco, one would be tempted to dismiss its claims of inventing Read more…

By John Russell

Intel, Micro Debut Quad-Level Cell NAND Flash

May 22, 2018

Chipmakers continue to gear designs toward AI and other demanding cloud workloads that take advantage of datacenter flash storage capacity. To that end, memory specialist Micron Technology Inc. began shipping compact sol Read more…

By George Leopold

Japan Meteorological Agency Takes Delivery of Pair of Crays

May 21, 2018

Cray has supplied two identical Cray XC50 supercomputers to the Japan Meteorological Agency (JMA) in northwestern Tokyo. Boasting more than 18 petaflops combined peak computing capacity, the new systems will extend the a Read more…

By Tiffany Trader

HPE Extreme Performance Solutions

HPC and AI Convergence is Accelerating New Levels of Intelligence

Data analytics is the most valuable tool in the digital marketplace – so much so that organizations are employing high performance computing (HPC) capabilities to rapidly collect, share, and analyze endless streams of data. Read more…

IBM Accelerated Insights

Mastering the Big Data Challenge in Cognitive Healthcare

Patrick Chain, genomics researcher at Los Alamos National Laboratory, posed a question in a recent blog: What if a nurse could swipe a patient’s saliva and run a quick genetic test to determine if the patient’s sore throat was caused by a cold virus or a bacterial infection? Read more…

ASC18: Final Results Revealed & Wrapped Up

May 17, 2018

It was an exciting week at ASC18 in Nanyang, China. The student teams braved extreme heat, extremely difficult applications, and extreme competition in order to cross the cluster competition finish line. The gala awards ceremony took place on Wednesday. The auditorium was packed with student teams, various dignitaries, the media, and other interested parties. So what happened? Read more…

By Dan Olds

Pattern Computer – Startup Claims Breakthrough in ‘Pattern Discovery’ Technology

May 23, 2018

If it weren’t for the heavy-hitter technology team behind start-up Pattern Computer, which emerged from stealth today in a live-streamed event from San Franci Read more…

By John Russell

Japan Meteorological Agency Takes Delivery of Pair of Crays

May 21, 2018

Cray has supplied two identical Cray XC50 supercomputers to the Japan Meteorological Agency (JMA) in northwestern Tokyo. Boasting more than 18 petaflops combine Read more…

By Tiffany Trader

ASC18: Final Results Revealed & Wrapped Up

May 17, 2018

It was an exciting week at ASC18 in Nanyang, China. The student teams braved extreme heat, extremely difficult applications, and extreme competition in order to cross the cluster competition finish line. The gala awards ceremony took place on Wednesday. The auditorium was packed with student teams, various dignitaries, the media, and other interested parties. So what happened? Read more…

By Dan Olds

Spring Meetings Underscore Quantum Computing’s Rise

May 17, 2018

The month of April 2018 saw four very important and interesting meetings to discuss the state of quantum computing technologies, their potential impacts, and th Read more…

By Alex R. Larzelere

Quantum Network Hub Opens in Japan

May 17, 2018

Following on the launch of its Q Commercial quantum network last December with 12 industrial and academic partners, the official Japanese hub at Keio University is now open to facilitate the exploration of quantum applications important to science and business. The news comes a week after IBM announced that North Carolina State University was the first U.S. university to join its Q Network. Read more…

By Tiffany Trader

Democratizing HPC: OSC Releases Version 1.3 of OnDemand

May 16, 2018

Making HPC resources readily available and easier to use for scientists who may have less HPC expertise is an ongoing challenge. Open OnDemand is a project by t Read more…

By John Russell

PRACE 2017 Annual Report: Exascale Aspirations; Industry Collaboration; HPC Training

May 15, 2018

The Partnership for Advanced Computing in Europe (PRACE) today released its annual report showcasing 2017 activities and providing a glimpse into thinking about Read more…

By John Russell

US Forms AI Brain Trust

May 11, 2018

Amid calls for a U.S. strategy for promoting AI development, the Trump administration is forming a senior-level panel to help coordinate government and industry research efforts. The Select Committee on Artificial Intelligence was announced Thursday (May 10) during a White House summit organized by the Office of Science and Technology Policy (OSTP). Read more…

By George Leopold

MLPerf – Will New Machine Learning Benchmark Help Propel AI Forward?

May 2, 2018

Let the AI benchmarking wars begin. Today, a diverse group from academia and industry – Google, Baidu, Intel, AMD, Harvard, and Stanford among them – releas Read more…

By John Russell

How the Cloud Is Falling Short for HPC

March 15, 2018

The last couple of years have seen cloud computing gradually build some legitimacy within the HPC world, but still the HPC industry lies far behind enterprise I Read more…

By Chris Downing

Russian Nuclear Engineers Caught Cryptomining on Lab Supercomputer

February 12, 2018

Nuclear scientists working at the All-Russian Research Institute of Experimental Physics (RFNC-VNIIEF) have been arrested for using lab supercomputing resources to mine crypto-currency, according to a report in Russia’s Interfax News Agency. Read more…

By Tiffany Trader

Nvidia Responds to Google TPU Benchmarking

April 10, 2017

Nvidia highlights strengths of its newest GPU silicon in response to Google's report on the performance and energy advantages of its custom tensor processor. Read more…

By Tiffany Trader

Deep Learning at 15 PFlops Enables Training for Extreme Weather Identification at Scale

March 19, 2018

Petaflop per second deep learning training performance on the NERSC (National Energy Research Scientific Computing Center) Cori supercomputer has given climate Read more…

By Rob Farber

AI Cloud Competition Heats Up: Google’s TPUs, Amazon Building AI Chip

February 12, 2018

Competition in the white hot AI (and public cloud) market pits Google against Amazon this week, with Google offering AI hardware on its cloud platform intended Read more…

By Doug Black

US Plans $1.8 Billion Spend on DOE Exascale Supercomputing

April 11, 2018

On Monday, the United States Department of Energy announced its intention to procure up to three exascale supercomputers at a cost of up to $1.8 billion with th Read more…

By Tiffany Trader

Lenovo Unveils Warm Water Cooled ThinkSystem SD650 in Rampup to LRZ Install

February 22, 2018

This week Lenovo took the wraps off the ThinkSystem SD650 high-density server with third-generation direct water cooling technology developed in tandem with par Read more…

By Tiffany Trader

Leading Solution Providers

HPC and AI – Two Communities Same Future

January 25, 2018

According to Al Gara (Intel Fellow, Data Center Group), high performance computing and artificial intelligence will increasingly intertwine as we transition to Read more…

By Rob Farber

Google Chases Quantum Supremacy with 72-Qubit Processor

March 7, 2018

Google pulled ahead of the pack this week in the race toward "quantum supremacy," with the introduction of a new 72-qubit quantum processor called Bristlecone. Read more…

By Tiffany Trader

HPE Wins $57 Million DoD Supercomputing Contract

February 20, 2018

Hewlett Packard Enterprise (HPE) today revealed details of its massive $57 million HPC contract with the U.S. Department of Defense (DoD). The deal calls for HP Read more…

By Tiffany Trader

CFO Steps down in Executive Shuffle at Supermicro

January 31, 2018

Supermicro yesterday announced senior management shuffling including prominent departures, the completion of an audit linked to its delayed Nasdaq filings, and Read more…

By John Russell

Deep Learning Portends ‘Sea Change’ for Oil and Gas Sector

February 1, 2018

The billowing compute and data demands that spurred the oil and gas industry to be the largest commercial users of high-performance computing are now propelling Read more…

By Tiffany Trader

Nvidia Ups Hardware Game with 16-GPU DGX-2 Server and 18-Port NVSwitch

March 27, 2018

Nvidia unveiled a raft of new products from its annual technology conference in San Jose today, and despite not offering up a new chip architecture, there were still a few surprises in store for HPC hardware aficionados. Read more…

By Tiffany Trader

Hennessy & Patterson: A New Golden Age for Computer Architecture

April 17, 2018

On Monday June 4, 2018, 2017 A.M. Turing Award Winners John L. Hennessy and David A. Patterson will deliver the Turing Lecture at the 45th International Sympo Read more…

By Staff

Part One: Deep Dive into 2018 Trends in Life Sciences HPC

March 1, 2018

Life sciences is an interesting lens through which to see HPC. It is perhaps not an obvious choice, given life sciences’ relative newness as a heavy user of H Read more…

By John Russell

  • arrow
  • Click Here for More Headlines
  • arrow
Share This