AMD Searches for an HPC Strategy

By Michael Feldman

February 15, 2008

Both Intel and NVIDIA have laid out a pretty clear strategy on how they’re going to attack the HPC market over the next year or so. Intel will continue to push out their 45nm Xeons, then the Nehalem processors, then Larrabee. NVIDIA will introduce 64-bit floating point support into their Tesla GPU computing line and continue to refine the CUDA programming environment. AMD, however, which is still reeling from a disastrous 2007, has seemed less focused on the high end of the market than ever before. The company’s stated mission to regain profitability in 2008 means it will refocus its energies on the volume market — desktop, laptop, mobile and embedded computing.

With that as a backdrop, I thought this might be a good time to talk with David Rich, director of marketing for HPC at AMD, and get a sense of the company’s strategy for high-end computing over the next year or two.

One of the first things that AMD would like to rectify this year is its visibility in the HPC community — or lack thereof. Rich admitted that they’ve been getting questions from people in the community wondering if they really care about HPC anymore. Not a good thing — especially when Intel is making a big push with its high performance Xeon processors, experimenting with 80-core teraflop processors and on-chip lasers, and just generally dominating the high-end computing conversation. “We recognize that we have not been as visible as we should have been [in the past], so we’re going to make an effort to be present at more HPC-oriented events,” says Rich.

Rich says they intend to make an extra effort to reconnect with HPC users this year, especially at the big conferences like the International Supercomputing Conference (ISC’08) in Dresden and the Supercomputing Expo and Conference (SC08) in Austin, Texas. AMD actually lucked out this year. Two of the companies big fabs are in Dresden, and Austin is a major business operations site. AMD is likely to use the home court advantage to have a larger than average contingent at the two biggest HPC events of the year.

One thing AMD still has going for it is the good will it has built up in the high performance computing community over the past few years due to the superior attributes of its Opteron processor. No doubt some of that good will has been eroded due to missteps in 2007, especially the failed Barcelona launch that left HPC OEMs looking longingly at Intel parts. Overall though, since 2005, better memory performance and scalability allowed Opterons to shine in the HPC realm when compared to their Xeon counterparts. Since most supercomputers, especially the top 10 variety, get planned two to four years in advance, AMD will still be able to ride this momentum at least until the end of the decade.

With the exception of SGI, every major HPC system vendor uses AMD chips today. Most vendors offer both Intel- and AMD-based systems, although Cray is AMD-only, at least until 2010. And despite Sun Microsystem’s embrace of Intel in 2007, the largest machines, like the TSUBAME supercomputer in Japan and the 500 teraflop system just deployed at TACC, are Opteron-based.

As I’ve written about before, though, the Opteron’s HPC advantage is about a year away from disappearing. In truth, the latest 45nm Xeons with the souped up front-side bus are already faster than the current 65nm Opterons on a range of technical computing applications. With Intel’s upcoming Nehalem processor family, scheduled to start rolling out in late 2008/early 2009, the company will be adding integrated memory controllers and QuickPath, a HyperTransport-like point-to-point interconnect that will replace Intel’s antiquated front-side bus. At that point, you have to ask how AMD intends to compete at the high end.

In the short-term, AMD expects Nehalem to initially be delivered in the 2P flavor for dual-socket systems. In that configuration, Intel will match up very well against the 2P Opterons. If AMD is still a process generation behind its rival, as it is now, Intel will almost certainly have the performance edge. In 2009, AMD plans to implement HyperTransport 3.0 on its processors, which, according to Rich, will allow them to retain a memory bandwidth advantage, at least in 4-socket servers.

“Then we’ll be in a situation that we’re actually already in,” says Rich. “Some applications will perform better on Intel [processors] and some will perform better on ours. People are really going to have to look at their applications to see where they get better performance. It’s going to be a neck and neck race.”

Although most people point to the Opteron as the area where AMD lost the high ground this year, the company’s ATI-derived GPU computing products for HPC got blind-sided by NVIDIA when it rolled out the Tesla product line and the associated CUDA GPU programming environment. AMD’s 64-bit FireStream stream processor was announced in November 2007 and is expected to be go to the market sometime this year. Rich says the FireStream hardware is a very competitive product, but admits they have been behind on the software front. According to him, though, they’re catching up quickly. For high-level development, AMD has developed Brook+, a tool that provides C extensions for stream computing on GPU hardware, and which is based on the Brook project at Stanford. Rich notes there are similarities with NVIDIA’s CUDA environment, but stopped short of saying that Brook+ would be CUDA compatible. When announced at the end of last year, AMD said the FireStream product would launch in Q1 of 2008, which is the same time frame targeted by NVIDIA for its 64-bit Tesla offering.

Going head-to-head against Intel and NVIDIA with CPU and GPU offerings, respectively, is a conservative strategy and maybe a problematic one, considering the economies of scale in play in the chip design and manufacturing business. But because AMD now owns both kinds of architectures, it should be able to use that advantage against its much larger rivals. That was certainly part of the rationale behind the ATI-AMD merger in 2006. If they ever intend to extract some synergy out of the CPU-GPU, now would be a good time to take the pole position. AMD’s CPU-GPU Fusion hybrid processor, now referred to as an accelerated processing unit (APU), is due out in the second half of 2009. But by this date, Intel may have its own version of a CPU-GPU processor.

Layered on top of the CPU, GPU, and APU product set is AMD’s Accelerated Computing strategy, which is intended to create a software stack for a heterogeneous computing environment. This will include elements such as drivers, APIs, compilers, and OS support. According to Rich, a lot of work has been going into this behind the scenes and AMD should be ready to elaborate on the strategy this spring, but it’s clear they intend to build on top of Torrenza, the first phase of AMD’s accelerated computing platform.

The big picture with accelerated computing is to create a system environment where different species of processors (CPUs, GPUs, FPGAs, and custom ASICs) can be brought together to provide a rich set of computational engines for application software. The acceleration effect is the result of mapping the different software components onto the most appropriate hardware. The software stack running on top of the hardware will provide a standard and, presumably, high-level way to access the underlying processors. More than anything, this sounds like a mainstream version of Cray’s Adaptive Computing vision, the supercomputer maker’s strategy to take HPC to the next level.

If AMD manages to deliver this new paradigm to the mass market, the company will have once again succeeded in making an end-run around its larger rivals. It wouldn’t be the first time.

—–

As always, comments about HPCwire are welcomed and encouraged. Write to me, Michael Feldman, at editor@hpcwire.com.

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