Image processing appears in numerous application domains, including video transcoding, medicine, mapping, inspection, photography, and document processing. Due to the proliferation of image sensors and high-resolution displays, digital image processing is a staple on everything from cell phones to supercomputers.

However, whatever the hardware platform, the performance of image processing applications can significantly affect their usefulness and the user experience. Multi-core processors and many-core accelerators offer many new opportunities for radically improved performance in the area of digital imaging. Achieving maximum performance on these processors, however, requires a parallel implementation and, due to the large amount of data processed, efficient use of the memory system. In this article, we will consider a range of digital image processing applications and will discuss how they can be efficiently implemented on multi-core processors using a pattern-based approach and the use of a development platform that can translate these patterns directly into machine language.

High performance image processing has been a key enabler for many new products. Computation can be used to overcome noise limitations for handheld cameras (enabling the use of a less expensive sensor), can be used to achieve high compression rates (enabling video to be used over low bandwidth network connections), or can be used to extract metadata from images (enabling them to be indexed in a database). In fact, the use of image processing has been used to correct for diffraction effects in optical lithography masks, enabling the electronic industry itself to produce the extremely dense multi-core processors we are addressing here!

Image processing is also extremely important in the consumer space. In particular, image processing can be used to dramatically extend the capabilities of handheld photography. It can be used to reduce noise, allowing low-light photography; to create panoramas by registering and blending multiple images; to create high-dynamic range images by combining multiple exposures; to automatically focus on faces and to compensate for vibration; and to dramatically improve shots taken using natural lighting by combining them with more detailed images taken with a flash.

The keys to performance are the exploitation of parallelism and data locality. Fortunately, many image processing algorithms are based on a relatively small number of patterns of computation. Each of these patterns has a certain amount of latent parallelism and data locality. Since different processors have different mechanisms for expressing parallelism and data locality, different optimizations may be required on different systems. However, a software development platform can still exploit these patterns if image processing algorithms are expressed in terms of them. Such an approach can significantly reduce implementation complexity and costs.

Image processing algorithms can basically be classified into the map, stencil, spectral, and segmented computational patterns:

• The map pattern applies an independent computation to every pixel of an image, or more generally, an array of elements. Simple examples include color space conversions, contrast and brightness adjustments, and hue correction.
• The stencil pattern computes, for every neighborhood in the input found using a stencil of offset values, a single output value. Examples of algorithms that use this pattern include convolution (which can be used to implement blurring and sharpening), noise reduction filters such as bilateral filters (which unlike convolution, may be nonlinear), explicit partial differential equation solvers, and image resizing.
• The spectral pattern applies some computation to a sequence of values at different “strides” or frequencies in the image. Examples include the FFT (Fast Fourier Transform), the DCT (Discrete Cosine Transform), and bitonic sort. The FFT is used to convert a convolution operation to and from a map operation, which is more efficient for large convolutions. The DCT is used in compression, for example in JPEG and MPEG codecs. A sort is useful for building and managing data structures.
• The segmented pattern breaks the image into irregular regions of different sizes and applies a separate computation to each region. For example, an image might be separated into connected regions of different colors and the area of each blob calculated, or a set of chain codes connecting the edges around each region might be computed. This pattern supports irregular computation and data structures.

It should be noted that these are patterns, not library functions. Patterns are more about how data is accessed and managed and how tasks are applied to that data rather than about particular computations. Many possible computations can be implemented under every pattern, and image processing applications often involve a complex composition of these patterns.

The number of patterns required is surprisingly small. However, even the simplest pattern does require some processor-specific optimizations for maximum performance.  Consider the map pattern. Even this “trivial” parallel pattern can benefit from blocking up operations and using these blocks to perform loop unrolling and vectorization, as well as the use of cache management strategies such as alignment, prefetching, and double buffering. Since operations may be composed, the per-element operation used in the map pattern may become arbitrarily complex, and in particular may not take a constant amount of time to execute. In this case load balancing is also required.

Other patterns require more complex optimizations. For example, in order to implement the stencil pattern effectively, data read into the processor’s on-chip memory for one stencil’s neighborhood should be reused, whenever possible, in other computations for which it is needed. One useful implementation strategy on a serial machine is a sliding window. On a parallel machine, tiled sliding windows can be used, but their geometry should be chosen to avoid false sharing and other negative cache effects while achieving load balancing and good alignment. When multiple opportunities for exploiting parallelism are available in the hardware, implementing high-performance versions of even these seemingly simple patterns using traditional low-level approaches can result in very complex and error-prone code.

One approach is to use a framework that embodies these patterns and allows their composition. While a framework makes it easy to write sophisticated applications quickly, it does not provide the ultimate in performance since typically only limited amounts of low-level optimization can be performed automatically. This is because a framework is “on top” of machine language implemented using a traditional compiled serial language. The framework does not have access to the finer grained versions of parallelism that only a system directly manipulating machine language can target. Conversely, with a framework the compiler sees only the serial code used to implement the framework and not the parallelism intrinsic to the pattern. A framework can also add significant amounts of overhead, depending on its implementation.

An alternative approach allows the developer to express their computations as compositions of patterns, but uses a development platform to generate machine language directly from these patterns without going through an intermediate serial language. The patterns express the intent of the programmer and provide the platform with sufficient parallelism and data locality to use as a basis for optimization. However, patterns do not over-specify the order of operations. This leaves the platform free to map the desired computations onto the wide variety of implementation mechanisms available across different processors and even within one processor. From this point of view, targeting multiple cores is just another parallelism mechanism, and it is not necessary to burden the developer with the details.

Working at this level not only makes the code more portable, it also makes it easier to develop and maintain. In fact, the code can be higher performing and more stable than manually written low-level code, since there are fewer details to get wrong. For example, in the RapidMind platform, computational patterns that would result in race conditions are excluded by default. This makes synchronization bugs impossible to specify, so code is correct by construction, at least from a synchronization point of view.

Of course one can argue that this model is restrictive, that some particular algorithm cannot be implemented with a particular set of patterns. In fact this is not true: it has been shown that a sufficiently rich set of patterns is in fact universal, and that the number of patterns needed to achieve universality is quite low. This is true even if we insist on implementations that are as efficient as any other implementation. Traditional serial computing has simply used a fairly limited set of patterns based only on sequence, alternation, iteration and/or recursion, as well as random access to data. For parallel computing, and for image processing in particular, other sets of patterns in addition to these are useful, and in particular patterns that also include some notion of coherent or managed data access are important. Use of these parallel patterns can lead to clearer code as well as greater opportunities for performance, as long as a development platform is used that can properly exploit them. As noted at the outset of this article, high-performance image processing is a key enabler for a wide range of applications. Organizations seeking to fully harness the power of multi-core processors and image processing, while accelerating their development timelines and reducing costs, should seriously consider this approach.

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About the Authors

Dr. Michael McCool is an Associate Professor at the University of Waterloo and co-founder and Chief Scientist of RapidMind. He continues to perform research within the Computer Graphics Lab at the University of Waterloo. Professor McCool has a diverse set of published papers, and his research interests include high-quality real-time rendering, global and local illumination, hardware algorithms, parallel computing, reconfigurable computing, interval and Monte Carlo methods and applications, end-user programming and metaprogramming, image and signal processing, and sampling. Michael has degrees in Computer Engineering and Computer Science.

Stefanus Du Toit is founder and Chief Architect of RapidMind. He has led the development and evolution of the RapidMind platform since 2003. Stefanus has extensive experience in the areas of graphics, GPGPU, systems programming, and compilers. Stefanus holds a Bachelors of Mathematics degree in Computer Science.