Here’s a collection of highlights, selected totally subjectively, from this week’s HPC news stream as reported at insideHPC.com and HPCwire.
>>10 words and a link
Intel starts strategic peaks at big HPC vision;
Sun wins $44M DARPA contract for silicon photonics research;
HPTi Wins $4M NOAA GFDL Contract;
Lockheed Martin wins $344M centralized management contract for HPCMP;
DOE/DOT team up on new HPC center for transportation research;
IMSL Numerical Library for Fortran comes to Windows;
Marathon introduces software to protect VM from physical failures;
>>Yahoo! delivers free HPC to Indian universities
You’ve probably read about this deal already, but in case you haven’t, you might be interested to learn that Yahoo! has teamed up with Computational Research Laboratories to give free access to HPC cycles for researchers in India working on large scale computing around Hadoop. Hadoop is the open source implementation of Google’s MapReduce.
It’s a big system: 14,400 processors with a 180 TFLOPS peak. And Yahoo! doesn’t plan to stop in India:
Yahoo aims to get more developers to research and develop applications that can scale around Hadoop, said Rajeev Rastogi, vice president and head of Yahoo Labs Bangalore, in an interview on Tuesday. To this end, the company plans to replicate the model it is trying in India in some other countries as well.
There are articles all over the place, but this one (http://www.infoworld.com/article/08/03/25/Yahoo-offers-free-supercomputing-to-Hadoop-developers_1.html) at InfoWorld is short, sweet, and to the point.
>>Intel’s new low power server chips
This week Intel announced two new lower power chips for use in servers and workstations. The new quad core L5400 series uses a 45 nm process and runs at just 50 watts at either 2.33 GHz or 2.5 GHz. These chips replace the previous 65 nm low power Clovertown gear. From the release (http://www.intel.com/pressroom/archive/releases/20080325comp.htm?iid=pr1_releasepri_20080325m):
Benefiting companies with power-constrained, high-compute density environments, the Quad-Core Intel Xeon L5400 processors are as much as 25 percent faster and have a 50 percent larger cache size than Intel’s previous-generation, low-voltage Quad-Core Intel Xeon processors, while at the same time maintaining the low 50-watt thermal envelope. The quad-core L5420 and L5410 processors run at 2.50 GHz and 2.33 GHz, respectively, and feature a unique 12 megabytes (MB) of on-die cache and dedicated 1333 MHz front side buses (FSB).
You can find the L5400 series in a variety of vendor gear, including Asus, Dell, Fujitsu, HP, IBM, Verari and others.
Next quarter Intel expects to lower the power bar even further:
Next quarter, Intel will also begin shipping a new dual-core low-voltage processor that will boast a 40-watt rating and clock speed of 3 GHz, with a 6 MB cache size and a 1333 MHz FSB.
>>City College of New York Using SGI for Traffic Sims
The recently unveiled Universal Transportation Model Simulation Center (UTMSC) at City College of New York has chosen an SGI Altix 4700 high performance computing platform. The machine is destined to run traffic simulators and models for traffic planing, signal optimization and network flow. The 40 processor [Itanium2] will assist in developing models to meet the escalating traffic demands or to establish an effective transportation plan in the event of a disaster.
“Traffic simulation is a very data intensive application,” said Dr. Neville Parker, director of UTMSC, CUNY Institute for Transportation Systems. “The 40 core SGI Altix 4700 platform provides the low latency, scalability and expansive shared memory we need to allow multiple users to run our large-scale transportation models simultaneously.”
The main traffic simulation software application, VISTA, allows researchers, public agencies and private consulting firms to generate large scale models for a number of different scenarios. These models include evaluating the impact of various infrastructure changes and assessing traffic control measures such as signal timing, speed limit changes, and HOV lanes.
Read the full article at http://sev.prnewswire.com/computer-electronics/20080326/AQW03326032008-1.html.