As most high performance computing users are aware, the rise of multicore-based systems has spawned a number of problems. One of the most fundamental of them is the memory bandwidth bottleneck. As more cores are added to the die, there is proportionally less cache to serve each one, resulting in more accesses to slower main memory. To state it simply, computational power is growing faster than memory performance.

The result is that additional processor cores often spend an inordinate amount of time waiting for data to crunch on, thereby wasting the computational power of the multiple cores. Avoiding unnecessary main memory accesses and keeping cache usage optimized is critically important for performance since a processor core can execute hundreds of instructions in the time it takes to access a memory location. Chip designers have compensated to some extent by constructing processors with larger multi-level caches and hardware prefetching. Unfortunately, the potential of such hardware is only realized if the software can exploit it. To date, composing high-level source code that is well-tuned for these cache-dependent architectures has been a major challenge.

Help may be on the way. Acumem, a two-year-old Swedish company that operated in semi-stealth mode until recently, has released a new performance analyzer specifically developed to help programmers achieve good cache utilization and optimize memory access. The technology is based on work done by Erik Hagersten, the CTO of Acumem, and his research team at Uppsala University.

Called SlowSpotter, the Acumem tool illuminates “slow spots” in an application and points the developer to the offending source code or data structures. Up until now, performance analysis tools relied on hardware counters, and typically only revealed where a lot of cache misses were occurring — so called hot spots. It was left up to the programmer to figure out what to do with that information. SlowSpotter actually finds the problematic source and suggests ways to tweak the code to optimize performance. Better yet, it ranks the problem areas in the code according to their potential for performance improvement.

For example, a fairly common problem in programs is thrashing the cache by accessing multi-dimensional arrays inefficiently. If a nested loop is traversing a two-dimensional matrix in column order (row order for Fortran), the traversal will touch one element in too many cache lines before returning to touch more data. By that time, the cache line may have been evicted. Usually, by just switching the loop traversal around, cache use is optimized.

Beside loop nesting problems, SlowSpotter will also find code with poor cache line utilization (a section of the code is using high amounts of bandwidth due to inefficient data packing); loop fusion opportunities (two loops are using the same data and may be fused to improve cache usage); irregular access patterns (an irregular data access pattern causing inefficient cache usage); and hot spots (a section of the code with a high amount of cache misses, but with no obvious fix).

Hagersten, a self-proclaimed “cache nerd,” realized that most programmers aren’t equipped to optimize code performance on the modern microprocessor. He says SlowSpotter results are presented in such as way so the average (i.e., non-parallel thinking) programmer can understand the problems and make the necessary code changes.

While the tool is aimed at the least common dominator, experts can benefit too. According to Hagersten, some of the most extreme performance people he knows have used the tool to uncover performance problems in code that they thought they had tuned. One customer — an ISV — bought a site license for the entire company. Even though the ISV had three or four people that focused on performance, they wanted everybody to have the tool to change their mindset about the importance of optimization.

Because of the ubiquity of multicore, the potential audience for SlowSpotter is huge. But the company intends to initially focus on the HPC market, where memory bandwidth limitations are most acute and the users have a better understanding of the problem. And HPC users will be the ones to see the most dramatic speed-ups. “They are getting on the multicore train much faster,” notes Hagersten.

Acumem tested SlowSpotter on a SPEC application benchmark (470.lbm) that uses the “Lattice Boltzmann Method” (LBM) to simulate incompressible fluids in 3D. Using an Intel Core2 Quad Q6600 2.4GHz (1066MHz FSB and equipped with 800 MHz DDR2 RAM), the original code ran only 1.5 times faster on all four cores compared to a single core. After the SlowSpotter optimization was applied, the code ran 3.2 times faster. Even for single core execution, optimization produced a 1.6X speedup.

SlowSpotter runs on x86 processors, but is compiler agnostic, operating on the application binaries themselves. The way the tool works is by attaching to a running application, at which point it collects thread and memory data. The tool then takes a “fingerprint” of the application by sampling data access behavior at between 20,000 and 50,000 code locations, which generates a multi-megabyte data file. The fingerprint can then be used to analyze the behavior of the application. Since the analysis is source code-centric, the collected data can be used to model a system other than the one the application was originally executed on.

“The information you collect here is architecturally independent,” explains Hagersten. “It doesn’t matter what the cache size, cache line size and TLB size are. What we are measuring here in the fingerprint is the locality goodness of the binary.”

Acumem is offering SlowSpotter via its Web site and has wisely provided a free trial version, called SpotLite, so that potential customers can give the technology a spin. Hagersten says the company currently has about a 100 beta users, including national labs, financial institutions, animation studios, and ISVs. Acumen is also part of HP’s Multicore Optimizations program, and has additional partnerships with both AMD and Sun Microsystems.

Josh Simons, distinguished engineer at Sun Microsystems, believes the Acumem offering is well positioned, given that HPC growth is mostly at the lower end of the market — an area where multicore programming skills are limited. He says that any tool that lowers the barrier to taking advantage of these processors is going to be critical. And once you get into the broader market, that kind of expertise becomes extremely rare. “It’s clear that this focus on memory bandwidth is going to go far beyond HPC,” he says. “To me that’s huge.”