A lot of industry people in the know are predicting that Moore’s Law will come to an end sometime in the next decade. Starting with the current leading-edge 45nm process technology, chipmakers are looking to deliver three more shrinks until silicon-based transistors run up against quantum mechanical effects. Most vendors have plans in place for 32nm and 22nm processors using UV lithography. The next stop is 16nm, but the general consensus is that it will have to be implemented with something other than CMOS-based material — perhaps SiGe or graphene. At 9 or 10 nanometers, quantum tunneling starts to become a real problem, so even more futuristic approaches, like molecular electronics or spintronics, will be required.

There’s no guarantee that the development of these more advanced technologies will obey a Moore’s Law timeline, which was based on the progression of two-dimensional semiconductors. So what’s a chipmaker to do? Bernard Meyerson, IBM Fellow and chief technologist for the company’s systems and technology group, thinks 3-D chip stacking will be the way to go. In a recent article in Semiconductor International, Meyerson argues that in the future 2D scaling will break down for silicon technologies.

“Density will improve through 3-D stacking and the application of optical technology,” he said. “Some version of Moore’s Law will be followed. We didn’t foresee it would require a vertical perspective. There will be a tremendous focus on 3-D system architecture — logic, cache, memory, I/O subsystem — all optimized and integrated in a single stack.”

Meyerson believes the 3-D route will be the path most chipmakers will pursue, rather than relying on the development of higher risk nanoelectronics. And it actually may help processor architects simplify the designs. In 2D, the microarchitecture had to integrate all the logic, cache and I/O on the same level. Adding an extra dimension means the architects will have a lot more flexibility. In a Forbes interview last month, Myerson talked about some of the possibilities:

There are still many tricks that we can play. When you start looking at the ability to put 10 or 20 chips in a stack, you can re-architect the entire system. The stack is your system. But you can re-architect the stack to be much more effective. Companies brag about the size of the cache. What if the cache was unlimited? What if you could put an entire plane of super high-density memory right above a plane of logic? What if you could put multiple cores on a single level and then reconfigure the wiring between that chip and the one above it?

Optical communication between the chips will be key since it delivers lots more data than electronics with much less power. Using conventional electronics to link stacks of chips would mean communication would be subject to resistive capacitive delay and would probably not be practical. Going optical has the additional advantage of seamless communication across an optical backplane.

Of course 3-D chip stacking has not been perfected, nor have chip-level optical interconnects. But these are manufacturing problems, which should eventually yield to engineering. Nanoelectronic-based transistors, on the other hand, are still in the basic research stage and may remain there for the foreseeable future. In any case, computing will likely continue to shrink into smaller spaces, even after Moore’s Law itself yields to the laws of physics.