HyperTransport Stays Ahead of the Curve

By Michael Feldman

August 14, 2008

The HyperTransport technology was introduced in 2001 to provide a general purpose, low-latency, high bandwidth system interconnect that was designed to overcome some of the shortcomings of shared bus technologies and proprietary interconnects. The HyperTransport Consortium controls the technology specification and drives its development. This non-profit organization maintains HyperTransport as an open standard, available to any vendor willing to become a Consortium member. Since its introduction, the technology has attracted system designers in high performance computing and other IT segments where performance and scalability are of paramount importance.

In the multiprocessor world of supercomputing, the system interconnect is as important as the processors themselves. Since commodity processors are now being used in the majority of these machines, the proprietary interconnect fabric is becoming one of the more expensive elements of the system. Of course, this is not just the case for supercomputers. Servers, network appliances and even desktop systems have a great need for fast data transfers. But in the high-performance realm, the need for a low-latency, high bandwidth interconnects is especially crucial.

“Even though it's used in very high-end systems, it's also used in very low-end PC, with an eye to reducing the cost,” said David Rich, president of the HyperTransport Consortium. “So the technology has to be very accepting of the quality of the signal integrity that's on the board. We can't specify a very expensive board manufacturing regimen to get the speed.”

Originally just used for processor-to-processor connections, HyperTransport now provides processor-to-peripheral links as well. With last month's introduction of the HyperTransport 3.0 specification, it can now be used for system-to-system connections. More about that later.

One of the most prominent uses of HyperTransport in the HPC domain are in AMD's Opteron processors which are the basis of many high performance clusters and supercomputers — for example, Cray's Red Storm system. In fact, the popularity of the Opteron throughout the server and high performance segments has helped to drive adoption of the HyperTransport technology throughout the IT industry. As the number of devices that want to talk directly to Opterons grow, so grows the demand for HyperTransport. The recently announced DRC FPGA cooprocessor also takes advantage of the HyperTransport technology by plugging directly into AMD Opteron sockets.

Another example of this technology in high performance computing is PathScale's InfiniPath adapter. Here HyperTransport has been used to achieve extremely low-latency cluster interconnects (1.29 microseconds MPI latency).

According to Mario Cavalli, general manager for the HyperTransport Consortium, one of the unique strengths of HyperTransport is its processor native interface. This provides simple, but highly efficient chip-to-chip communication that scales with the number of HyperTransport-enabled processors. Unlike front-side bus architectures, which require adapters to connect to standard buses like PCI or AGP, the HyperTransport interconnect is simpler and more flexible.

The technology supports a variable bus width, from 2 to 32 bits; and buses of various widths can be mixed together within a single application. Also, the implementation may choose the clock speed in 200MHz steps, up to a maximum of 2.6GHz in the 3.0 specification. This type of flexibility enables the system designer to specify a hardware implementation that closely matches the desired performance.

Since it was introduced in 2001, the HyperTransport specification has been enhanced in order to increase both speed and functionality. As both CPUs and networks get faster — and as more cores get added to the chip — the need to increase the processor's bandwidth grows according. In addition, as computing systems get more specialized and more complex, there is a corresponding need to have more design flexibility.

The new HyperTransport 3.0 specification was designed to create some headroom in both the bandwidth and flexibility. Specifically, the maximum aggregate bandwidth for the 3.0 specification is 41.6 GB/second, assuming a 32-bit bus at 2.6GHz. This is almost double the maximum bandwidth of the 2.0 specification and more than five times the highest bandwidth currently implemented in an actual product. Fortunately, the new spec maintains the same hardware pinouts; the heavy lifting is done by upgrading the physical signaling methods.

Although no systems even approach this 3.0 bandwidth today, some vendors, like AMD, are undoubtedly making plans for faster implementations. David Rich says that we can expect to see 16-bit HyperTransport implementations make use of 80 to 90 percent of that bandwidth in the not-too-distant future.

The new specification also has some features that are targeted specifically for flexibility. This includes power management, which is supported by dynamically changing the bit widths and clock frequency. The idea is that you use a lot less power at 200MHz and 4 bits than you would at 2.6GHz on 16 bits. So, for example, during those times when a server is doing calculations that are all in cache or memory, and I/O traffic is dead, the HyperTransport link could power down significantly.

There is also an un-ganging feature that allows a connection to be split from one 16-bit link to two 8-bit links. This could naturally be applied to SMP applications. Other applications are possible as well, especially in multiprocessor implementations, where more HyperTransport links are needed for processor-to-processor as well as and processor-to-I/O connections.

It should be noted that the reduction of link width from 16 to 8 bits does not constitute a drawback in processor-to-processor subsystems, where bandwidth is not as important as it is in I/O processing, but latency definitely is. In this case, 8-bit links latency can be just as low as with 16-bit links. An example of this could be the new 8-bit and 16-bit versions of recently introduced coprocessing platforms, such as DRC's FPGA, mentioned earlier.

Perhaps the biggest new feature of HyperTransport 3.0 is the addition of the AC operating mode. This optional mode supports longer runs to blackplanes, cables and other systems. HyperTransport designers decided to add this feature as they saw the increased need for off-board connectivity in larger more complex systems, where memory and processors often scale beyond the board.

“We've made it much easier for people to design systems that have multiple boards and have chassis-to-chassis connections, so that they can physically construct the system as they want,” said Rich. “At full speed we're looking at about a meter. You can back off the speed and go substantially further. But we're not looking at this as even a 'room-area network.' It's basically for the interconnect within a system; but now those systems can get fairly large and complex. HyperTransport is scaling up with that size and complexity. So with HyperTransport 3.0, we can provide yet more headroom for the future in terms of what can be implemented. This puts us comfortably ahead of the requirements of the silicon products over the next couple of years.”

Subscribe to HPCwire's Weekly Update!

Be the most informed person in the room! Stay ahead of the tech trends with industy updates delivered to you every week!

At SC19: What Is UrgentHPC and Why Is It Needed?

November 14, 2019

The UrgentHPC workshop, taking place Sunday (Nov. 17) at SC19, is focused on using HPC and real-time data for urgent decision making in response to disasters such as wildfires, flooding, health emergencies, and accidents. We chat with organizer Nick Brown, research fellow at EPCC, University of Edinburgh, to learn more. Read more…

By Tiffany Trader

China’s Tencent Server Design Will Use AMD Rome

November 13, 2019

Tencent, the Chinese cloud giant, said it would use AMD’s newest Epyc processor in its internally-designed server. The design win adds further momentum to AMD’s bid to erode rival Intel Corp.’s dominance of the glo Read more…

By George Leopold

NCSA Industry Conference Recap – Part 1

November 13, 2019

Industry Program Director Brendan McGinty welcomed guests to the annual National Center for Supercomputing Applications (NCSA) Industry Conference, October 8-10, on the University of Illinois campus in Urbana (UIUC). One hundred seventy from 40 organizations attended the invitation-only, two-day event. Read more…

By Elizabeth Leake, STEM-Trek

Cray, Fujitsu Both Bringing Fujitsu A64FX-based Supercomputers to Market in 2020

November 12, 2019

The number of top-tier HPC systems makers has shrunk due to a steady march of M&A activity, but there is increased diversity and choice of processing components with Intel Xeon, AMD Epyc, IBM Power, and Arm server ch Read more…

By Tiffany Trader

Intel AI Summit: New ‘Keem Bay’ Edge VPU, AI Product Roadmap

November 12, 2019

At its AI Summit today in San Francisco, Intel touted a raft of AI training and inference hardware for deployments ranging from cloud to edge and designed to support organizations at various points of their AI journeys. The company revealed its Movidius Myriad Vision Processing Unit (VPU)... Read more…

By Doug Black

AWS Solution Channel

Making High Performance Computing Affordable and Accessible for Small and Medium Businesses with HPC on AWS

High performance computing (HPC) brings a powerful set of tools to a broad range of industries, helping to drive innovation and boost revenue in finance, genomics, oil and gas extraction, and other fields. Read more…

IBM Accelerated Insights

Help HPC Work Smarter and Accelerate Time to Insight

 

[Attend the IBM LSF & HPC User Group Meeting at SC19 in Denver on November 19]

To recklessly misquote Jane Austen, it is a truth, universally acknowledged, that a company in possession of a highly complex problem must be in want of a massive technical computing cluster. Read more…

SIA Recognizes Robert Dennard with 2019 Noyce Award

November 12, 2019

If you don’t know what Dennard Scaling is, the chances are strong you don’t labor in electronics. Robert Dennard, longtime IBM researcher, inventor of the DRAM and the fellow for whom Dennard Scaling was named, is th Read more…

By John Russell

Cray, Fujitsu Both Bringing Fujitsu A64FX-based Supercomputers to Market in 2020

November 12, 2019

The number of top-tier HPC systems makers has shrunk due to a steady march of M&A activity, but there is increased diversity and choice of processing compon Read more…

By Tiffany Trader

Intel AI Summit: New ‘Keem Bay’ Edge VPU, AI Product Roadmap

November 12, 2019

At its AI Summit today in San Francisco, Intel touted a raft of AI training and inference hardware for deployments ranging from cloud to edge and designed to support organizations at various points of their AI journeys. The company revealed its Movidius Myriad Vision Processing Unit (VPU)... Read more…

By Doug Black

IBM Adds Support for Ion Trap Quantum Technology to Qiskit

November 11, 2019

After years of percolating in the shadow of quantum computing research based on superconducting semiconductors – think IBM, Rigetti, Google, and D-Wave (quant Read more…

By John Russell

Tackling HPC’s Memory and I/O Bottlenecks with On-Node, Non-Volatile RAM

November 8, 2019

On-node, non-volatile memory (NVRAM) is a game-changing technology that can remove many I/O and memory bottlenecks and provide a key enabler for exascale. That’s the conclusion drawn by the scientists and researchers of Europe’s NEXTGenIO project, an initiative funded by the European Commission’s Horizon 2020 program to explore this new... Read more…

By Jan Rowell

MLPerf Releases First Inference Benchmark Results; Nvidia Touts its Showing

November 6, 2019

MLPerf.org, the young AI-benchmarking consortium, today issued the first round of results for its inference test suite. Among organizations with submissions wer Read more…

By John Russell

Azure Cloud First with AMD Epyc Rome Processors

November 6, 2019

At Ignite 2019 this week, Microsoft's Azure cloud team and AMD announced an expansion of their partnership that began in 2017 when Azure debuted Epyc-backed instances for storage workloads. The fourth-generation Azure D-series and E-series virtual machines previewed at the Rome launch in August are now generally available. Read more…

By Tiffany Trader

Nvidia Launches Credit Card-Sized 21 TOPS Jetson System for Edge Devices

November 6, 2019

Nvidia has launched a new addition to its Jetson product line: a credit card-sized (70x45mm) form factor delivering up to 21 trillion operations/second (TOPS) o Read more…

By Doug Black

In Memoriam: Steve Tuecke, Globus Co-founder

November 4, 2019

HPCwire is deeply saddened to report that Steve Tuecke, longtime scientist at Argonne National Lab and University of Chicago, has passed away at age 52. Tuecke Read more…

By Tiffany Trader

Supercomputer-Powered AI Tackles a Key Fusion Energy Challenge

August 7, 2019

Fusion energy is the Holy Grail of the energy world: low-radioactivity, low-waste, zero-carbon, high-output nuclear power that can run on hydrogen or lithium. T Read more…

By Oliver Peckham

Using AI to Solve One of the Most Prevailing Problems in CFD

October 17, 2019

How can artificial intelligence (AI) and high-performance computing (HPC) solve mesh generation, one of the most commonly referenced problems in computational engineering? A new study has set out to answer this question and create an industry-first AI-mesh application... Read more…

By James Sharpe

Cray Wins NNSA-Livermore ‘El Capitan’ Exascale Contract

August 13, 2019

Cray has won the bid to build the first exascale supercomputer for the National Nuclear Security Administration (NNSA) and Lawrence Livermore National Laborator Read more…

By Tiffany Trader

DARPA Looks to Propel Parallelism

September 4, 2019

As Moore’s law runs out of steam, new programming approaches are being pursued with the goal of greater hardware performance with less coding. The Defense Advanced Projects Research Agency is launching a new programming effort aimed at leveraging the benefits of massive distributed parallelism with less sweat. Read more…

By George Leopold

AMD Launches Epyc Rome, First 7nm CPU

August 8, 2019

From a gala event at the Palace of Fine Arts in San Francisco yesterday (Aug. 7), AMD launched its second-generation Epyc Rome x86 chips, based on its 7nm proce Read more…

By Tiffany Trader

D-Wave’s Path to 5000 Qubits; Google’s Quantum Supremacy Claim

September 24, 2019

On the heels of IBM’s quantum news last week come two more quantum items. D-Wave Systems today announced the name of its forthcoming 5000-qubit system, Advantage (yes the name choice isn’t serendipity), at its user conference being held this week in Newport, RI. Read more…

By John Russell

Ayar Labs to Demo Photonics Chiplet in FPGA Package at Hot Chips

August 19, 2019

Silicon startup Ayar Labs continues to gain momentum with its DARPA-backed optical chiplet technology that puts advanced electronics and optics on the same chip Read more…

By Tiffany Trader

Crystal Ball Gazing: IBM’s Vision for the Future of Computing

October 14, 2019

Dario Gil, IBM’s relatively new director of research, painted a intriguing portrait of the future of computing along with a rough idea of how IBM thinks we’ Read more…

By John Russell

Leading Solution Providers

ISC 2019 Virtual Booth Video Tour

CRAY
CRAY
DDN
DDN
DELL EMC
DELL EMC
GOOGLE
GOOGLE
ONE STOP SYSTEMS
ONE STOP SYSTEMS
PANASAS
PANASAS
VERNE GLOBAL
VERNE GLOBAL

Intel Confirms Retreat on Omni-Path

August 1, 2019

Intel Corp.’s plans to make a big splash in the network fabric market for linking HPC and other workloads has apparently belly-flopped. The chipmaker confirmed to us the outlines of an earlier report by the website CRN that it has jettisoned plans for a second-generation version of its Omni-Path interconnect... Read more…

By Staff report

Kubernetes, Containers and HPC

September 19, 2019

Software containers and Kubernetes are important tools for building, deploying, running and managing modern enterprise applications at scale and delivering enterprise software faster and more reliably to the end user — while using resources more efficiently and reducing costs. Read more…

By Daniel Gruber, Burak Yenier and Wolfgang Gentzsch, UberCloud

Dell Ramps Up HPC Testing of AMD Rome Processors

October 21, 2019

Dell Technologies is wading deeper into the AMD-based systems market with a growing evaluation program for the latest Epyc (Rome) microprocessors from AMD. In a Read more…

By John Russell

Rise of NIH’s Biowulf Mirrors the Rise of Computational Biology

July 29, 2019

The story of NIH’s supercomputer Biowulf is fascinating, important, and in many ways representative of the transformation of life sciences and biomedical res Read more…

By John Russell

Xilinx vs. Intel: FPGA Market Leaders Launch Server Accelerator Cards

August 6, 2019

The two FPGA market leaders, Intel and Xilinx, both announced new accelerator cards this week designed to handle specialized, compute-intensive workloads and un Read more…

By Doug Black

When Dense Matrix Representations Beat Sparse

September 9, 2019

In our world filled with unintended consequences, it turns out that saving memory space to help deal with GPU limitations, knowing it introduces performance pen Read more…

By James Reinders

With the Help of HPC, Astronomers Prepare to Deflect a Real Asteroid

September 26, 2019

For years, NASA has been running simulations of asteroid impacts to understand the risks (and likelihoods) of asteroids colliding with Earth. Now, NASA and the European Space Agency (ESA) are preparing for the next, crucial step in planetary defense against asteroid impacts: physically deflecting a real asteroid. Read more…

By Oliver Peckham

Cerebras to Supply DOE with Wafer-Scale AI Supercomputing Technology

September 17, 2019

Cerebras Systems, which debuted its wafer-scale AI silicon at Hot Chips last month, has entered into a multi-year partnership with Argonne National Laboratory and Lawrence Livermore National Laboratory as part of a larger collaboration with the U.S. Department of Energy... Read more…

By Tiffany Trader

  • arrow
  • Click Here for More Headlines
  • arrow
Do NOT follow this link or you will be banned from the site!
Share This