Compilers and More: Parallel Programming Made Easy?

By Michael Wolfe

September 2, 2008

Look at all the current research projects aimed at exactly that: making parallel programming easy!

The NESL language aims to “make parallel programming easy and portable.” More precisely, its goal is to allow programmers “to write parallel code as concisely and clearly as sequential code, while achieving close to peak performance.”

Microsoft’s Parallel Computing Platform team aims to provide a runtime that provides support for parallelism, models, libraries and tools that “make it easy for developers to construct correct, efficient, maintainable and scalable parallel programs.”

The CxC (C by C) language has one-sided communication operations, “which makes parallel programming easy and efficient.”

My alma mater, the University of Illinois, has a new Universal Parallel Computing Research Center, whose goal is simply “Making parallel programming easy.” Marc Snir, the Computer Science Department head, said the goal for this effort is to “make ‘parallel programming’ synonymous with ‘programming’.”

The Parallel Computing Lab at the University of California at Berkeley has adopted the goal to “make it easy to write correct programs that run efficiently on manycore systems, and which scale as the number of cores doubles every two years.”

Intel’s Threaded Building Blocks (TBB) extends C++ for parallelism in an easy to use and efficient manner.

Tim Mattson (Intel) points out that in “our quest to find that perfect language to make parallel programming easy,” we have come up with an alarming array of parallel programming choices: MPI, OpenMP, Ct, HPF, TBB, Erlang, Shmem, Portals, ZPL, BSP, CHARM++, Cilk, Co-array Fortran, PVM, Pthreads, Windows threads, Tstreams, GA, Java, UPC, Titanium, Parlog, NESL, Split-C, and on and on.

Tim and I are colleagues on the OpenMP Language committee, which recently finalized the OpenMP 3.0 standard. OpenMP’s mission is to define a “portable, scalable model that gives shared-memory parallel programmers a simple and flexible interface for developing parallel applications for platforms ranging from the desktop to the supercomputer.” Is simple even easier than easy?

Every time I see someone claiming they’ve come up with a method to make parallel programming easy, I can’t take them seriously. First, “making parallel programming easy” must be harder than “making programming easy,” and I don’t think we’ve reached that first milestone yet. Yes, I can (and do) knock off quick programs to search or compute something simple, but then I can knock off a quick project to build a bridge over the seasonal stream in our backyard, too. I wouldn’t trust that bridge to freeway traffic, and I wouldn’t trust that quick program to solve anyone else’s problem, either.

All this is folly. I agree with Andrew Tanenbaum, quoted at the June 2008 Usenix conference: “Sequential programming is really hard, and parallel programming is a step beyond that.” Yes, programming is really hard. Look at the programming effort it takes to produce a well-supported world-class application. If it were easy, Microsoft wouldn’t need legions of programmers to develop and support its software. If sequential programming were a solved problem, we wouldn’t have the relatively recent introductions of new and successful languages, such as Java, and C#.

Consider any software development project. Typically it begins with discussion of interfaces (with other software, with data, with users), standards (programming language, operating system, formats), and requirements (functionality and performance). Often, a prototype implementation is developed and tested. One of the tests will involve performance, especially at the limits of the expected input. If the performance is satisfactory, no further tuning is necessary. If not, the team will look at alternative implementations, different algorithms, data structures, shortcuts, etc.; one of the schemes will be to use more parallelism.

In fact, the ONLY reason to consider parallelism is for better performance. Parallelism by itself doesn’t deliver any new features or functionality; it may allow you to deliver new functionality because of improved performance, but the parallelism itself didn’t create the functionality. Most of the programs I write don’t need parallelism because they don’t take long enough to matter. Only those with large datasets or lots of computation are even candidates. I’d be wasting my time and my employer’s resources adding complexity to my program in order to use parallelism that I don’t need.

Moreover, parallelism does not equate to performance. The focus needs to be not on parallelism, but on performance, where parallelism is one of the tools to get it.

Time and again we hear advocates claiming that if you just use their compiler, language, library, tool, methodology, etc., they will guarantee good performance now and forevermore. Yet each time around, the methods are limited to the technology of the day. Let’s look at an example algorithm, matrix multiplication:

   for i in 1:n
     for j in 1:n
       for k in 1:n
         c(i,j) = c(i,j) + a(i,k)*b(k,j)

Early compilers were tuned to optimize just such programs. As pipelined functional units were introduced, libraries were written to replace the inner kernel loops, such as STACKLIB and the BLAS; we could write this loop using a DAXPY call:

   for j in 1:n
     for k in 1:n
       daxpy( n, b(k,j), a(1,k), 1, c(1,j), 1 )
       ! equivalent to:
       ! for i in 1:n
       !   c(i,j) = c(i,j) + b(k,j)*a(i,k)

The library routines were rewritten in vector mode in the 1970s. However, it was soon realized that you could achieve even higher vector performance, called supervector performance, if you optimized the inner two loops to take advantage of vector register locality. Thus came the level-2 BLAS, implementing matrix-vector operations. Matrix multiplication turned into a loop around a DGEMV call:

   for j in 1:n
     dgemv( ‘n’, n, n, 1.0, a(1,1), n, b(1,j), n, 1.0, c(1,j), 1 )
     ! equivalent to:
     ! for k in 1:n
     !   for i in 1:n
     !     c(i,j) = 1.0*c(i,j) + 1.0*b(k,j)*a(i,k)

This was sufficient until the microprocessor revolution, where cache behavior dominated the processor performance. We then were given the level-3 BLAS, implementing matrix multiplication in a single call to DGEMM, which could then be appropriately tiled, unrolled, vectorized, and optimized for each machine. Now we’re in the multicore or manycore era, and who knows where it will lead in the next decade or two? Given how well we’ve predicted what the machines of the future will look like, can we design the universal programming model today?

One aspect of computer science is algorithm analysis, studying the computational and memory requirements of an algorithm. We learn how to reverse a linked list in linear time and constant space. We learn about the differences between bubble sort (O(N^3)), quicksort (O(N log N) on average, easily parallelizable) and heapsort (O(N log N) worst case, and my personal favorite). We learn to pay attention to the hidden constants in the big-O notation, since the constant factor can dominate the computation cost for reasonable inputs; thus, O(N^3) is almost always worse than O(N^2), but O(N log N) with a small constant may be better than O(N) with a big constant, for the expected cases.

For instance, in compilers, no one ever uses the linear time algorithm for computing dominators, because the constant factor is too big. We learn that the analysis usually translates directly to the actual performance. And we learn tricks, like hash table lookup, to work around difficult performance problems. None of this depends on the particular programming language or processor; the von Neumann model has served us well.

Algorithm analysis for parallel computing studies parallelism models, such as Bulk Synchronous Parallel (BSP), Communicating Sequential Processes (CSP), Data-Flow, and so on. These models make assumptions about the cost (or lack thereof) for synchronization and communication. Until we have machines that implement these models more closely, we need to take into account the cost of the virtualization as well. It doesn’t matter how efficient an algorithm is in some abstract machine model if the implementation of the abstract model is itself expensive.

The current “parallelism crisis” can only be resolved by three things. First, we need to develop and, more importantly, teach a range of parallel algorithms. When we teach sorting, we take into account in-core vs. out-of-core, the cost of doing a comparison, and the cost of copying the data versus using indices. Different sort algorithms work better with different dataset characteristics. Similarly, we must teach a range of parallel algorithms, so a programmer knows what dataset and system characteristics will affect the performance, and hence the choice of algorithm.

Second, we need to expand algorithm analysis to include different parallelism styles. It’s not enough to focus on just the BSP or SIMD or any other model; we must understand several models and how they map onto the target systems. We’ve become lazy; the sequential von Neumann model has been sufficiently universal that we think we can use a single model to cover all computing. Yes, this sounds like work, and it sounds like we’re going to have to think for a living.

Finally, we need to learn how to analyze and tune actual parallel programs. Sequential performance tuning has largely been reduced to (at most) profiling to find the computationally-intensive region of code, and either choosing a more efficient algorithm, choosing a different set of compiler flags or different compiler, or using a canned library routine. Advanced analysis may consider cache bandwidth and interference or operating system jitter. Parallel performance analysis is subject to many more pitfalls. Threads or processes may be delayed due to synchronization or communication delays; shared cache usage may cause additional interference; NUMA memory accesses may require more careful attention to memory allocation strategies. Program analysis tools can help here.

Stanford’s Computer Science Department Chair, Bill Dally, is quoted as saying “parallel programming is perhaps the largest problem in computer science today and is the major obstacle to the continued scaling of computing performance that has fueled the computing industry, and several related industries, for the last 40 years.” David Patterson, former ACM president and head of the Parallel Computing Laboratory at Cal Berkeley, said that “in order for parallelism to succeed, it has to result in better productivity, efficiency, and accuracy.”

Parallel processing is an obstacle, but then so is sequential processing. Parallel computing can result in better productivity, efficiency, and accuracy in the scientific process overall, but it’s silly to think that it will result in better productivity and efficiency in the programming process itself. The best we can hope for is to make parallel programming not much harder than sequential programming. Dally himself is giving a keynote speech at the International Conference on Parallel Processing in Portland in September titled “Streams: Parallel Programming Made Simple.” There’s that simple word yet again.

That’s not to say there aren’t problems to be solved. There are, and parallel programming is going to continue to be a problem. However, unlike the doomsayers and the simplifiers, I think these are hard problems, but not impossible. We solve hard problems every day. We’ve already developed several successful, widely-used parallel programming paradigms, including MPI and OpenMP. They may not be perfect, universal models, but we should learn what worked. And we have as much to learn from proposed models that did not succeed or survive, such as High Performance Fortran.

And, frankly, I have confidence in the applications programmer’s ability to develop algorithms and approaches to using parallelism. Apparently, many in the computer science community do not.

—–

Michael Wolfe has developed compilers for over 30 years in both academia and industry, and is now a senior compiler engineer at The Portland Group, Inc. (www.pgroup.com), a wholly-owned subsidiary of STMicroelectronics, Inc. The opinions stated here are those of the author, and do not represent opinions of The Portland Group, Inc. or STMicroelectronics, Inc.

Subscribe to HPCwire's Weekly Update!

Be the most informed person in the room! Stay ahead of the tech trends with industy updates delivered to you every week!

Fluid HPC: How Extreme-Scale Computing Should Respond to Meltdown and Spectre

February 15, 2018

The Meltdown and Spectre vulnerabilities are proving difficult to fix, and initial experiments suggest security patches will cause significant performance penalties to HPC applications. Even as these patches are rolled o Read more…

By Pete Beckman

Intel Touts Silicon Spin Qubits for Quantum Computing

February 14, 2018

Debate around what makes a good qubit and how best to manufacture them is a sprawling topic. There are many insistent voices favoring one or another approach. Referencing a paper published today in Nature, Intel has offe Read more…

By John Russell

Brookhaven Ramps Up Computing for National Security Effort

February 14, 2018

Last week, Dan Coats, the director of Director of National Intelligence for the U.S., warned the Senate Intelligence Committee that Russia was likely to meddle in the 2018 mid-term U.S. elections, much as it stands accused of doing in the 2016 Presidential election. Read more…

By John Russell

HPE Extreme Performance Solutions

Safeguard Your HPC Environment with the World’s Most Secure Industry Standard Servers

Today’s organizations operate in an environment with ever-evolving threats, and in order to protect themselves they must continuously bolster their security strategy. Hewlett Packard Enterprise (HPE) and Intel® are addressing modern security challenges with the world’s most secure industry standard servers powered by the latest generation of Intel® Xeon® Scalable processors. Read more…

AI Cloud Competition Heats Up: Google’s TPUs, Amazon Building AI Chip

February 12, 2018

Competition in the white hot AI (and public cloud) market pits Google against Amazon this week, with Google offering AI hardware on its cloud platform intended to make it easier, faster and cheaper to train and run machi Read more…

By Doug Black

Fluid HPC: How Extreme-Scale Computing Should Respond to Meltdown and Spectre

February 15, 2018

The Meltdown and Spectre vulnerabilities are proving difficult to fix, and initial experiments suggest security patches will cause significant performance penal Read more…

By Pete Beckman

Brookhaven Ramps Up Computing for National Security Effort

February 14, 2018

Last week, Dan Coats, the director of Director of National Intelligence for the U.S., warned the Senate Intelligence Committee that Russia was likely to meddle in the 2018 mid-term U.S. elections, much as it stands accused of doing in the 2016 Presidential election. Read more…

By John Russell

AI Cloud Competition Heats Up: Google’s TPUs, Amazon Building AI Chip

February 12, 2018

Competition in the white hot AI (and public cloud) market pits Google against Amazon this week, with Google offering AI hardware on its cloud platform intended Read more…

By Doug Black

Russian Nuclear Engineers Caught Cryptomining on Lab Supercomputer

February 12, 2018

Nuclear scientists working at the All-Russian Research Institute of Experimental Physics (RFNC-VNIIEF) have been arrested for using lab supercomputing resources to mine crypto-currency, according to a report in Russia’s Interfax News Agency. Read more…

By Tiffany Trader

The Food Industry’s Next Journey — from Mars to Exascale

February 12, 2018

Global food producer and one of the world's leading chocolate companies Mars Inc. has a unique perspective on the impact that exascale computing will have on the food industry. Read more…

By Scott Gibson, Oak Ridge National Laboratory

Singularity HPC Container Start-Up – Sylabs – Emerges from Stealth

February 8, 2018

The driving force behind Singularity, the popular HPC container technology, is bringing the open source platform to the enterprise with the launch of a new vent Read more…

By George Leopold

Dell EMC Debuts PowerEdge Servers with AMD EPYC Chips

February 6, 2018

AMD notched another EPYC processor win today with Dell EMC’s introduction of three PowerEdge servers (R6415, R7415, and R7425) based on the EPYC 7000-series p Read more…

By John Russell

‘Next Generation’ Universe Simulation Is Most Advanced Yet

February 5, 2018

The research group that gave us the most detailed time-lapse simulation of the universe’s evolution in 2014, spanning 13.8 billion years of cosmic evolution, is back in the spotlight with an even more advanced cosmological model that is providing new insights into how black holes influence the distribution of dark matter, how heavy elements are produced and distributed, and where magnetic fields originate. Read more…

By Tiffany Trader

Inventor Claims to Have Solved Floating Point Error Problem

January 17, 2018

"The decades-old floating point error problem has been solved," proclaims a press release from inventor Alan Jorgensen. The computer scientist has filed for and Read more…

By Tiffany Trader

Japan Unveils Quantum Neural Network

November 22, 2017

The U.S. and China are leading the race toward productive quantum computing, but it's early enough that ultimate leadership is still something of an open questi Read more…

By Tiffany Trader

AMD Showcases Growing Portfolio of EPYC and Radeon-based Systems at SC17

November 13, 2017

AMD’s charge back into HPC and the datacenter is on full display at SC17. Having launched the EPYC processor line in June along with its MI25 GPU the focus he Read more…

By John Russell

Researchers Measure Impact of ‘Meltdown’ and ‘Spectre’ Patches on HPC Workloads

January 17, 2018

Computer scientists from the Center for Computational Research, State University of New York (SUNY), University at Buffalo have examined the effect of Meltdown Read more…

By Tiffany Trader

Nvidia Responds to Google TPU Benchmarking

April 10, 2017

Nvidia highlights strengths of its newest GPU silicon in response to Google's report on the performance and energy advantages of its custom tensor processor. Read more…

By Tiffany Trader

IBM Begins Power9 Rollout with Backing from DOE, Google

December 6, 2017

After over a year of buildup, IBM is unveiling its first Power9 system based on the same architecture as the Department of Energy CORAL supercomputers, Summit a Read more…

By Tiffany Trader

Fast Forward: Five HPC Predictions for 2018

December 21, 2017

What’s on your list of high (and low) lights for 2017? Volta 100’s arrival on the heels of the P100? Appearance, albeit late in the year, of IBM’s Power9? Read more…

By John Russell

Russian Nuclear Engineers Caught Cryptomining on Lab Supercomputer

February 12, 2018

Nuclear scientists working at the All-Russian Research Institute of Experimental Physics (RFNC-VNIIEF) have been arrested for using lab supercomputing resources to mine crypto-currency, according to a report in Russia’s Interfax News Agency. Read more…

By Tiffany Trader

Leading Solution Providers

Chip Flaws ‘Meltdown’ and ‘Spectre’ Loom Large

January 4, 2018

The HPC and wider tech community have been abuzz this week over the discovery of critical design flaws that impact virtually all contemporary microprocessors. T Read more…

By Tiffany Trader

Perspective: What Really Happened at SC17?

November 22, 2017

SC is over. Now comes the myriad of follow-ups. Inboxes are filled with templated emails from vendors and other exhibitors hoping to win a place in the post-SC thinking of booth visitors. Attendees of tutorials, workshops and other technical sessions will be inundated with requests for feedback. Read more…

By Andrew Jones

How Meltdown and Spectre Patches Will Affect HPC Workloads

January 10, 2018

There have been claims that the fixes for the Meltdown and Spectre security vulnerabilities, named the KPTI (aka KAISER) patches, are going to affect applicatio Read more…

By Rosemary Francis

GlobalFoundries, Ayar Labs Team Up to Commercialize Optical I/O

December 4, 2017

GlobalFoundries (GF) and Ayar Labs, a startup focused on using light, instead of electricity, to transfer data between chips, today announced they've entered in Read more…

By Tiffany Trader

Tensors Come of Age: Why the AI Revolution Will Help HPC

November 13, 2017

Thirty years ago, parallel computing was coming of age. A bitter battle began between stalwart vector computing supporters and advocates of various approaches to parallel computing. IBM skeptic Alan Karp, reacting to announcements of nCUBE’s 1024-microprocessor system and Thinking Machines’ 65,536-element array, made a public $100 wager that no one could get a parallel speedup of over 200 on real HPC workloads. Read more…

By John Gustafson & Lenore Mullin

Flipping the Flops and Reading the Top500 Tea Leaves

November 13, 2017

The 50th edition of the Top500 list, the biannual publication of the world’s fastest supercomputers based on public Linpack benchmarking results, was released Read more…

By Tiffany Trader

V100 Good but not Great on Select Deep Learning Aps, Says Xcelerit

November 27, 2017

Wringing optimum performance from hardware to accelerate deep learning applications is a challenge that often depends on the specific application in use. A benc Read more…

By John Russell

2017 Gordon Bell Prize Finalists Named

October 23, 2017

The three finalists for this year’s Gordon Bell Prize in High Performance Computing have been announced. They include two papers on projects run on China’s Read more…

By John Russell

  • arrow
  • Click Here for More Headlines
  • arrow
Share This