Intel: CPUs Will Prevail Over Accelerators in HPC

By Michael Feldman

September 24, 2008

HPC hardware accelerators — GPUs, FPGAs, the Cell processor, and custom ASICs like the ClearSpeed floating point device — have captured the imagination of HPC users in search of higher performance and lower power consumption. While these offload engines continue to show impressive performance results for supercomputing workloads, Intel is sticking to its CPU guns to deliver HPC to the broader market. According to Richard Dracott, Intel’s general manager of the company’s High Performance Computing business unit, CPU multicore processors, and eventually manycore processors, will prevail over accelerator solutions in the financial services industry, as well as for HPC applications in general.

Dracott says he’s seen the pattern before where people get attracted to specialized hardware for particular applications. But in the end, he says, general-purpose CPUs turn out to deliver the best ROI. Dracott claims that to exploit acceleration in HPC, developers need to modify the software anyway, so they might as well modify it for multicore. “What we’re finding is that if someone is going to go to the effort of optimizing an application to take advantage of an offload engine, whatever it may be, the first thing they have to do is parallelize their code,” he told me.

To Intel’s credit, the company has developed a full-featured set of tools and libraries to help mainstream developers parallelize their codes for x86 hardware. With the six-core Dunnington in the field today and eight-core Nehalem processors just around the corner, developers will need all the help they can get to fully utilize the additional processing power.

In fact though, adding CPU-based multithreading parallelism to your app tends to be more difficult than adding data parallelism. The latter is the only type of parallelism accelerators are any good at. And if your workload can exploit data parallelism, this can be done rather straightforwardly. With the advent of NVIDIA’s CUDA, AMD’s Brook+, RapidMind’s development platform, FPGA C-based frameworks, and SDKs from ClearSpeed and other vendors, the programming of these devices has become simpler.

And it may get simpler yet. PGI compiler developer Michael Wolfe thinks there is no reason why high-level language compilers can’t take advantage of these offload engines. “We believe we can produce compilers that allow evolutionary migration from today’s processors to accelerators, and that accelerators provide the most promising path to high performance in the future,” he wrote recently in his HPCwire column.

Of course, CPUs are not standing still performance-wise. According to Dracott, when financial customers were asked how long a 10x performance advantage over a CPU-based solution would have to be maintained to make it worth their while, they told him anywhere from 2-3 years up to as much as 7 years. For production environments, the software investment required to bring accelerators into the mix needs to account for re-testing and re-certification. In the case of the financial services industry (because of regulatory and other legal requirements), this can be a significant part of the effort. “And by the time they actually make the investment in the software, the general-purpose [CPU] hardware has caught up,” says Dracott.

Maybe. A lot of applications are already realizing much better than a 10x improvements in performance with hardware acceleration. SciComp, a company that offers derivatives pricing software, recently announced a “20-100X execution speed increase” for its pricing models. Other HPC workloads have done even better. And while the CPU hardware will eventually catch up to current accelerators, all silicon is moving up the performance ladder, roughly according to Moore’s Law. So the CPU-accelerator performance gap will in all likelihood remain.

Accelerators do have a steeper hill to climb in certain areas though. Except for the Cell processor, where a PowerPC core is built-in, all accelerators require a connection to a CPU host. Depending upon the nature of the connection (PCI, HyperTransport, QuickPath, etc.) the offload engine can become starved for data because of bandwidth limitations. In fact, the time spent talking to the host can eat up any performance gains realized through faster execution. More local store on the accelerator and careful programming can often mitigate this, but the general-purpose CPU has a built-in advantage here.

Dracott points out that the lack of double precision floating point capabilities and error correction code (ECC) memory limits accelerator deployment in many HPC production environments. This is especially true in the financial space, where predictability and reliability of results are paramount. But the latest generation of offload engines all support DP to some degree, and only GPUs have an ECC problem. ClearSpeed ASICs, in particular, have full-throttle 64-bit support plus enterprise-level ECC protection. GPUs, on the other hand, will have to deal with soft error protection in some systematic way to become a more widely deployed solution for technical computing. I’ve got to believe that NVIDIA and AMD will eventually add this capability to their GPU computing offerings.
 
The shortcomings of accelerator solutions have prevented much real-world deployment in production situations, according to Dracott. He thinks users will continue to experiment with offload engines for several more years, but with the exception of certain application niches, most will eventually end up back at the CPU. But interest in these more exotic solutions remains high in the HPC community. HPCwire’s Dennis Barker, at this week’s High Performance on Wall Street conference, reports that the hardware accelerator companies were drawing quite a crowd and a number of FPGA-accelerated products are already on the market. “Sellers of these products were all over the place, their booths were busy, and several sessions on the subject were standing-room only,” he writes.

And despite Intel’s commitment to the x86 CPU and Dracott’s take on the future of accelerators, the company has been evolving its position on co-processor acceleration. Intel’s (and IBM’s) Geneseo initiative to extend PCI Express for offload engines and its plans to license the new QuickPath interconnect technology would seem to indicate that the company hasn’t completely discounted acceleration. AMD, of course, has Torenzza, its own co-processor integration technology. Whether Intel is just hedging its bets to counter its rival or is genuinely committed to sharing the computing world with other architectures remains to be seen.

Subscribe to HPCwire's Weekly Update!

Be the most informed person in the room! Stay ahead of the tech trends with industy updates delivered to you every week!

Ayar Labs to Demo Photonics Chiplet in FPGA Package at Hot Chips

August 19, 2019

Silicon startup Ayar Labs continues to gain momentum with its DARPA-backed optical chiplet technology that puts advanced electronics and optics on the same chip using standard CMOS fabrication. At Hot Chips 31 in Stanfor Read more…

By Tiffany Trader

Talk to Me: Nvidia Claims NLP Inference, Training Records

August 15, 2019

Nvidia says it’s achieved significant advances in conversation natural language processing (NLP) training and inference, enabling more complex, immediate-response interchanges between customers and chatbots. And the co Read more…

By Doug Black

Trump Administration and NIST Issue AI Standards Development Plan

August 14, 2019

Efforts to develop AI are gathering steam fast. On Monday, the White House issued a federal plan to help develop technical standards for AI following up on a mandate contained in the Administration’s AI Executive Order Read more…

By John Russell

AWS Solution Channel

Efficiency and Cost-Optimization for HPC Workloads – AWS Batch and Amazon EC2 Spot Instances

High Performance Computing on AWS leverages the power of cloud computing and the extreme scale it offers to achieve optimal HPC price/performance. With AWS you can right size your services to meet exactly the capacity requirements you need without having to overprovision or compromise capacity. Read more…

HPE Extreme Performance Solutions

Bring the combined power of HPC and AI to your business transformation

FPGA (Field Programmable Gate Array) acceleration cards are not new, as they’ve been commercially available since 1984. Typically, the emphasis around FPGAs has centered on the fact that they’re programmable accelerators, and that they can truly offer workload specific hardware acceleration solutions without requiring custom silicon. Read more…

IBM Accelerated Insights

Cloudy with a Chance of Mainframes

[Connect with HPC users and learn new skills in the IBM Spectrum LSF User Community.]

Rapid rates of change sometimes result in unexpected bedfellows. Read more…

Scientists to Tap Exascale Computing to Unlock the Mystery of our Accelerating Universe

August 14, 2019

The universe and everything in it roared to life with the Big Bang approximately 13.8 billion years ago. It has continued expanding ever since. While we have a good understanding of the early universe, its fate billions Read more…

By Rob Johnson

Ayar Labs to Demo Photonics Chiplet in FPGA Package at Hot Chips

August 19, 2019

Silicon startup Ayar Labs continues to gain momentum with its DARPA-backed optical chiplet technology that puts advanced electronics and optics on the same chip Read more…

By Tiffany Trader

Scientists to Tap Exascale Computing to Unlock the Mystery of our Accelerating Universe

August 14, 2019

The universe and everything in it roared to life with the Big Bang approximately 13.8 billion years ago. It has continued expanding ever since. While we have a Read more…

By Rob Johnson

AI is the Next Exascale – Rick Stevens on What that Means and Why It’s Important

August 13, 2019

Twelve years ago the Department of Energy (DOE) was just beginning to explore what an exascale computing program might look like and what it might accomplish. Today, DOE is repeating that process for AI, once again starting with science community town halls to gather input and stimulate conversation. The town hall program... Read more…

By Tiffany Trader and John Russell

Cray Wins NNSA-Livermore ‘El Capitan’ Exascale Contract

August 13, 2019

Cray has won the bid to build the first exascale supercomputer for the National Nuclear Security Administration (NNSA) and Lawrence Livermore National Laborator Read more…

By Tiffany Trader

AMD Launches Epyc Rome, First 7nm CPU

August 8, 2019

From a gala event at the Palace of Fine Arts in San Francisco yesterday (Aug. 7), AMD launched its second-generation Epyc Rome x86 chips, based on its 7nm proce Read more…

By Tiffany Trader

Lenovo Drives Single-Socket Servers with AMD Epyc Rome CPUs

August 7, 2019

No summer doldrums here. As part of the AMD Epyc Rome launch event in San Francisco today, Lenovo announced two new single-socket servers, the ThinkSystem SR635 Read more…

By Doug Black

Building Diversity and Broader Engagement in the HPC Community

August 7, 2019

Increasing diversity and inclusion in HPC is a community-building effort. Representation of both issues and individuals matters - the more people see HPC in a w Read more…

By AJ Lauer

Xilinx vs. Intel: FPGA Market Leaders Launch Server Accelerator Cards

August 6, 2019

The two FPGA market leaders, Intel and Xilinx, both announced new accelerator cards this week designed to handle specialized, compute-intensive workloads and un Read more…

By Doug Black

High Performance (Potato) Chips

May 5, 2006

In this article, we focus on how Procter & Gamble is using high performance computing to create some common, everyday supermarket products. Tom Lange, a 27-year veteran of the company, tells us how P&G models products, processes and production systems for the betterment of consumer package goods. Read more…

By Michael Feldman

Supercomputer-Powered AI Tackles a Key Fusion Energy Challenge

August 7, 2019

Fusion energy is the Holy Grail of the energy world: low-radioactivity, low-waste, zero-carbon, high-output nuclear power that can run on hydrogen or lithium. T Read more…

By Oliver Peckham

Cray, AMD to Extend DOE’s Exascale Frontier

May 7, 2019

Cray and AMD are coming back to Oak Ridge National Laboratory to partner on the world’s largest and most expensive supercomputer. The Department of Energy’s Read more…

By Tiffany Trader

Graphene Surprises Again, This Time for Quantum Computing

May 8, 2019

Graphene is fascinating stuff with promise for use in a seeming endless number of applications. This month researchers from the University of Vienna and Institu Read more…

By John Russell

AMD Verifies Its Largest 7nm Chip Design in Ten Hours

June 5, 2019

AMD announced last week that its engineers had successfully executed the first physical verification of its largest 7nm chip design – in just ten hours. The AMD Radeon Instinct Vega20 – which boasts 13.2 billion transistors – was tested using a TSMC-certified Calibre nmDRC software platform from Mentor. Read more…

By Oliver Peckham

TSMC and Samsung Moving to 5nm; Whither Moore’s Law?

June 12, 2019

With reports that Taiwan Semiconductor Manufacturing Co. (TMSC) and Samsung are moving quickly to 5nm manufacturing, it’s a good time to again ponder whither goes the venerable Moore’s law. Shrinking feature size has of course been the primary hallmark of achieving Moore’s law... Read more…

By John Russell

Deep Learning Competitors Stalk Nvidia

May 14, 2019

There is no shortage of processing architectures emerging to accelerate deep learning workloads, with two more options emerging this week to challenge GPU leader Nvidia. First, Intel researchers claimed a new deep learning record for image classification on the ResNet-50 convolutional neural network. Separately, Israeli AI chip startup Hailo.ai... Read more…

By George Leopold

Cray Wins NNSA-Livermore ‘El Capitan’ Exascale Contract

August 13, 2019

Cray has won the bid to build the first exascale supercomputer for the National Nuclear Security Administration (NNSA) and Lawrence Livermore National Laborator Read more…

By Tiffany Trader

Leading Solution Providers

ISC 2019 Virtual Booth Video Tour

CRAY
CRAY
DDN
DDN
DELL EMC
DELL EMC
GOOGLE
GOOGLE
ONE STOP SYSTEMS
ONE STOP SYSTEMS
PANASAS
PANASAS
VERNE GLOBAL
VERNE GLOBAL

Nvidia Embraces Arm, Declares Intent to Accelerate All CPU Architectures

June 17, 2019

As the Top500 list was being announced at ISC in Frankfurt today with an upgraded petascale Arm supercomputer in the top third of the list, Nvidia announced its Read more…

By Tiffany Trader

Top500 Purely Petaflops; US Maintains Performance Lead

June 17, 2019

With the kick-off of the International Supercomputing Conference (ISC) in Frankfurt this morning, the 53rd Top500 list made its debut, and this one's for petafl Read more…

By Tiffany Trader

AMD Launches Epyc Rome, First 7nm CPU

August 8, 2019

From a gala event at the Palace of Fine Arts in San Francisco yesterday (Aug. 7), AMD launched its second-generation Epyc Rome x86 chips, based on its 7nm proce Read more…

By Tiffany Trader

A Behind-the-Scenes Look at the Hardware That Powered the Black Hole Image

June 24, 2019

Two months ago, the first-ever image of a black hole took the internet by storm. A team of scientists took years to produce and verify the striking image – an Read more…

By Oliver Peckham

Cray – and the Cray Brand – to Be Positioned at Tip of HPE’s HPC Spear

May 22, 2019

More so than with most acquisitions of this kind, HPE’s purchase of Cray for $1.3 billion, announced last week, seems to have elements of that overused, often Read more…

By Doug Black and Tiffany Trader

Chinese Company Sugon Placed on US ‘Entity List’ After Strong Showing at International Supercomputing Conference

June 26, 2019

After more than a decade of advancing its supercomputing prowess, operating the world’s most powerful supercomputer from June 2013 to June 2018, China is keep Read more…

By Tiffany Trader

In Wake of Nvidia-Mellanox: Xilinx to Acquire Solarflare

April 25, 2019

With echoes of Nvidia’s recent acquisition of Mellanox, FPGA maker Xilinx has announced a definitive agreement to acquire Solarflare Communications, provider Read more…

By Doug Black

Qualcomm Invests in RISC-V Startup SiFive

June 7, 2019

Investors are zeroing in on the open standard RISC-V instruction set architecture and the processor intellectual property being developed by a batch of high-flying chip startups. Last fall, Esperanto Technologies announced a $58 million funding round. Read more…

By George Leopold

  • arrow
  • Click Here for More Headlines
  • arrow
Do NOT follow this link or you will be banned from the site!
Share This