Straight Shooter: A Conversation with 2008 Seymour Cray Award Winner Steve Wallach

By Michael Feldman

November 17, 2008

Steve Wallach, a supercomputing legend, has participated in all 20 supercomputing shows and will be honored at the 2008 event with IEEE’s Seymour Cray Award for his “contribution to high-performance computing through design of innovative vector and parallel computing systems, notably the Convex mini-supercomputer series, a distinguished industrial career and acts of public service.”

The Seymour Cray Award, established in 1998 by the IEEE Computer Society Board of Governors, is given each year to individuals whose innovative contributions to high-performance computing systems best exemplify the creative spirit demonstrated by the late Seymour Cray. Steve Wallach will accept the award on November 20 at 1:30 p.m. at SC08. In addition he will give a plenary presentation, “Processor Architecture: Past, Present, Future” on Wednesday, November 19 at 1:30 p.m.

Those who know Steve Wallach know he is never short on opinions, especially when it comes to high performance computing. HPCwire talked to Wallach about everything from the future of HPC to his philosophy on building a successful HPC business.

Steve Wallach, Convey Computer Corp.HPCwire: First of all, congratulations on the award. What’s the best thing about winning the Cray award?

Steve Wallach: Everything. This is one of our industry’s greatest honors and I am deeply appreciative. To be associated with Seymour Cray, even in name only, is phenomenal. When I was notified, I was speechless. When the Cray 1 was announced, I read every piece of literature I could find on it. Seymour Cray and his designs had an effect on me, from a technical perspective, more than any other single event.

HPCwire: What’s the single biggest change you’ve seen in high-performance computing in the past 20 years?

Wallach: Perhaps the biggest change is the leveling of the uniprocessor performance. For all practical purposes, with the leveling off of clock frequency and memory bandwidth, the performance of ONE processor core has not changed much. Thus, we have multicore and massive parallelism. In fact, if one calculates the memory bandwidth per core (total memory bandwidth divided by the number of cores) it is DECREASING over time (normalized for peak gflops/core). I was a member of several government studies (National Academy of Engineering and Defense Science Board) that highlighted this leveling-off phenomena.

If we can’t access the data, we can’t operate on the data. This is one reason the industry is looking into ways to create semantically rich instructions. We know we can achieve more compute performance once the data is located within the core’s memory/register infrastructure.

HPCwire: You state in your plenary presentation that the past 40 years has taught us that the “system that is easier to program will always win.” Why is that?

Wallach: It boils down to two issues: cost of ownership and cost of development. At a recent Los Alamos Conference, it was pointed out that the cost of a programmer for one year is MORE than the cost of acquiring a TERAFLOP (peak performance) system. We need to address the software productivity issue. Of course this is one of the main objectives of DARPA’s HPCS (High Productivity Computer Systems) program.

We address both issues with our new servers. For example, the Convey overall system hardware and software architecture is identical to the x86, with coprocessor instructions appearing as extensions to the x86. Thus, programmers benefit from 100 percent productivity and portability.

The Convey coprocessor and the Intel x86 share a common cache-coherent physical and virtual address space. What this means is that the programmer does not need to manage the physical memory on the coprocessor nor explicitly move data back and forth between the x86 main memory and the coprocessor main memory.

Finally, the Convey-engineered, ANSI standard C, C++, and Fortran compiler automatically generates x86 and coprocessor instructions. Only one compiler is used, which is a significant contrast to various forms of attached accelerators that use two or more compilers. Existing applications can be compiled as is, and language subsets and/or non-standard extensions are not required to use the Convey coprocessor.

HPCwire: After all the history with parallel programming, why is HPC application development still so problematic?

Wallach: As Yogi Berra said: “It is déjà vu all over again.” Many of the issues discussed and analyzed today, existed 20 years ago. Many applications still have code that is 20 years old. Many applications still have “serial math” as their underpinning. And before we forget, our universities are really not teaching parallel programming. But now HPC applications are moving into a different application space called Data Intensive Computing. The computer centers at Google and Microsoft are substantially larger than what was once thought of as a “classic” HPC center. The industry needs to put more time and money into software productivity — and we are doing that. Just last March, for example, Microsoft and Intel announced a joint research initiative focusing on improving programming tools for multicore processing.

HPCwire: What’s happened to innovation in high-performance computing?

Wallach: It’s always there. HPC represents the leading — and sometimes the bleeding edge of computing coupled with a variety of practical applications. Innovation also rules in the area of results gained from HPC. Without supercomputing power, we wouldn’t understand the human genome, travel to Mars, or — as our first customer the University of California, San Diego is experiencing — initiate unrestricted “blind searches” of massive protein databases to look for possible and unanticipated modifications in proteins. Modifications are particularly important for the study of diseases where multiple genes are involved, such as heart disease or cancer.

HPCwire: What is next for high performance computing?

Wallach: I believe there will be two major thrusts. One thrust will be in the software development area. We need new paradigms. At the recent Salishan Conference, this was pointed out over and over again. I expect we begin to have more widespread use of PGAS (Partitioned Global Address Space) languages. These languages are more productive than using MPI. And, with the introduction of Intel’s QPI, coupled with AMD’s HT, I expect PGAS to accelerate.

The other major thrust will be the widespread use of optical interconnects. We need more bisection bandwidth for the next generation MPPs. We also need more bandwidth for chip-to-chip connections. The telecommunications industry uses DWDM (dense wavelength division multiplexing) optics for all its long haul communications. Hopefully, a combination of Moore’s Law and material advances will bring this technology to centimeter-length busses.

HPCwire: What’s your philosophy of the HPC business and how has it changed over the years?

Wallach: It’s all about value for the customer — a philosophy that has stayed constant over the years. How do we make life easier for the customer? As an engineering company driven by engineers for engineers, we understand what makes one product difficult to work with and another one easy and we strive for easy. While our customers will probably buy our servers for the performance gains and price value, we’ll win their trust and enthusiasm by being the easiest to program.

We’ve focused on making it easy for programmers, developers and system administrators to use our product. We know that they will be the ones who ultimately have to make our solutions work. We actively consider ease-of-use in all our decisions knowing that we want them to be our most enthusiastic fans in the future.

HPCwire: What advice would you give to up-and-coming computer scientists?

Wallach: I am not sure I am the best person to answer this! I practice what I call “Eclectic Engineering.” I believe to be innovative and productive you need to know as much as possible about the entire application/problem before focusing on one particular aspect. So, even if you want to be a compiler writer, you should know how to connect a logic analyzer to a circuit board.

Subscribe to HPCwire's Weekly Update!

Be the most informed person in the room! Stay ahead of the tech trends with industry updates delivered to you every week!

MLPerf Inference 4.0 Results Showcase GenAI; Nvidia Still Dominates

March 28, 2024

There were no startling surprises in the latest MLPerf Inference benchmark (4.0) results released yesterday. Two new workloads — Llama 2 and Stable Diffusion XL — were added to the benchmark suite as MLPerf continues Read more…

Q&A with Nvidia’s Chief of DGX Systems on the DGX-GB200 Rack-scale System

March 27, 2024

Pictures of Nvidia's new flagship mega-server, the DGX GB200, on the GTC show floor got favorable reactions on social media for the sheer amount of computing power it brings to artificial intelligence.  Nvidia's DGX Read more…

Call for Participation in Workshop on Potential NSF CISE Quantum Initiative

March 26, 2024

Editor’s Note: Next month there will be a workshop to discuss what a quantum initiative led by NSF’s Computer, Information Science and Engineering (CISE) directorate could entail. The details are posted below in a Ca Read more…

Waseda U. Researchers Reports New Quantum Algorithm for Speeding Optimization

March 25, 2024

Optimization problems cover a wide range of applications and are often cited as good candidates for quantum computing. However, the execution time for constrained combinatorial optimization applications on quantum device Read more…

NVLink: Faster Interconnects and Switches to Help Relieve Data Bottlenecks

March 25, 2024

Nvidia’s new Blackwell architecture may have stolen the show this week at the GPU Technology Conference in San Jose, California. But an emerging bottleneck at the network layer threatens to make bigger and brawnier pro Read more…

Who is David Blackwell?

March 22, 2024

During GTC24, co-founder and president of NVIDIA Jensen Huang unveiled the Blackwell GPU. This GPU itself is heavily optimized for AI work, boasting 192GB of HBM3E memory as well as the the ability to train 1 trillion pa Read more…

MLPerf Inference 4.0 Results Showcase GenAI; Nvidia Still Dominates

March 28, 2024

There were no startling surprises in the latest MLPerf Inference benchmark (4.0) results released yesterday. Two new workloads — Llama 2 and Stable Diffusion Read more…

Q&A with Nvidia’s Chief of DGX Systems on the DGX-GB200 Rack-scale System

March 27, 2024

Pictures of Nvidia's new flagship mega-server, the DGX GB200, on the GTC show floor got favorable reactions on social media for the sheer amount of computing po Read more…

NVLink: Faster Interconnects and Switches to Help Relieve Data Bottlenecks

March 25, 2024

Nvidia’s new Blackwell architecture may have stolen the show this week at the GPU Technology Conference in San Jose, California. But an emerging bottleneck at Read more…

Who is David Blackwell?

March 22, 2024

During GTC24, co-founder and president of NVIDIA Jensen Huang unveiled the Blackwell GPU. This GPU itself is heavily optimized for AI work, boasting 192GB of HB Read more…

Nvidia Looks to Accelerate GenAI Adoption with NIM

March 19, 2024

Today at the GPU Technology Conference, Nvidia launched a new offering aimed at helping customers quickly deploy their generative AI applications in a secure, s Read more…

The Generative AI Future Is Now, Nvidia’s Huang Says

March 19, 2024

We are in the early days of a transformative shift in how business gets done thanks to the advent of generative AI, according to Nvidia CEO and cofounder Jensen Read more…

Nvidia’s New Blackwell GPU Can Train AI Models with Trillions of Parameters

March 18, 2024

Nvidia's latest and fastest GPU, codenamed Blackwell, is here and will underpin the company's AI plans this year. The chip offers performance improvements from Read more…

Nvidia Showcases Quantum Cloud, Expanding Quantum Portfolio at GTC24

March 18, 2024

Nvidia’s barrage of quantum news at GTC24 this week includes new products, signature collaborations, and a new Nvidia Quantum Cloud for quantum developers. Wh Read more…

Alibaba Shuts Down its Quantum Computing Effort

November 30, 2023

In case you missed it, China’s e-commerce giant Alibaba has shut down its quantum computing research effort. It’s not entirely clear what drove the change. Read more…

Nvidia H100: Are 550,000 GPUs Enough for This Year?

August 17, 2023

The GPU Squeeze continues to place a premium on Nvidia H100 GPUs. In a recent Financial Times article, Nvidia reports that it expects to ship 550,000 of its lat Read more…

Shutterstock 1285747942

AMD’s Horsepower-packed MI300X GPU Beats Nvidia’s Upcoming H200

December 7, 2023

AMD and Nvidia are locked in an AI performance battle – much like the gaming GPU performance clash the companies have waged for decades. AMD has claimed it Read more…

DoD Takes a Long View of Quantum Computing

December 19, 2023

Given the large sums tied to expensive weapon systems – think $100-million-plus per F-35 fighter – it’s easy to forget the U.S. Department of Defense is a Read more…

Synopsys Eats Ansys: Does HPC Get Indigestion?

February 8, 2024

Recently, it was announced that Synopsys is buying HPC tool developer Ansys. Started in Pittsburgh, Pa., in 1970 as Swanson Analysis Systems, Inc. (SASI) by John Swanson (and eventually renamed), Ansys serves the CAE (Computer Aided Engineering)/multiphysics engineering simulation market. Read more…

Choosing the Right GPU for LLM Inference and Training

December 11, 2023

Accelerating the training and inference processes of deep learning models is crucial for unleashing their true potential and NVIDIA GPUs have emerged as a game- Read more…

Intel’s Server and PC Chip Development Will Blur After 2025

January 15, 2024

Intel's dealing with much more than chip rivals breathing down its neck; it is simultaneously integrating a bevy of new technologies such as chiplets, artificia Read more…

Baidu Exits Quantum, Closely Following Alibaba’s Earlier Move

January 5, 2024

Reuters reported this week that Baidu, China’s giant e-commerce and services provider, is exiting the quantum computing development arena. Reuters reported � Read more…

Leading Solution Providers

Contributors

Comparing NVIDIA A100 and NVIDIA L40S: Which GPU is Ideal for AI and Graphics-Intensive Workloads?

October 30, 2023

With long lead times for the NVIDIA H100 and A100 GPUs, many organizations are looking at the new NVIDIA L40S GPU, which it’s a new GPU optimized for AI and g Read more…

Shutterstock 1179408610

Google Addresses the Mysteries of Its Hypercomputer 

December 28, 2023

When Google launched its Hypercomputer earlier this month (December 2023), the first reaction was, "Say what?" It turns out that the Hypercomputer is Google's t Read more…

AMD MI3000A

How AMD May Get Across the CUDA Moat

October 5, 2023

When discussing GenAI, the term "GPU" almost always enters the conversation and the topic often moves toward performance and access. Interestingly, the word "GPU" is assumed to mean "Nvidia" products. (As an aside, the popular Nvidia hardware used in GenAI are not technically... Read more…

Shutterstock 1606064203

Meta’s Zuckerberg Puts Its AI Future in the Hands of 600,000 GPUs

January 25, 2024

In under two minutes, Meta's CEO, Mark Zuckerberg, laid out the company's AI plans, which included a plan to build an artificial intelligence system with the eq Read more…

Google Introduces ‘Hypercomputer’ to Its AI Infrastructure

December 11, 2023

Google ran out of monikers to describe its new AI system released on December 7. Supercomputer perhaps wasn't an apt description, so it settled on Hypercomputer Read more…

China Is All In on a RISC-V Future

January 8, 2024

The state of RISC-V in China was discussed in a recent report released by the Jamestown Foundation, a Washington, D.C.-based think tank. The report, entitled "E Read more…

Intel Won’t Have a Xeon Max Chip with New Emerald Rapids CPU

December 14, 2023

As expected, Intel officially announced its 5th generation Xeon server chips codenamed Emerald Rapids at an event in New York City, where the focus was really o Read more…

IBM Quantum Summit: Two New QPUs, Upgraded Qiskit, 10-year Roadmap and More

December 4, 2023

IBM kicks off its annual Quantum Summit today and will announce a broad range of advances including its much-anticipated 1121-qubit Condor QPU, a smaller 133-qu Read more…

  • arrow
  • Click Here for More Headlines
  • arrow
HPCwire