10GbE Networking for HPC — Applications and Technology Trends

By Saqib Jang

June 15, 2009

The first in a two-part series, this article examines the drivers for 10GbE deployment for high-performance cluster computing (HPCC) environments and related technology trends.

Ten Gigabit-per-second Ethernet (10GbE) represents the next level of Ethernet network bandwidth, with networking vendors promoting it as the next great capability. But high-performance computing (HPC) infrastructure and operations professionals must strike a balance between constant operational improvement and sound financial decision-making. So far, 10GbE has been a high-end luxury for environments that want maximum performance regardless of cost, but that’s changing fast. The per-port pricing gap between 10GbE and alternate network options is narrowing rapidly as more vendors increase the competitive pressure on pricing for related components.

So where will this technology truly matter for HPC environments? This article examines the impact of 10GbE on HPC infrastructure and provides guidance for the most effective transformation of your network. The initial focus will be on the top drivers and applications for 10GbE deployment in HPC environments and then the leading technology trends impacting 10GbE NIC designs will be reviewed. The next article in the series will examine the major offerings in the 10GbE NIC area.

Network Convergence for HPC Datacenters

Clusters of commodity servers have rapidly evolved into a highly cost-effective form of supercomputer. As the technology has matured and costs have declined, enterprises across a wide range of industries have begun leveraging HPC for product design and simulation, data analysis and other highly compute intensive applications that were previously beyond the reach of IT budgets. Off-the-shelf clusters frequently use Gigabit Ethernet as the cluster interconnect technology, but a number of cluster vendors are exploiting more specialized cluster interconnect fabrics that feature very low message-passing latency.

Although Ethernet has been the de facto technology for the general purpose LAN, Gigabit Ethernet has been considered as a sub-optimal switching fabric for very high performance cluster interconnect and storage networking. This is due primarily to performance issues stemming from the fact that GbE has lower bandwidth than InfiniBand and Fibre Channel, and typically exhibits significantly higher end-to-end latency and CPU utilization.

However, this situation has changed dramatically due to recent developments in low-latency 10 GbE switching and intelligent Ethernet NICs that offload cluster and storage protocol processing from the host processor. These enhancements allow server end systems to fully exploit 10 GbE line rates, while reducing one-hop end-to-end latency to less than 10 microseconds and CPU utilization for line-rate transfers to less than 10 percent.

As a result, 10 GbE end-to-end performance now compares very favorably with that of more specialized datacenter interconnects, eliminating performance as a drawback to the adoption of an Ethernet unified datacenter fabric. Off-loading cluster and storage protocol processing from the central CPU to intelligent 10GbE NIC can also improve the power efficiency of end stations because off-load ASIC processors are generally considerably more power efficient in executing protocol workloads.

10GbE R-NICs for Low-Latency IPC

Traditionally, TCP/IP protocol processing has been performed in software by the end system’s CPU. The load on the CPU increases linearly as a function of packets processed, with the usual rule of thumb being that each bit per second of bandwidth consumes about a Hz of CPU clock (e.g., 1 Gbps of network traffic consumes about 1 GHz of CPU). As more of the host CPU is consumed by the network load, both CPU utilization and host send/receive latency become significant issues.

Over the last few years, vendors of intelligent Ethernet NICs, together with the RDMA Consortium and the IETF, have been working on specifications for hardware-accelerated RDMA over TCP/IP (or iWARP) protocol stacks that can support the ever-increasing performance demands of cluster inter-process communications (IPC) over 10 GbE.

An RDMA over TCP/IP NIC (or R-NIC) provides hardware support for a remote direct memory access (RDMA) mechanism. R-NICs allows a server to read/write data directly between its user memory space and the user memory space of another R-NIC-enabled host on the network, without any involvement of the host operating systems.

R-NICs provide an OS kernel bypass mechanism allowing applications running in user space to post read/write commands that are transferred directly to the RDMA over TCP/IP NIC (R-NIC). This eliminates the delay and overhead associated with copy operations among multiple buffer locations, kernel transitions and application context switches. R-NICs can reduce CPU utilization for 10 Gbps transfers to less than 10 percent and can reduce the host component of end-to-end latency to as little as 5–10 microseconds.

To reduce latency and maximize performance, cluster applications use the industry-standard message passing interface (MPI) middleware that is implemented atop of iWARP and other RDMA transports. Use of MPI removes the need for developers to understand the details of the particular cluster interconnect.

There are many MPI variants, some of which are vendor-specific, while others are open source-based standards. The former includes Intel MPI, HP MPI, Platform (Scali) MPI, and MPI/Pro. Popular open source MPI variants include MPICH and LAM/MPI.

The OpenFabrics Alliance is developing open-source middleware APIs for iWARP and other RDMA transport. The OpenFabrics stack includes user-level (uDAPL) and kernel-level (kDAPL) intermediate APIs which run atop RDMA transports, including iWARP. Most of the popular MPI packages now support the OpenFabrics APIs removing the need for 10bE iWARP NIC hardware vendors to directly support MPI middleware. OpenFabrics Alliance has also taken the step of offering a fully-validated Open Fabrics Enterprise Distribution (OFED) stack for Linux.

Enter 10GbE iSCSI and FCoE: Enablers for Storage I/O Consolidation

The concept behind I/O consolidation is simple: the sharing of storage and networking traffic on the same Ethernet physical cable or, in cases that network isolation is desired, the flexibility to configure and use the same hardware for either type of network load, and the prioritizing of traffic delivery through quality of service (QoS) metrics. The benefits end-users will realize from this simple idea are significant.

Companies that leverage I/O consolidation will be able to realize significant gains in server slot efficiencies by using multi-function network/storage adapters to simplify their cabling scheme within a rack, thereby reducing the amount of heat each server generates.
The dominant approach to storage I/O consolidation was iSCSI (Internet SCSI), a flexible and powerful storage area networking (SAN) protocol, providing data availability and performance compared to other Ethernet-based storage approaches such as network-attached storage (NAS). iSCSI replaced the FC stack with the standard networking TCP/IP stack in order to transport the storage traffic over standard lower cost Ethernet.

Customers in entry-level, mid-range, and high-end segments are building flexible storage infrastructures using iSCSI to allocate and shift resources dynamically to cost-effectively meet the storage demands of their compute cluster environments.

There are a number of 10 GbE NICs available that provide hardware-based iSCSI offload including comprehensive bare metal provisioning and management capabilities that come from hardware based boot-from-SAN technology in the 10 GbE NIC. With hardware-based iSCSI offload, SCSI commands issued by the OS are offloaded to the 10GbE NIC, converted into TCP/IP packets and transmitted to the iSCSI storage target that stores the disks. To the OS, the remote storage device appears as locally attached SCSI device. The hardware-based iSCSI offload also enables an OS-agnostic boot-from-SAN, which effectively removes the need for any direct attached storage in the server and moves the software image into a centralized iSCSI SAN.

Although successful in supporting block storage for the broad range of HPC applications, iSCSI has not been adopted for the most demanding of applications, such as data mining and decision support applications, due to performance, resilience, and manageability issues specific to these applications.

The value proposition of the emerging FCoE standard is based primarily on the elimination of the expensive FC infrastructure components in datacenters, which are currently used to connect servers running high-end applications to their networked storage systems. Since FCoE requires 10GbE (with Enhanced Ethernet extensions in both the NICs and the switches), its deployment is not expected till 2010 and is likely to remain an expensive niche interconnect for the foreseeable future.

While FCoE aims to eliminate the FC infrastructure by unifying the storage and networking interconnect into a single 10GbE fabric, it will also provide investment protection for many years — particularly at the storage end of the Fibre Channel SAN via Enhanced Ethernet-to-Fibre Channel switches/gateways.

10GbE Server Connectivity Standards

Most new 10GbE controllers and adapters support dual ports on the network side. Some 10GbE controllers use the second port only for failover, whereas the trend is for dual-port 10GbE NICs to support active/active configurations (i.e., concurrent operation for both ports).

For host-side connectivity, 10GbE NICs supporting PCI Express is the industry standard CPU-to-I/O serial interconnect in volume servers. The available 10GbE NICs support a mix of PCIe v1.1 and the second generation of PCIe, PCIe v2.0 or PCIe Gen2, which was finalized by PCI-SIG in January 2007 and is rapidly gaining market traction.

Intel started shipping X38, the first system-logic chip set supporting PCIe Gen2, in September, 2007, with AMD and NVIDIA following suit shortly thereafter. In March 2009, Intel’s dual-socket (2P) and quad-socket (4P0 server platforms completed the transition to PCIe Gen2.

PCIe Gen2 doubles the data rate possible in each lane of the scalable serial interface to 5Gb/s bidirectional throughput per lane compared to PCIe Gen1 devices, which supports 2.5Gb/s per lane. Thus, a PCIe Gen x8 slot can support an effective throughput of 32Gb/s (assuming the standard Ethernet 8b/10b encoding — every 10 bits sent carry 8 bits of data — so that the useful data transmission rate is four-fifths the raw rate). In comparison, a PCIe V1.1 slot can support 16 Gb/s effective bidirectional throughput.

Traditionally, blade servers have used GbE as the backplane fabric to connect server blades within the chassis. For these systems, blade system manufacturers open up their system designs to enable third parties to offer Fibre Channel and InfiniBand adapters for storage and clustering applications, respectively.

An emerging alternative to adding parallel fabrics for networking, storage and clustering gaining ground in blade servers is to provide 10GbE backplanes for these systems, enabling the use of iSCSI and iWARP storage and clustering protocols, which thereby eliminate the power and space requirements of multiple fabrics and controllers.

During 2007, HP and IBM introduced blade server designs with 1/10Gbe backplanes and mezzanine card offerings for 10GbE connectivity. In September 2008, HP introduced a blade server model that integrates a dual-port 10GbE controller as a default capability. First-generation 10GbE-based blade server designs use the KX4 Backplane Standard, which uses four 3.125 Gbps SerDes links and in which the network-side XAUI port of 10GbE NICs connects to a 10GBASE-KX4-to-XAUI optical PHY.

The blade server market is rapidly moving toward next-generation designs that use 10 Gbps serial links based on 10GBase-KR standard and which reduce the number of backplane traces. In this case, XAUI ports of 10GbE NICs connect to 10GBASE-KR-to-XAUI optical PHYs.

Contrasting 10GbE Physical Layer Options

The 10 Gigabit Ethernet standard encompasses a number of different physical layer (PHY) standards, including optical and copper cabling standards. As of 2009 10 Gigabit Ethernet is still an emerging technology with only 2 million ports shipped in 2008 — the overwhelming majority of which had optical PHYs. Additionally, the majority of these 10GbE ports shipped into switch applications, with only about 5 percent shipping into server interconnects (NICs).

Each successive generation of 10GbE optical modules has resulted in lower power dissipation, smaller footprint, and therefore higher port density. Most importantly for widespread deployment, the cost of these modules has declined by two orders of magnitude since 2002. As a result, 10GbE is nearing the price points required for mass adoption in HPC networks. Typically adoption of a new generation of Ethernet technology occurs when IT managers can buy a 10X increase in bandwidth for 3X-4X increase in price.

SFP+ is the most recent and state-of-the-art optical module form factor, and offers a significant improvement over the earlier XFP standard — with respect to footprint, allowing 24-port and 48-port dense top-of-rack switches and half-height PCIe NICs for datacenter server interfaces.

The SFP+ form-factor has been defined to support both optical interfaces and copper (twin-ax) 10GbE serial connections for distances up to 10 meters, for example, for a top-of-rack switch and for connecting racks within a datacenter. This “direct attach copper (DAC)” configuration further reduces the cost of the module by removing the transmit and receive optical subassemblies. SFP+ optical modules typically dissipate less than 1 W of power, while DAC versions have no active power-consuming components.

The key features enabling DAC connections of over 10m are i) EDC, ii) 10G TX pre-emphasis, and iii) forward error correction. NetLogic Microsystems has demonstrated up to 20m transmission using these three features. Other companies with similar devices include Broadcom and AMCC, although neither has shown equivalent DAC distances for similar power dissipation numbers.

While SFP+ is rapidly gaining traction for 10GbE HPC datacenter applications due to its lower cost and power characteristics, the alternative 10GBASE-T technology for 10GbE transmission over Category 6/7 twisted-pair copper cabling has been lagging in gaining market acceptance. 10GBASE-T has proven to be a challenging technology to implement in a cost- and power-effective way, because of the complexity of the signal processing required to overcome the bandwidth limitations and noise characteristics of the twisted-pair medium.

Other than link distance, 10GBASE-T suffers from several inherent disadvantages relative to SFP+ DAC. The most significant is power. Even using the latest IC process technology, 10GBASE-T PHYs dissipate around 6 W of power. This effectively has ruled out current 10GBASE-T offerings as a viable technology for the emerging generation of dual-port NIC cards and high-density switch technology, relegating it to single-port adapters and uplinks.

Another significant disadvantage of 10GBASE-T is its latency of approximately 2 µsec. This severely limits its applicability for IPC and storage workloads found in HPC datacenters. The latency of SFP+ is less than 0.1 µsec for all 10GbE standards, and much less than that for datacenter applications. In contrast, the combination of an SFP+ module and PHY for datacenter applications dissipates 1-1.5 W of power, depending on reach.

Next generation 10GBASE-T PHY development is underway today with several companies working on solutions to break the 4W per port power dissipation barrier. It remains to be seen how HPC environments adopt these solutions when they are available. Trade-offs include cost, power dissipation, latency and distance. In the meantime, short (15m and less), low-cost copper connections within the server rack and from server to end-of-row switch can be implemented with DAC and short-range optical interconnects.

About the Author

Saqib Jang is founder and principal at Margalla Communications, a Woodside, Calif.-based strategic and technical marketing consulting firm focused on storage and server networking. He can be contacted at saqibj@margallacomm.com.

Subscribe to HPCwire's Weekly Update!

Be the most informed person in the room! Stay ahead of the tech trends with industy updates delivered to you every week!

Nvidia Shares Recipe to Accelerate AI Cloud Adoption

May 29, 2017

In March, Nvidia revealed blueprints for a new open source Tesla GPU-based accelerator – HGX-1 – developed for clouds with Microsoft under its Project Olym Read more…

By Tiffany Trader

Doug Kothe on the Race to Build Exascale Applications

May 29, 2017

Ensuring there are applications ready to churn out useful science when the first U.S. exascale computers arrive in the 2021-2023 timeframe is Doug Kothe’s job Read more…

By John Russell

PRACEdays Reflects Europe’s HPC Commitment

May 25, 2017

More than 250 attendees and participants came together for PRACEdays17 in Barcelona last week, part of the European HPC Summit Week 2017, held May 15-19 at t Read more…

By Tiffany Trader

Russian Researchers Claim First Quantum-Safe Blockchain

May 25, 2017

The Russian Quantum Center today announced it has overcome the threat of quantum cryptography by creating the first quantum-safe blockchain, securing cryptocurr Read more…

By Doug Black

HPE Extreme Performance Solutions

Exploring the Three Models of Remote Visualization

The explosion of data and advancement of digital technologies are dramatically changing the way many companies do business. With the help of high performance computing (HPC) solutions and data analytics platforms, manufacturers are developing products faster, healthcare providers are improving patient care, and energy companies are improving planning, exploration, and production. Read more…

Google Debuts TPU v2 and will Add to Google Cloud

May 25, 2017

Not long after stirring attention in the deep learning/AI community by revealing the details of its Tensor Processing Unit (TPU), Google last week announced the Read more…

By John Russell

Nvidia CEO Predicts AI ‘Cambrian Explosion’

May 25, 2017

The processing power and cloud access to developer tools used to train machine-learning models are making artificial intelligence ubiquitous across computing pl Read more…

By George Leopold

PGAS Use will Rise on New H/W Trends, Says Reinders

May 25, 2017

If you have not already tried using PGAS, it is time to consider adding PGAS to the programming techniques you know. Partitioned Global Array Space, commonly kn Read more…

By James Reinders

Exascale Escapes 2018 Budget Axe; Rest of Science Suffers

May 23, 2017

President Trump's proposed $4.1 trillion FY 2018 budget is good for U.S. exascale computing development, but grim for the rest of science and technology spend Read more…

By Tiffany Trader

Nvidia Shares Recipe to Accelerate AI Cloud Adoption

May 29, 2017

In March, Nvidia revealed blueprints for a new open source Tesla GPU-based accelerator – HGX-1 – developed for clouds with Microsoft under its Project Olym Read more…

By Tiffany Trader

Doug Kothe on the Race to Build Exascale Applications

May 29, 2017

Ensuring there are applications ready to churn out useful science when the first U.S. exascale computers arrive in the 2021-2023 timeframe is Doug Kothe’s job Read more…

By John Russell

PRACEdays Reflects Europe’s HPC Commitment

May 25, 2017

More than 250 attendees and participants came together for PRACEdays17 in Barcelona last week, part of the European HPC Summit Week 2017, held May 15-19 at t Read more…

By Tiffany Trader

PGAS Use will Rise on New H/W Trends, Says Reinders

May 25, 2017

If you have not already tried using PGAS, it is time to consider adding PGAS to the programming techniques you know. Partitioned Global Array Space, commonly kn Read more…

By James Reinders

Exascale Escapes 2018 Budget Axe; Rest of Science Suffers

May 23, 2017

President Trump's proposed $4.1 trillion FY 2018 budget is good for U.S. exascale computing development, but grim for the rest of science and technology spend Read more…

By Tiffany Trader

Cray Offers Supercomputing as a Service, Targets Biotechs First

May 16, 2017

Leading supercomputer vendor Cray and datacenter/cloud provider the Markley Group today announced plans to jointly deliver supercomputing as a service. The init Read more…

By John Russell

HPE’s Memory-centric The Machine Coming into View, Opens ARMs to 3rd-party Developers

May 16, 2017

Announced three years ago, HPE’s The Machine is said to be the largest R&D program in the venerable company’s history, one that could be progressing tow Read more…

By Doug Black

What’s Up with Hyperion as It Transitions From IDC?

May 15, 2017

If you’re wondering what’s happening with Hyperion Research – formerly the IDC HPC group – apparently you are not alone, says Steve Conway, now senior V Read more…

By John Russell

Quantum Bits: D-Wave and VW; Google Quantum Lab; IBM Expands Access

March 21, 2017

For a technology that’s usually characterized as far off and in a distant galaxy, quantum computing has been steadily picking up steam. Just how close real-wo Read more…

By John Russell

Trump Budget Targets NIH, DOE, and EPA; No Mention of NSF

March 16, 2017

President Trump’s proposed U.S. fiscal 2018 budget issued today sharply cuts science spending while bolstering military spending as he promised during the cam Read more…

By John Russell

Google Pulls Back the Covers on Its First Machine Learning Chip

April 6, 2017

This week Google released a report detailing the design and performance characteristics of the Tensor Processing Unit (TPU), its custom ASIC for the inference Read more…

By Tiffany Trader

HPC Compiler Company PathScale Seeks Life Raft

March 23, 2017

HPCwire has learned that HPC compiler company PathScale has fallen on difficult times and is asking the community for help or actively seeking a buyer for its a Read more…

By Tiffany Trader

CPU-based Visualization Positions for Exascale Supercomputing

March 16, 2017

Since our first formal product releases of OSPRay and OpenSWR libraries in 2016, CPU-based Software Defined Visualization (SDVis) has achieved wide-spread adopt Read more…

By Jim Jeffers, Principal Engineer and Engineering Leader, Intel

Nvidia Responds to Google TPU Benchmarking

April 10, 2017

Last week, Google reported that its custom ASIC Tensor Processing Unit (TPU) was 15-30x faster for inferencing workloads than Nvidia's K80 GPU (see our coverage Read more…

By Tiffany Trader

Nvidia’s Mammoth Volta GPU Aims High for AI, HPC

May 10, 2017

At Nvidia's GPU Technology Conference (GTC17) in San Jose, Calif., this morning, CEO Jensen Huang announced the company's much-anticipated Volta architecture a Read more…

By Tiffany Trader

TSUBAME3.0 Points to Future HPE Pascal-NVLink-OPA Server

February 17, 2017

Since our initial coverage of the TSUBAME3.0 supercomputer yesterday, more details have come to light on this innovative project. Of particular interest is a ne Read more…

By Tiffany Trader

Leading Solution Providers

Facebook Open Sources Caffe2; Nvidia, Intel Rush to Optimize

April 18, 2017

From its F8 developer conference in San Jose, Calif., today, Facebook announced Caffe2, a new open-source, cross-platform framework for deep learning. Caffe2 is Read more…

By Tiffany Trader

Tokyo Tech’s TSUBAME3.0 Will Be First HPE-SGI Super

February 16, 2017

In a press event Friday afternoon local time in Japan, Tokyo Institute of Technology (Tokyo Tech) announced its plans for the TSUBAME3.0 supercomputer, which w Read more…

By Tiffany Trader

Is Liquid Cooling Ready to Go Mainstream?

February 13, 2017

Lost in the frenzy of SC16 was a substantial rise in the number of vendors showing server oriented liquid cooling technologies. Three decades ago liquid cooling Read more…

By Steve Campbell

MIT Mathematician Spins Up 220,000-Core Google Compute Cluster

April 21, 2017

On Thursday, Google announced that MIT math professor and computational number theorist Andrew V. Sutherland had set a record for the largest Google Compute Eng Read more…

By Tiffany Trader

US Supercomputing Leaders Tackle the China Question

March 15, 2017

As China continues to prove its supercomputing mettle via the Top500 list and the forward march of its ambitious plans to stand up an exascale machine by 2020, Read more…

By Tiffany Trader

HPC Technique Propels Deep Learning at Scale

February 21, 2017

Researchers from Baidu's Silicon Valley AI Lab (SVAIL) have adapted a well-known HPC communication technique to boost the speed and scale of their neural networ Read more…

By Tiffany Trader

DOE Supercomputer Achieves Record 45-Qubit Quantum Simulation

April 13, 2017

In order to simulate larger and larger quantum systems and usher in an age of "quantum supremacy," researchers are stretching the limits of today's most advance Read more…

By Tiffany Trader

Knights Landing Processor with Omni-Path Makes Cloud Debut

April 18, 2017

HPC cloud specialist Rescale is partnering with Intel and HPC resource provider R Systems to offer first-ever cloud access to Xeon Phi "Knights Landing" process Read more…

By Tiffany Trader

  • arrow
  • Click Here for More Headlines
  • arrow
Share This