Parallel Programming Is Here – Are You Ready?

By Nicole Hemsoth

June 23, 2009

Whether you’re simulating the extreme conditions inside an exploding star or designing an ergonomically innovative office chair, it’s a good bet that a high performance computing (HPC) system and some brain-bending programming will be involved.

The HPC system may be a supercomputer like the 1.6 petaflop Jaguar behemoth at Oak Ridge National Laboratory, or a cluster powered by off-the-shelf multicore components. Whatever the scale of the hardware and the scope of the application, developers will have to learn how to deal with the complexities of parallel programming to get the most out of their computational resources.

The need for parallel programming is being driven by advances in multicore architectures. This rapid and accelerating technology trend is creating an array of HPC systems that range from dual and quad core systems to supercomputers and clusters with tens, hundreds and thousands of cores. These platforms perform at teraflop and petaflop speeds on terabytes of data. Capable of tackling some of today’s most complex and pressing problems in engineering and science, these HPC systems are composed of a computational ecosystem that includes: scalable multicore architectures; fast, flexible, mammoth memories that can support many simultaneous threads; and high bandwidth I/O and communications.

Developers who have honed their parallel programming skills are ready to create applications that reach new levels of scalability, performance, safety and reliability. In particular, parallelism can be exploited in mechanical computer-aided engineering (MCAE) applications code for structural analysis and fluid dynamics, in computational chemistry and computational physics simulations and modeling, and industrial applications that run the gamut from oil and gas exploration to the design of high end golf equipment. For example, in the world of MCAE, Dale Layfield, engineer in Sun Microsystem’s ISV Engineering organization, points to the benefits realized by applying parallelization to NASTRAN, a venerable finite element analysis (FEA) program that has been around for about 40 years.

“NASTRAN is a highly compute and I/O intensive structural analysis program,” explains Layfield. “It lends itself well to being broken into smaller components and spreading those components across distributed computer clusters which substantially reduces throughput time. Distributed memory parallelism (DMP) helps eliminate the I/O bottleneck by dividing the analysis across a network of separate nodes. Multithreaded SMP (symmetric multiprocessing) allows you to make best use of the processing power within each node. SMP combined with DMP gives you the most bang for your buck.”

Like NASTRAN, many of the other complex applications designed to run on HPC systems rely on parallel programming methodologies to handle the increasing number of computationally intensive jobs involving massive amounts of data and memory.

As David Conover, Chief Technologist, Mechanical Products for ANSYS notes, “Among the major benefits of parallel programming are faster turnaround time and the ability to create higher fidelity simulations and modeling to solve engineering design challenges. Engineers applying finite element methods can create models with much higher spatial resolutions and more geometric detail. And they can build models that include entire assemblies, rather than just one small component. Then they can analyze the interactions between those components at a high level of detail. Because the users are able to perform more simultaneous tasks of increased complexity, the entire engineering process is far more productive. You just can’t achieve this level of functionality with applications that rely on sequential processes.”

By creating larger high fidelity models with greater geometric detail and subjecting them to detailed simulations of the physical forces that they will encounter in real life, engineers can reduce the need for expensive and time-consuming physical testing — the “build and break” approach. In addition, parallelization allows engineers to run more simulations in order to make design decisions earlier in the project lifecycle.

To achieve the speedup in applications performance, parallel programming uses threads that allow multiple operations to occur simultaneously. In an article in the May 20, 2009 HPCwire titled,“Parallel Programming: Some Fundamentals Concepts,” authors Shameen Akhter and Jason Roberts, both of Intel, commented, “The entire concept of parallel programming centers on the design, development and deployment of threads within an application and the coordination between threads and their respective operations.”

In short, parallel programming allows you to write scalable, flexible code that harnesses more HPC CPU resources and maximizes memory and I/O. It also allows users of the code — whether it’s you, a member of your organization’s engineering or scientific staff, or a customer – to solve problems that could not be solved using sequential programs, and solve them more quickly.

Parallel programming is not easy

However, as computer science professor Andrew S. Tanenbaum stated at the USENIX ’08 conference, “Sequential programming is really hard…the difficulty is that parallel programming is a step beyond that.”

Bronson Messer, a computational astrophysicist at Oak Ridge National Laboratory (ORNL), concurs. He points out that to do computing at the large scales he and his colleagues encounter daily, the application developer needs to understand the entire HPC ecosystem which includes multicore CPUs, high speed file and connective systems, and terabytes of memory that have to be swapped in and out at blinding speeds.

“Everything has to play together,” Messer says. “If there is a weak link at this scale, it will almost immediately be exposed. Your parallel code may run on a quad-core or eight-core system, but when you move up to thousands and tens of thousands of processors, your application may be dead in the water. Debugging code on this many processors is an unsolved problem.”

Messer also comments that building robustness and fault tolerance into the code is another major hurdle as the rate of data collection escalates. For example, the Sloan Digital Sky Survey telescope in Sun Spot, New Mexico is precisely mapping a swath of space some five billion light years in diameter, generating terabytes, even petabytes of data every night. And when CERN’s Large Hadron Collider finally comes on line, it will generate 700 megabytes of data every second.

These parallel programming speed bumps not only apply to code written for the huge supercomputers that are the workhorses of government labs and academia. Developers creating algorithms for the rapidly growing population of HPC grids, clusters and clouds that are infiltrating the enterprise are running into similar problems. And within industry the pressure is even more intense as companies seek to gain a competitive edge through the use of HPC.

When asked what he thought was the most difficult task facing developers working with this new programming paradigm, Scott J. Lasica, VP Technical Services Worldwide for HPC toolmaker Rogue Wave Software, was very clear. “Today’s developers need to learn to do multithreading, which, in my opinion, is one of the hardest — if not the hardest — task associated with software programming. Given the level of complexity we’re dealing with, it’s very easy to make mistakes and very hard to figure out where things went wrong.”

What’s a developer to do?

Lasica points out that fortunately there are a lot of tools available to help developers write multithreaded code in languages like C++ and Java — even Fortran. For example, a Java(TM) application can be dropped into an application server and the server will take care of the threading. Various new debugging tools also help ease the bumpy road to parallelization. But Lasica says that a thorough grounding in the intricacies of multithreading is essential for developers dealing with today’s complex distributed systems.

Reza Sadeghi, CTO of MSC Software agrees. And he also prescribes a major mind shift for today’s developers. “Developers tend to think serially, not in terms of what they can do with multiple CPUs,” he explains. “And even if they are thinking parallel, they are still in the realm of dual, quad or eight cores. But the new HPC systems are raising the bar to encompass hundreds and thousands of cores as well as multicore sub architectures. It’s a whole new way of building algorithms and solving complex loops. By adopting this different mindset, backed up by learning all you can about parallelism and multithreading, you can make optimum use of the many diagnostic tools that are now available and build successful HPC applications.”

Advanced programming models also help ease the developer’s path. Among the most popular are OpenMP for shared memory programming, and MPI (message passing interface) for distributed memory programming.

ORNL’s Messer adds that given the rapid pace of technology, it is important for developers to create algorithms that will scale far beyond their current systems. “If you know apriori that your algorithm won’t scale, you have an immediate problem,” he says. “With today’s multicore HPC systems, you are dealing with a deeper and more complicated memory hierarchy in addition to the problems inherent in multithreading. Despite advances in OS, compilers and programming models, you still may have to manage some of that hierarchy yourself. The results are worth it.”

Continuing education is key

Addison Snell, general manager of Tabor Research, comments that developers need to familiarize themselves with how to optimize software on multicore HPC systems. “I’m not sure the latest generation of software engineers has been trained to cope with advanced parallelism – there is a serious question of readiness in the software community,” he says.

It is certain that as the world of high performance computing heats up, and multicore, multithreaded systems move into the enterprise, those individuals who are familiar with parallel programming will command a favorable position in today’s rough and tumble job market. Application developers should be very familiar with the principles of parallel programming, including how to handle multithreading. They should also be acquainted with parallel tools, and be able to build thread-safe component interfaces. Also, both test engineers and field engineers should have parallel debugging skills and be familiar with parallel analysis and profiling tools.

In order to help developers and engineers meet the challenges posed by parallel programming, Sun Microsystems is offering a series of seminars called “An Introduction to Parallel Programming” discussing parallel programming as a fundamental of application development. Log on weekly to access each of these seven modules presented by mathematician and Sun senior staff engineer Ruud van der Pas. http://www.sun.com/solutions/hpc/development.jsp.

Subscribe to HPCwire's Weekly Update!

Be the most informed person in the room! Stay ahead of the tech trends with industy updates delivered to you every week!

UCSD, AIST Forge Tighter Alliance with AI-Focused MOU

January 18, 2018

The rich history of collaboration between UC San Diego and AIST in Japan is getting richer. The organizations entered into a five-year memorandum of understanding on January 10. The MOU represents the continuation of a 1 Read more…

By Tiffany Trader

New Blueprint for Converging HPC, Big Data

January 18, 2018

After five annual workshops on Big Data and Extreme-Scale Computing (BDEC), a group of international HPC heavyweights including Jack Dongarra (University of Tennessee), Satoshi Matsuoka (Tokyo Institute of Technology), Read more…

By John Russell

Researchers Measure Impact of ‘Meltdown’ and ‘Spectre’ Patches on HPC Workloads

January 17, 2018

Computer scientists from the Center for Computational Research, State University of New York (SUNY), University at Buffalo have examined the effect of Meltdown and Spectre security updates on the performance of popular H Read more…

By Tiffany Trader

HPE Extreme Performance Solutions

HPE and NREL Take Steps to Create a Sustainable, Energy-Efficient Data Center with an H2 Fuel Cell

As enterprises attempt to manage rising volumes of data, unplanned data center outages are becoming more common and more expensive. As the cost of downtime rises, enterprises lose out on productivity and valuable competitive advantage without access to their critical data. Read more…

Fostering Lustre Advancement Through Development and Contributions

January 17, 2018

Six months after organizational changes at Intel's High Performance Data (HPDD) division, most in the Lustre community have shed any initial apprehension around the potential changes that could affect or disrupt Lustre Read more…

By Carlos Aoki Thomaz

UCSD, AIST Forge Tighter Alliance with AI-Focused MOU

January 18, 2018

The rich history of collaboration between UC San Diego and AIST in Japan is getting richer. The organizations entered into a five-year memorandum of understandi Read more…

By Tiffany Trader

New Blueprint for Converging HPC, Big Data

January 18, 2018

After five annual workshops on Big Data and Extreme-Scale Computing (BDEC), a group of international HPC heavyweights including Jack Dongarra (University of Te Read more…

By John Russell

Researchers Measure Impact of ‘Meltdown’ and ‘Spectre’ Patches on HPC Workloads

January 17, 2018

Computer scientists from the Center for Computational Research, State University of New York (SUNY), University at Buffalo have examined the effect of Meltdown Read more…

By Tiffany Trader

Fostering Lustre Advancement Through Development and Contributions

January 17, 2018

Six months after organizational changes at Intel's High Performance Data (HPDD) division, most in the Lustre community have shed any initial apprehension aroun Read more…

By Carlos Aoki Thomaz

When the Chips Are Down

January 11, 2018

In the last article, "The High Stakes Semiconductor Game that Drives HPC Diversity," I alluded to the challenges facing the semiconductor industry and how that may impact the evolution of HPC systems over the next few years. I thought I’d lift the covers a little and look at some of the commercial challenges that impact the component technology we use in HPC. Read more…

By Dairsie Latimer

How Meltdown and Spectre Patches Will Affect HPC Workloads

January 10, 2018

There have been claims that the fixes for the Meltdown and Spectre security vulnerabilities, named the KPTI (aka KAISER) patches, are going to affect applicatio Read more…

By Rosemary Francis

Momentum Builds for US Exascale

January 9, 2018

2018 looks to be a great year for the U.S. exascale program. The last several months of 2017 revealed a number of important developments that help put the U.S. Read more…

By Alex R. Larzelere

ANL’s Rick Stevens on CANDLE, ARM, Quantum, and More

January 8, 2018

Late last year HPCwire caught up with Rick Stevens, associate laboratory director for computing, environment and life Sciences at Argonne National Laboratory, f Read more…

By John Russell

Inventor Claims to Have Solved Floating Point Error Problem

January 17, 2018

"The decades-old floating point error problem has been solved," proclaims a press release from inventor Alan Jorgensen. The computer scientist has filed for and Read more…

By Tiffany Trader

US Coalesces Plans for First Exascale Supercomputer: Aurora in 2021

September 27, 2017

At the Advanced Scientific Computing Advisory Committee (ASCAC) meeting, in Arlington, Va., yesterday (Sept. 26), it was revealed that the "Aurora" supercompute Read more…

By Tiffany Trader

Japan Unveils Quantum Neural Network

November 22, 2017

The U.S. and China are leading the race toward productive quantum computing, but it's early enough that ultimate leadership is still something of an open questi Read more…

By Tiffany Trader

AMD Showcases Growing Portfolio of EPYC and Radeon-based Systems at SC17

November 13, 2017

AMD’s charge back into HPC and the datacenter is on full display at SC17. Having launched the EPYC processor line in June along with its MI25 GPU the focus he Read more…

By John Russell

Nvidia Responds to Google TPU Benchmarking

April 10, 2017

Nvidia highlights strengths of its newest GPU silicon in response to Google's report on the performance and energy advantages of its custom tensor processor. Read more…

By Tiffany Trader

IBM Begins Power9 Rollout with Backing from DOE, Google

December 6, 2017

After over a year of buildup, IBM is unveiling its first Power9 system based on the same architecture as the Department of Energy CORAL supercomputers, Summit a Read more…

By Tiffany Trader

Fast Forward: Five HPC Predictions for 2018

December 21, 2017

What’s on your list of high (and low) lights for 2017? Volta 100’s arrival on the heels of the P100? Appearance, albeit late in the year, of IBM’s Power9? Read more…

By John Russell

Chip Flaws ‘Meltdown’ and ‘Spectre’ Loom Large

January 4, 2018

The HPC and wider tech community have been abuzz this week over the discovery of critical design flaws that impact virtually all contemporary microprocessors. T Read more…

By Tiffany Trader

Leading Solution Providers

Perspective: What Really Happened at SC17?

November 22, 2017

SC is over. Now comes the myriad of follow-ups. Inboxes are filled with templated emails from vendors and other exhibitors hoping to win a place in the post-SC thinking of booth visitors. Attendees of tutorials, workshops and other technical sessions will be inundated with requests for feedback. Read more…

By Andrew Jones

Tensors Come of Age: Why the AI Revolution Will Help HPC

November 13, 2017

Thirty years ago, parallel computing was coming of age. A bitter battle began between stalwart vector computing supporters and advocates of various approaches to parallel computing. IBM skeptic Alan Karp, reacting to announcements of nCUBE’s 1024-microprocessor system and Thinking Machines’ 65,536-element array, made a public $100 wager that no one could get a parallel speedup of over 200 on real HPC workloads. Read more…

By John Gustafson & Lenore Mullin

Delays, Smoke, Records & Markets – A Candid Conversation with Cray CEO Peter Ungaro

October 5, 2017

Earlier this month, Tom Tabor, publisher of HPCwire and I had a very personal conversation with Cray CEO Peter Ungaro. Cray has been on something of a Cinderell Read more…

By Tiffany Trader & Tom Tabor

Flipping the Flops and Reading the Top500 Tea Leaves

November 13, 2017

The 50th edition of the Top500 list, the biannual publication of the world’s fastest supercomputers based on public Linpack benchmarking results, was released Read more…

By Tiffany Trader

How Meltdown and Spectre Patches Will Affect HPC Workloads

January 10, 2018

There have been claims that the fixes for the Meltdown and Spectre security vulnerabilities, named the KPTI (aka KAISER) patches, are going to affect applicatio Read more…

By Rosemary Francis

GlobalFoundries, Ayar Labs Team Up to Commercialize Optical I/O

December 4, 2017

GlobalFoundries (GF) and Ayar Labs, a startup focused on using light, instead of electricity, to transfer data between chips, today announced they've entered in Read more…

By Tiffany Trader

HPC Chips – A Veritable Smorgasbord?

October 10, 2017

For the first time since AMD's ill-fated launch of Bulldozer the answer to the question, 'Which CPU will be in my next HPC system?' doesn't have to be 'Whichever variety of Intel Xeon E5 they are selling when we procure'. Read more…

By Dairsie Latimer

Nvidia, Partners Announce Several V100 Servers

September 27, 2017

Here come the Volta 100-based servers. Nvidia today announced an impressive line-up of servers from major partners – Dell EMC, Hewlett Packard Enterprise, IBM Read more…

By John Russell

  • arrow
  • Click Here for More Headlines
  • arrow
Share This