A Trio of HPC Offerings Unveiled at ISC

By Michael Feldman

July 1, 2009

Last week’s International Supercomputing Conference (ISC’09) was a convenient excuse for vendors to announce a raft of new products, but three, in particular, stood out. Storage vendor DataDirect Networks (DDN) launched its new “Storage Fusion Architecture” that gives it an IOPS story; Mellanox jumped into the InfiniBand switch and fabric management business in a big way; and PGI released its first C and Fortran compilers with support for GPU acceleration.

DataDirect Does IOPS

DataDirect Network’s historical leadership in high throughput storage has kept it atop the supercomputing world. Today, eight of the top 10 systems use DDN gear, including the petaflop-capable Jaguar supercomputer at Oak Ridge National Lab. Storage demand continues to grow in HPC, but it’s growing even faster in other areas like Web services and media content.

With that in mind, DDN is looking to tap into a bigger slice of that market with a revamped architecture. In truth, DataDirect has already begun this transition. According to DDN senior director of product management Josh Goldenhar, the revenue breakdown for the company is now 45 percent HPC, 30 percent rich media, and most of the remainder Web 2.0 type applications.

With its next-generation storage platform, called Storage Fusion Architecture (SFA), the company is looking to add a high performance random access capability on top of high performance throughput, the idea being that I/O per second (IOPS) is the critical metric for all this unstructured data that is spreading across the storage landscape. Even in HPC, high IOPS is becoming a necessity. Multicore computing means structured data access is becoming randomized, since I/O now tends to be performed across multiple threads. In particular, metadata is becoming the choke point for large clustered file systems since it tends to be accessed randomly.

The SFA design is based on a controller couplet pair that can support up to 1,200 disk drives, which can be a mix of SATA, SAS, and SSD devices. That mean that with the new 2 TB SATA drives, a single controller pair can drive 2.4 petabytes of storage.

Data throughput for a single controller is 10 GB/second — significantly better than the 6 GB/second provided by the current generation S2A design. But the real story is the IOPS. An SFA controller can deliver up to 1 million IOPS to cache storage and 300 thousand IOPS to disk. The high disk IOPS will be especially important to users who want to get the most out of attached SSD devices, which support much faster read/write speeds than their spinning brethren.

The SFA controller hardware itself is very different from the current generation S2A technology. DDN has made the jump to a CPU-based architecture (in this case Intel Nehalem), dumping the FPGAs it relied on in previous generations. By doing this, the company is able to take advantage of standard x86 technology, PCIe Gen2, and DDR3 memory. Part of the memory (16 GB) is used for storage cache, which is why DDN was able to achieve such high rates of cache IOPS. Perhaps more importantly, the standard platform will allow DDN to create new features much more easily than on an FPGA-based platform. “We are poised to take advantage of the very same advances in CPU technology that have been aiding our clients, in the storage itself, with a completely multithreaded storage engine under the covers,” said Goldenhar.

Early SFA products are in customer trials in California and Europe, with general availability scheduled for September.

Mellanox Adds Big InfiniBand Switches, Fabric Management Software

Also at ISC, Mellanox Technologies launched its first director-class InfiniBand switches and fabric management suite. The IS5000 modular switches support from 108 to 648 QDR ports and are paired with the company’s new FabricIT management software to support large scaled-out clusters comprised of thousand or tens of thousands of nodes. The IS5000 is a true modular architecture: the platform makes use of common leaf and spine components, as well as interchangeable power supplies and fans. Mellanox has also added a new 36-port fixed switch, which is able to support the fabric management software. The older 36-port MTS3600 switch was externally managed since it lacked a CPU.

With Mellanox’s expanded portfolio, the InfiniBand switch and fabric management space is starting to look ever more crowded. The other InfiniBand players — Voltaire, QLogic and Sun Microsystems — have all recently introduced QDR director-class switches of their own. QLogic has the largest general-purpose switch to date, with up to 864 ports; the other three vendors top out at 648 ports (not including the 3,456-port Magnum switch Sun reserves for Constellation supers).

As Mellanox has moved up the food chain, the situation has become a bit tricky. With the addition of a fully-populated switch portfolio, the company’s current partners — Sun and Voltaire — are ostensibly competitors. Mellanox provides its own InfiniBand chips to Sun and Voltaire, as well as using them natively. (QLogic also produces InfiniBand silicon, but keeps the technology in-house for its own products.) Although InfiniBand use is expanding, it’s not clear if there will be enough market space to support multiple vendors with similar offerings. According to John Monson, VP of marketing at Mellanox, vendors are carving out their own niches in the InfiniBand market with regard to vertical segments and server OEM relationships, and have different value propositions. “There’s plenty of room in the market for that competition, but there will be some overlap,” he admits.

With the addition of the director-class switches and the fabric management software to its traditional portfolio of host channel adapters, device silicon, gateways, and Ethernet product offerings, Mellanox has filled in its product set rather completely. The addition of the fabric management suite was a big step for the company. As InfiniBand use expands to less traditional HPC users and with increasing cluster sizes, ease of management will be much more important. And to the extent InfiniBand can make inroads into the enterprise and cloud computing realm, a fabric management capability becomes a must-have feature.

PGI Adds GPU Computing Support to Compilers

A year and a half ago, compiler vendor PGI (aka The Portland Group) came to the conclusion that heterogenous computing, via accelerators, would probably be the next big thing in technical computing, and began a strategy to support that model in its software tools. PGI Release 9.0 brings the first implementation of that work to fruition, with the support of NVIDIA GPUs for general-purpose computing via the company’s C and Fortran compilers.

Unless you’re brand new to HPC, you know that GPU computing has become the accelerator of choice on a range of HPC platforms — from personal workstations and small clusters to large supercomputers. Accelerating HPC applications with the latest GPUs can result in performance increases of one or two orders of magnitude compared to CPU-only execution. NVIDIA has largely been driving this new model, using its own CUDA development environment as the software platform.

Although CUDA source code is written in C, functionally it represents a rather low-level interface to GPU computing. PGI’s idea is to hide the GPU device management details of CUDA, and let the compiler generate GPU code directly from the C or Fortran application source. In practice though, this is not completely transparent to the developer. The model used by PGI is based on directives that the programmer must insert into the source code at the appropriate spots — similar to what’s done with OpenMP directives. The goal is to locate all the computationally-intensive portions of the code that can be parallelized on GPU hardware and direct the compiler to generate the low-level code. The most common directive is called ACC REGION. For example:

SUBROUTINE SAXPY (A,X,Y,N)
    INTEGER N
    REAL A,X(N),Y(N)
!$ACC REGION
    DO I = 1, N
       X(I) = A*X(I) + Y(I)
    ENDDO
 !$ACC END REGION
 END

The loop inside the ACC REGION will be parallelized by the compiler and the GPU code will be bundled into the executable file alongside the regular CPU code. At runtime the parallelized code will be downloaded to the GPU and executed natively, with all the data transfers to and from the device managed automatically. Under the covers, the compiler is employing CUDA as the low-level interface to do the device-specific work. Note that if a GPU is not detected, the runtime falls back to the CPU version of the code.

The directives are not the whole story. To squeeze maximum performance from the GPU, there is usually some source tweaking required in order to optimize the runtime behavior. The GPU memory system in particular is vastly different from the typical CPU, and the programmer must recognize that matching data to the on-board memory is going to boost performance. “The compiler is not magic,” explained Doug Miles, director of The Portland Group. “It can’t automatically detect, offload and optimize appropriate kernels. It can do a lot of the busywork. But the programmer is going to have to be in the loop.”

The first PGI implementation is Linux only and assumes an x86 CPU host with a CUDA-capable NVIDIA GPU. There are a few other limitations, mostly associated with the fact that CUDA is not really multi-GPU aware, so execution is currently limited to one GPU per application. PGI is also “investigating” a GPU implementation for AMD’s FireStream computing platform, but will need a working OpenCL implementation for that target.

The accelerator capability in the compilers is available at no charge until the end of 2009 for users with a working PGI Linux license. Starting in 2010, the acceleration features will require a license upgrade, with pricing to be determined. For more information, check out the FAQ on PGI’s Web site at http://www.pgroup.com/resources/accel.htm.

Subscribe to HPCwire's Weekly Update!

Be the most informed person in the room! Stay ahead of the tech trends with industy updates delivered to you every week!

DARPA Continues Investment in Post-Moore’s Technologies

July 24, 2017

The U.S. military long ago ceded dominance in electronics innovation to Silicon Valley, the DoD-backed powerhouse that has driven microelectronic generation for decades. With Moore's Law clearly running out of steam, the Read more…

By George Leopold

Graphcore Readies Launch of 16nm Colossus-IPU Chip

July 20, 2017

A second $30 million funding round for U.K. AI chip developer Graphcore sets up the company to go to market with its “intelligent processing unit” (IPU) in 2017 with scale-up production for enterprise datacenters and Read more…

By Tiffany Trader

Trinity Supercomputer’s Haswell and KNL Partitions Are Merged

July 19, 2017

Trinity supercomputer’s two partitions – one based on Intel Xeon Haswell processors and the other on Xeon Phi Knights Landing – have been fully integrated are now available for use on classified work in the Nationa Read more…

By HPCwire Staff

Fujitsu Continues HPC, AI Push

July 19, 2017

Summer is well under way, but the so-called summertime slowdown, linked with hot temperatures and longer vacations, does not seem to have impacted Fujitsu's output. The Japanese multinational has made a raft of HPC and A Read more…

By Tiffany Trader

HPE Extreme Performance Solutions

HPE Servers Deliver High Performance Remote Visualization

Whether generating seismic simulations, locating new productive oil reservoirs, or constructing complex models of the earth’s subsurface, energy, oil, and gas (EO&G) is a highly data-driven industry. Read more…

Researchers Use DNA to Store and Retrieve Digital Movie

July 18, 2017

From abacus to pencil and paper to semiconductor chips, the technology of computing has always been an ever-changing target. The human brain is probably the computer we use most (hopefully) and understand least. This mon Read more…

By John Russell

The Exascale FY18 Budget – The Next Step

July 17, 2017

On July 12, 2017, the U.S. federal budget for its Exascale Computing Initiative (ECI) took its next step forward. On that day, the full Appropriations Committee of the House of Representatives voted to accept the recomme Read more…

By Alex R. Larzelere

Summer Reading: IEEE Spectrum’s Chip Hall of Fame

July 17, 2017

Take a trip down memory lane – the Mostek MK4096 4-kilobit DRAM, for instance. Perhaps processors are more to your liking. Remember the Sh-Boom processor (1988), created by Russell Fish and Chuck Moore, and named after Read more…

By John Russell

Women in HPC Luncheon Shines Light on Female-Friendly Hiring Practices

July 13, 2017

The second annual Women in HPC luncheon was held on June 20, 2017, during the International Supercomputing Conference in Frankfurt, Germany. The luncheon provides participants the opportunity to network with industry lea Read more…

By Tiffany Trader

Graphcore Readies Launch of 16nm Colossus-IPU Chip

July 20, 2017

A second $30 million funding round for U.K. AI chip developer Graphcore sets up the company to go to market with its “intelligent processing unit” (IPU) in Read more…

By Tiffany Trader

Fujitsu Continues HPC, AI Push

July 19, 2017

Summer is well under way, but the so-called summertime slowdown, linked with hot temperatures and longer vacations, does not seem to have impacted Fujitsu's out Read more…

By Tiffany Trader

Researchers Use DNA to Store and Retrieve Digital Movie

July 18, 2017

From abacus to pencil and paper to semiconductor chips, the technology of computing has always been an ever-changing target. The human brain is probably the com Read more…

By John Russell

The Exascale FY18 Budget – The Next Step

July 17, 2017

On July 12, 2017, the U.S. federal budget for its Exascale Computing Initiative (ECI) took its next step forward. On that day, the full Appropriations Committee Read more…

By Alex R. Larzelere

Women in HPC Luncheon Shines Light on Female-Friendly Hiring Practices

July 13, 2017

The second annual Women in HPC luncheon was held on June 20, 2017, during the International Supercomputing Conference in Frankfurt, Germany. The luncheon provid Read more…

By Tiffany Trader

Satellite Advances, NSF Computation Power Rapid Mapping of Earth’s Surface

July 13, 2017

New satellite technologies have completely changed the game in mapping and geographical data gathering, reducing costs and placing a new emphasis on time series Read more…

By Ken Chiacchia and Tiffany Jolley

Intel Skylake: Xeon Goes from Chip to Platform

July 13, 2017

With yesterday’s New York unveiling of the new “Skylake” Xeon Scalable processors, Intel made multiple runs at multiple competitive threats and strategic Read more…

By Doug Black

Perverse Incentives? How Economics (Mis-)shaped Academic Science

July 12, 2017

The unintended consequences of how we fund academic research—in the U.S. and elsewhere—are strangling innovation, putting universities into debt and creatin Read more…

By Ken Chiacchia, Senior Science Writer, Pittsburgh Supercomputing Center

Google Pulls Back the Covers on Its First Machine Learning Chip

April 6, 2017

This week Google released a report detailing the design and performance characteristics of the Tensor Processing Unit (TPU), its custom ASIC for the inference Read more…

By Tiffany Trader

Nvidia Responds to Google TPU Benchmarking

April 10, 2017

Nvidia highlights strengths of its newest GPU silicon in response to Google's report on the performance and energy advantages of its custom tensor processor. Read more…

By Tiffany Trader

Quantum Bits: D-Wave and VW; Google Quantum Lab; IBM Expands Access

March 21, 2017

For a technology that’s usually characterized as far off and in a distant galaxy, quantum computing has been steadily picking up steam. Just how close real-wo Read more…

By John Russell

HPC Compiler Company PathScale Seeks Life Raft

March 23, 2017

HPCwire has learned that HPC compiler company PathScale has fallen on difficult times and is asking the community for help or actively seeking a buyer for its a Read more…

By Tiffany Trader

Trump Budget Targets NIH, DOE, and EPA; No Mention of NSF

March 16, 2017

President Trump’s proposed U.S. fiscal 2018 budget issued today sharply cuts science spending while bolstering military spending as he promised during the cam Read more…

By John Russell

CPU-based Visualization Positions for Exascale Supercomputing

March 16, 2017

In this contributed perspective piece, Intel’s Jim Jeffers makes the case that CPU-based visualization is now widely adopted and as such is no longer a contrarian view, but is rather an exascale requirement. Read more…

By Jim Jeffers, Principal Engineer and Engineering Leader, Intel

Nvidia’s Mammoth Volta GPU Aims High for AI, HPC

May 10, 2017

At Nvidia's GPU Technology Conference (GTC17) in San Jose, Calif., this morning, CEO Jensen Huang announced the company's much-anticipated Volta architecture a Read more…

By Tiffany Trader

Facebook Open Sources Caffe2; Nvidia, Intel Rush to Optimize

April 18, 2017

From its F8 developer conference in San Jose, Calif., today, Facebook announced Caffe2, a new open-source, cross-platform framework for deep learning. Caffe2 is the successor to Caffe, the deep learning framework developed by Berkeley AI Research and community contributors. Read more…

By Tiffany Trader

Leading Solution Providers

How ‘Knights Mill’ Gets Its Deep Learning Flops

June 22, 2017

Intel, the subject of much speculation regarding the delayed, rewritten or potentially canceled “Aurora” contract (the Argonne Lab part of the CORAL “ Read more…

By Tiffany Trader

Reinders: “AVX-512 May Be a Hidden Gem” in Intel Xeon Scalable Processors

June 29, 2017

Imagine if we could use vector processing on something other than just floating point problems.  Today, GPUs and CPUs work tirelessly to accelerate algorithms Read more…

By James Reinders

Russian Researchers Claim First Quantum-Safe Blockchain

May 25, 2017

The Russian Quantum Center today announced it has overcome the threat of quantum cryptography by creating the first quantum-safe blockchain, securing cryptocurrencies like Bitcoin, along with classified government communications and other sensitive digital transfers. Read more…

By Doug Black

MIT Mathematician Spins Up 220,000-Core Google Compute Cluster

April 21, 2017

On Thursday, Google announced that MIT math professor and computational number theorist Andrew V. Sutherland had set a record for the largest Google Compute Engine (GCE) job. Sutherland ran the massive mathematics workload on 220,000 GCE cores using preemptible virtual machine instances. Read more…

By Tiffany Trader

Google Debuts TPU v2 and will Add to Google Cloud

May 25, 2017

Not long after stirring attention in the deep learning/AI community by revealing the details of its Tensor Processing Unit (TPU), Google last week announced the Read more…

By John Russell

Groq This: New AI Chips to Give GPUs a Run for Deep Learning Money

April 24, 2017

CPUs and GPUs, move over. Thanks to recent revelations surrounding Google’s new Tensor Processing Unit (TPU), the computing world appears to be on the cusp of Read more…

By Alex Woodie

Six Exascale PathForward Vendors Selected; DoE Providing $258M

June 15, 2017

The much-anticipated PathForward awards for hardware R&D in support of the Exascale Computing Project were announced today with six vendors selected – AMD Read more…

By John Russell

Top500 Results: Latest List Trends and What’s in Store

June 19, 2017

Greetings from Frankfurt and the 2017 International Supercomputing Conference where the latest Top500 list has just been revealed. Although there were no major Read more…

By Tiffany Trader

  • arrow
  • Click Here for More Headlines
  • arrow
Share This