Compilers and More: OpenCL Promises and Potential

By Michael Wolfe

September 10, 2009

OpenCL was introduced with great fanfare and promise. Apple has served a key role, perhaps the key role, in pushing OpenCL to ratification and public release. In fact, Apple has apparently filed for trademark protection on OpenCL technology, presumably (or hopefully) to prevent anyone else from claiming prior art and thereby preventing Apple from using it themselves. The development of OpenCL included dozens of industrial and institutional partners, including AMD, ARM, IBM, Intel, NVIDIA, and Texas Instruments.

The excitement is intensified by a quote from Steve Jobs saying, “It’s way beyond what NVIDIA or anyone else has, and it’s really simple,” (more on this later), and the first line on the Khronos OpenCL page: “OpenCL is the first open, royalty-free standard for cross-platform, parallel programming of modern processors found in personal computers, servers and handheld/embedded devices.” That last comment leaves me rankled, since I’m personally deeply involved in OpenMP, another open, royalty-free standard for parallel programming of modern processors; perhaps there are enough adjectival phrases in the OpenCL statement to distinguish it. At the SC08 OpenCL Technical Briefing, Tim Mattson from Intel, who is also deeply involved in OpenMP language development, gushed about how we now finally have a portable parallel programming model, and predicted that half the people in the room would be using OpenCL by the next SC conference. I guess we’ll see in just a couple of months.

So, given all the hype, what can we expect from OpenCL? Is it really simple? Is it portable? Will it replace other parallel programming models? It’s still a little early; we’ve seen a multicore demonstration of OpenCL from AMD, a limited developer release from NVIDIA, and Apple is planning to release its next generation operating system in September, including OpenCL support. Yet we can prognosticate, given what we know about the language and related technologies.

Is it simple?

Simple is a loaded term. One can claim anything is simple if it’s simpler than something else that’s even more complex. But I’ve said before that parallel programming is hard, and is going to remain so. Perhaps that’s overstating the case: we can probably make it easy to write parallel programs that perform badly, but I’m assuming that isn’t the intent and is obviously unacceptable.

So, is there a metric by which we can claim that OpenCL is simple? I’m going to give a qualified no. In OpenCL, you have a host and one or more compute devices; you have a host program that launches kernels; you have task parallelism and data parallelism, work-items and work-groups; you have contexts and command queues; you have global memory, local memory, and private memory, not to mention constant memory, with different consistency models across the memory types; you have buffer objects, image objects, and sampler objects; and you have language restrictions and language extensions. It’s not simple.

Over fifty years of programming language development has led us to expect certain features in our programming environment, such as simple access to modular programming (procedures, argument passing, linkers), which are not so well represented in OpenCL. There’s no linker for GPU kernels in OpenCL; you must include library calls to build a device program and extract a handle to the kernel function. There’s no direct function call to the kernel; you must set up the arguments one at a time with a series of library calls. The OpenCL strategy was to not perturb the host programming language with additional keywords or syntax, but to encapsulate additional functionality in a host-side library. You can expect any number of OpenCL preprocessors to convert a higher-level representation (a la NVIDIA’s CUDA) to the lower-level OpenCL. If I haven’t convinced you that OpenCL isn’t simple, look at an OpenCL example program, in this case to compute the sum of a vector of numbers (provided by Apple).

So, what’s my qualification? If you had looked at the hoops programmers had to jump through to program GPUs for general purpose computing before OpenCL and CUDA, you’d agree that these languages are a very large step in the right direction. Much simpler, though not really simple.

Is it portable?

Again, we should define our metric. We’ve grown accustomed to being able to write programs that will run across a wide variety of target systems with almost no modifications. Compiled languages (Fortran, C, C++) will require a recompile for a new processor or operating system, and may need changes for system calls. Just-in-time platforms (for Java, C#) and interpreted languages (Perl, Python) don’t even need that.

However, in the HPC world we want more than the program to just work; we want it to deliver high performance. The gold standard in this regard has been vectorizing compilers. When the Cray-1 was delivered in 1976, the primary method to access the vector instructions was to use the vectorizing Fortran compiler, CFT (Cray Fortran Translator). The compiler generated a vectorization listing telling the user what loops were or were not vectorized; if there were vector hazards (data dependences) or other limitations (IO statements, procedure calls, conditionals), the listing would call them out. Programmers learned to read the listing and, if the loop were critical to performance, rewrite the loop so it would vectorize. They were rewarded with vector performance on that application, and they learned how to write code that would vectorize for their next project. Moreover, and this is the key, those programs would also vectorize on subsequent generations of vector machines from Fujitsu, NEC, IBM, Convex, Alliant, Hitachi, and others. Those vector programs were not just portable, they were performance portable.

Side note: We use exactly the same compiler technology for today’s packed instruction set extensions, like SSE on X64 and Altivec on IBM Power. And enjoy the same performance portability benefits as well.

So, are OpenCL programs going to be performance portable or not? Sadly, not. An OpenCL kernel is a low-level representation of the work to be done on the accelerator or GPU itself. To optimize the performance, you must know and take advantage of device-specific information such as the optimal number of work-items in a work-group, the amount of local memory and perhaps the number of banks, and trade-offs between parallelism and efficiency. An optimized kernel for one device may or may not perform well on another, but is unlikely to be optimal for that second device. This is not a condemnation of OpenCL, or even a failure of the language. It was intended and designed to be a low-level, high-performance, close-to-the-metal, efficient programming interface, borrowing phrases. The intent is apparently that OpenCL will support an ecosystem of tools, middleware and applications, not to be the portable parallel abstraction. Even though the kernels are not performance portable, even if you have to tune your kernels for each device, the ability to write your kernels for different devices in the same language is a great leap forward from where we are today.

Will it replace or supersede other parallel programming models?

What other models might it replace? The dominant parallel programming models are MPI for cluster programming and OpenMP for shared memory programming. Many others exist: Java threads, TBB, Map/Reduce, Unified Parallel C, Cilk, and many more, but let’s stick with the classics.

MPI programming targets a network of homogeneous or heterogeneous nodes running in MIMD mode, each communicating and synchronizing with other nodes, one-to-one or collectively. The node program is a complete scalar program; from the language perspective, it just happens to use a library that happens to communicate through I/O channels with other copies of itself that just happen to be running at the same time. OpenMP programming targets a homogeneous shared-memory multiprocessor running in MIMD mode, with a master thread that controls when the other threads running on other processors start to cooperate to help with parallel work. Unlike an MPI node program, the OpenMP program is a global program; it describes all the work to be done, with directives telling the compiler which parts to run on the master thread, which parts to run redundantly on all threads, and (most importantly) which parts to split up among the worker threads.

OpenCL kernel routines are like MPI node programs; they describe the work to be done by one thread. The OpenCL host program is like the OpenMP master thread; it controls the execution of the kernels and the parallel threads. OpenCL uses shared memory in the compute devices, like OpenMP, but has a weaker consistency model and weaker synchronization semantics. The requirement to break up the parallel part of the program into kernels, with a single host thread acting as master, and the shared memory among the compute devices, makes OpenCL an unlikely candidate to replace MPI on large network supercomputers. The separate host and compute device memory, very limited synchronization, and non-incremental nature make it unlikely to replace OpenMP as the preferred method to program multicore or other shared memory multiprocessors.

Will OpenCL replace CUDA?

This is a more interesting question. The OpenCL JumpStart Guide from NVIDIA points out that CUDA has two library API layers. There is a Runtime API, which includes some language syntax extensions, and which automates some of the handshaking between the host thread and the compute device. There is also a lower level, Driver API, which requires the programmer to manage all the interaction between the host and the device. OpenCL is quite similar in many respects to CUDA using the Driver API, and the above mentioned JumpStart Guide gives the correspondence between the two.

Will NVIDIA adopt OpenCL in place of CUDA? That would be silly; NVIDIA already has a large contingent of CUDA users, and CUDA C does include the higher level, easier-to-use Runtime API. NVIDIA has had a two-year head start in the GPU/Accelerator programming game. While OpenCL has the potential to level the playing field somewhat, the CUDA Runtime API gives NVIDIA a slight edge in programmability, so NVIDIA will not likely abandon it.

Does OpenCL have any value at all?

We certainly hope so, given how much effort has gone into its definition and various implementations from AMD, Apple, NVIDIA, and certainly others. Today, if you have the right kind of parallelism in your application, and you’re willing to expend the effort to recast your program in CUDA kernels and write the host program interface, you can see some dramatic performance improvements. Replacing CUDA with OpenCL may allow you to port your program from an NVIDIA device to an ATI GPU or Intel Larrabee with only an incremental effort. So, yes, there is definite value here. The question remaining to be answered is how much value, and how long will it continue to be valuable. I can’t answer that, and I don’t want to raise the FUD (fear, uncertainty, doubt) factor. If Intel’s Larrabee and other similar devices, which support a richer programming model, replace GPUs as the dominant compute accelerator, OpenCL may join the dead language heap, along with Thinking Machine’s C*, MasPar’s MPL, and ClearSpeed’s Cn. However, if GPUs and other accelerators can continue to use the OpenCL programming model efficiently, and deliver high performance at relatively low cost, then OpenCL can enjoy a long, useful life. My opinion: it’s likely to be more useful as a target language for higher level programming languages, tools, and environments, or as a language to implement optimized libraries, than as a language for a more general programming community.

So let’s accept and even celebrate OpenCL for what it is, and not try to make it what it can’t be. There’s danger is raising expectations too high, or claiming too much (a la Bernie Madoff); OpenCL can be influential and succeed without replacing other parallel languages. To correct Steve Job’s quote: “While OpenCL is very similar in many respects to NVIDIA’s CUDA, it adds features to take advantage of other targets; and though it’s quite complex, it has the potential to deliver very high performance, and is much easier than trying to map your computation into OpenGL or graphics primitives.” Hype I can agree with; but then, I’m not the Apple CEO.

—–

Michael Wolfe has developed compilers for over 30 years in both academia and industry, and is now a senior compiler engineer at The Portland Group, Inc. (www.pgroup.com), a wholly-owned subsidiary of STMicroelectronics, Inc. The opinions stated here are those of the author, and do not represent opinions of The Portland Group, Inc. or STMicroelectronics, Inc.

Subscribe to HPCwire's Weekly Update!

Be the most informed person in the room! Stay ahead of the tech trends with industy updates delivered to you every week!

AWS Embraces FPGAs, ‘Elastic’ GPUs

December 2, 2016

A new instance type rolled out this week by Amazon Web Services is based on customizable field programmable gate arrays that promise to strike a balance between performance and cost as emerging workloads create requirements often unmet by general-purpose processors. Read more…

By George Leopold

AWS Launches Massive 100 Petabyte ‘Sneakernet’

December 1, 2016

Amazon Web Services now offers a way to move data into its cloud by the truckload. Read more…

By Tiffany Trader

Weekly Twitter Roundup (Dec. 1, 2016)

December 1, 2016

Here at HPCwire, we aim to keep the HPC community apprised of the most relevant and interesting news items that get tweeted throughout the week. Read more…

By Thomas Ayres

HPC Career Notes (Dec. 2016)

December 1, 2016

In this monthly feature, we’ll keep you up-to-date on the latest career developments for individuals in the high performance computing community. Read more…

By Thomas Ayres

Lighting up Aurora: Behind the Scenes at the Creation of the DOE’s Upcoming 200 Petaflops Supercomputer

December 1, 2016

In April 2015, U.S. Department of Energy Undersecretary Franklin Orr announced that Intel would be the prime contractor for Aurora: Read more…

By Jan Rowell

IBM and NSF Computing Pioneer Erich Bloch Dies at 91

November 30, 2016

Erich Bloch, a computational pioneer whose competitive zeal and commercial bent helped transform the National Science Foundation while he was its director, died last Friday at age 91. Bloch was a productive force to be reckoned. During his long stint at IBM prior to joining NSF Bloch spearheaded development of the “Stretch” supercomputer and IBM’s phenomenally successful System/360. Read more…

By John Russell

Pioneering Programmers Awarded Presidential Medal of Freedom

November 30, 2016

In an awards ceremony on November 22, President Barack Obama recognized 21 recipients with the Presidential Medal of Freedom, the Nation’s highest civilian honor. Read more…

By Tiffany Trader

Seagate-led SAGE Project Delivers Update on Exascale Goals

November 29, 2016

Roughly a year and a half after its launch, the SAGE exascale storage project led by Seagate has delivered a substantive interim report – Data Storage for Extreme Scale. Read more…

By John Russell

AWS Launches Massive 100 Petabyte ‘Sneakernet’

December 1, 2016

Amazon Web Services now offers a way to move data into its cloud by the truckload. Read more…

By Tiffany Trader

Lighting up Aurora: Behind the Scenes at the Creation of the DOE’s Upcoming 200 Petaflops Supercomputer

December 1, 2016

In April 2015, U.S. Department of Energy Undersecretary Franklin Orr announced that Intel would be the prime contractor for Aurora: Read more…

By Jan Rowell

Seagate-led SAGE Project Delivers Update on Exascale Goals

November 29, 2016

Roughly a year and a half after its launch, the SAGE exascale storage project led by Seagate has delivered a substantive interim report – Data Storage for Extreme Scale. Read more…

By John Russell

Nvidia Sees Bright Future for AI Supercomputing

November 23, 2016

Graphics chipmaker Nvidia made a strong showing at SC16 in Salt Lake City last week. Read more…

By Tiffany Trader

HPE-SGI to Tackle Exascale and Enterprise Targets

November 22, 2016

At first blush, and maybe second blush too, Hewlett Packard Enterprise’s (HPE) purchase of SGI seems like an unambiguous win-win. SGI’s advanced shared memory technology, its popular UV product line (Hanna), deep vertical market expertise, and services-led go-to-market capability all give HPE a leg up in its drive to remake itself. Bear in mind HPE came into existence just a year ago with the split of Hewlett-Packard. The computer landscape, including HPC, is shifting with still unclear consequences. One wonders who’s next on the deal block following Dell’s recent merger with EMC. Read more…

By John Russell

Intel Details AI Hardware Strategy for Post-GPU Age

November 21, 2016

Last week at SC16, Intel revealed its product roadmap for embedding its processors with key capabilities and attributes needed to take artificial intelligence (AI) to the next level. Read more…

By Alex Woodie

SC Says Farewell to Salt Lake City, See You in Denver

November 18, 2016

After an intense four-day flurry of activity (and a cold snap that brought some actual snow flurries), the SC16 show floor closed yesterday (Thursday) and the always-extensive technical program wound down today. Read more…

By Tiffany Trader

D-Wave SC16 Update: What’s Bo Ewald Saying These Days

November 18, 2016

Tucked in a back section of the SC16 exhibit hall, quantum computing pioneer D-Wave has been talking up its new 2000-qubit processor announced in September. Forget for a moment the criticism sometimes aimed at D-Wave. This small Canadian company has sold several machines including, for example, ones to Lockheed and NASA, and has worked with Google on mapping machine learning problems to quantum computing. In July Los Alamos National Laboratory took possession of a 1000-quibit D-Wave 2X system that LANL ordered a year ago around the time of SC15. Read more…

By John Russell

Why 2016 Is the Most Important Year in HPC in Over Two Decades

August 23, 2016

In 1994, two NASA employees connected 16 commodity workstations together using a standard Ethernet LAN and installed open-source message passing software that allowed their number-crunching scientific application to run on the whole “cluster” of machines as if it were a single entity. Read more…

By Vincent Natoli, Stone Ridge Technology

IBM Advances Against x86 with Power9

August 30, 2016

After offering OpenPower Summit attendees a limited preview in April, IBM is unveiling further details of its next-gen CPU, Power9, which the tech mainstay is counting on to regain market share ceded to rival Intel. Read more…

By Tiffany Trader

AWS Beats Azure to K80 General Availability

September 30, 2016

Amazon Web Services has seeded its cloud with Nvidia Tesla K80 GPUs to meet the growing demand for accelerated computing across an increasingly-diverse range of workloads. The P2 instance family is a welcome addition for compute- and data-focused users who were growing frustrated with the performance limitations of Amazon's G2 instances, which are backed by three-year-old Nvidia GRID K520 graphics cards. Read more…

By Tiffany Trader

Think Fast – Is Neuromorphic Computing Set to Leap Forward?

August 15, 2016

Steadily advancing neuromorphic computing technology has created high expectations for this fundamentally different approach to computing. Read more…

By John Russell

The Exascale Computing Project Awards $39.8M to 22 Projects

September 7, 2016

The Department of Energy’s Exascale Computing Project (ECP) hit an important milestone today with the announcement of its first round of funding, moving the nation closer to its goal of reaching capable exascale computing by 2023. Read more…

By Tiffany Trader

HPE Gobbles SGI for Larger Slice of $11B HPC Pie

August 11, 2016

Hewlett Packard Enterprise (HPE) announced today that it will acquire rival HPC server maker SGI for $7.75 per share, or about $275 million, inclusive of cash and debt. The deal ends the seven-year reprieve that kept the SGI banner flying after Rackable Systems purchased the bankrupt Silicon Graphics Inc. for $25 million in 2009 and assumed the SGI brand. Bringing SGI into its fold bolsters HPE's high-performance computing and data analytics capabilities and expands its position... Read more…

By Tiffany Trader

ARM Unveils Scalable Vector Extension for HPC at Hot Chips

August 22, 2016

ARM and Fujitsu today announced a scalable vector extension (SVE) to the ARMv8-A architecture intended to enhance ARM capabilities in HPC workloads. Fujitsu is the lead silicon partner in the effort (so far) and will use ARM with SVE technology in its post K computer, Japan’s next flagship supercomputer planned for the 2020 timeframe. This is an important incremental step for ARM, which seeks to push more aggressively into mainstream and HPC server markets. Read more…

By John Russell

IBM Debuts Power8 Chip with NVLink and Three New Systems

September 8, 2016

Not long after revealing more details about its next-gen Power9 chip due in 2017, IBM today rolled out three new Power8-based Linux servers and a new version of its Power8 chip featuring Nvidia’s NVLink interconnect. Read more…

By John Russell

Leading Solution Providers

Vectors: How the Old Became New Again in Supercomputing

September 26, 2016

Vector instructions, once a powerful performance innovation of supercomputing in the 1970s and 1980s became an obsolete technology in the 1990s. But like the mythical phoenix bird, vector instructions have arisen from the ashes. Here is the history of a technology that went from new to old then back to new. Read more…

By Lynd Stringer

US, China Vie for Supercomputing Supremacy

November 14, 2016

The 48th edition of the TOP500 list is fresh off the presses and while there is no new number one system, as previously teased by China, there are a number of notable entrants from the US and around the world and significant trends to report on. Read more…

By Tiffany Trader

Intel Launches Silicon Photonics Chip, Previews Next-Gen Phi for AI

August 18, 2016

At the Intel Developer Forum, held in San Francisco this week, Intel Senior Vice President and General Manager Diane Bryant announced the launch of Intel's Silicon Photonics product line and teased a brand-new Phi product, codenamed "Knights Mill," aimed at machine learning workloads. Read more…

By Tiffany Trader

CPU Benchmarking: Haswell Versus POWER8

June 2, 2015

With OpenPOWER activity ramping up and IBM’s prominent role in the upcoming DOE machines Summit and Sierra, it’s a good time to look at how the IBM POWER CPU stacks up against the x86 Xeon Haswell CPU from Intel. Read more…

By Tiffany Trader

Beyond von Neumann, Neuromorphic Computing Steadily Advances

March 21, 2016

Neuromorphic computing – brain inspired computing – has long been a tantalizing goal. The human brain does with around 20 watts what supercomputers do with megawatts. And power consumption isn’t the only difference. Fundamentally, brains ‘think differently’ than the von Neumann architecture-based computers. While neuromorphic computing progress has been intriguing, it has still not proven very practical. Read more…

By John Russell

Dell EMC Engineers Strategy to Democratize HPC

September 29, 2016

The freshly minted Dell EMC division of Dell Technologies is on a mission to take HPC mainstream with a strategy that hinges on engineered solutions, beginning with a focus on three industry verticals: manufacturing, research and life sciences. "Unlike traditional HPC where everybody bought parts, assembled parts and ran the workloads and did iterative engineering, we want folks to focus on time to innovation and let us worry about the infrastructure," said Jim Ganthier, senior vice president, validated solutions organization at Dell EMC Converged Platforms Solution Division. Read more…

By Tiffany Trader

Container App ‘Singularity’ Eases Scientific Computing

October 20, 2016

HPC container platform Singularity is just six months out from its 1.0 release but already is making inroads across the HPC research landscape. It's in use at Lawrence Berkeley National Laboratory (LBNL), where Singularity founder Gregory Kurtzer has worked in the High Performance Computing Services (HPCS) group for 16 years. Read more…

By Tiffany Trader

Micron, Intel Prepare to Launch 3D XPoint Memory

August 16, 2016

Micron Technology used last week’s Flash Memory Summit to roll out its new line of 3D XPoint memory technology jointly developed with Intel while demonstrating the technology in solid-state drives. Micron claimed its Quantx line delivers PCI Express (PCIe) SSD performance with read latencies at less than 10 microseconds and writes at less than 20 microseconds. Read more…

By George Leopold

  • arrow
  • Click Here for More Headlines
  • arrow
Share This