Solace Systems Sets the Pace in the Race to Zero Latency

By Michael Feldman

September 14, 2009

In the algorithmic trading business, speed is literally money. An extra microsecond of latency between the market feed and the trading application could be worth a million dollars to a large investment bank or hedge fund. The annual take of algorithmic trading in the US is estimated in the billions of dollars per year — $8 billion according Tabb Group, a research and advisory firm for the financial industry.

That’s why companies that offer the fastest market messaging platforms are getting a lot of attention these days. In financial applications, messaging filters and massages the data, and as such, is the critical layer between the market data feed, or feed handler, and the trading application. For example, messaging middleware is the software that makes the decision to send MSFT messages to a subscriber that is looking to buy or sell Microsoft stock. But getting that information to the subscriber as quickly as possible is what determines how much of an advantage the customer has.

The lucrative messaging business has attracted a number of companies, including TIBCO Software, 29West, IBM, RTI, Tervela, NYSE Technologies, and Solace Systems. Of these, Solace has been one of the most aggressive in attacking the latency issue. The company’s big claim to fame is its hardware approach to message acceleration. Traditional messaging is accomplished via software running on servers, but Solace has developed what they call a message (or content) router. It’s implemented as an appliance that provides the message processing using FPGAs, network processors, and other off-the-shelf ASICs. The company’s Unified Messaging Platform API provides client applications access to the functionality.

According to Larry Neumann, Solace’s senior vice president of marketing and alliances, the hardware-based message router is analogous to what IP routers did for Internet, namely to commoditize software functionality into the network. The advantage, he says, is that the hardware approach gives a 10x performance boost — in some cases, 100x — compared to software-based messaging, mainly by eliminating all the context switching between the OS and the application. Also, FPGAs and ASICs just generally outperform CPUs for these kinds of high throughput workloads.

“Being a newer entrant into the market, if we were 20 percent faster, it would be very hard to displace the incumbent,” says Neumann. “But if you’re 10 times faster, they’ll take a good hard look at you; if you’re 100 times faster, it becomes pretty easy.”

The hardware is not identical for all use cases. Solace offers six different function-specific “blades” or cards that can be included in a configuration, and not all of them necessarily apply to financial market applications (Solace’s message platform offerings are applicable across a variety of application areas outside financial services, such as real-time billing systems, IPTV, mobile content distribution, and even geospatial applications like emergency alerts, proximity marketing, and social networking). For algorithmic trading, the minimum configuration is the network acceleration blade and the topic routing blade.

TIBCO Software and Tervela also offer hardware-based messaging appliances. In TIBCO’s case, the company is actually employing Solace blades, which are used to implement TIBCO’s Rendezvous messaging software in firmware. Tervela’s version is its own TMX Message Switch, which also uses a combination of ASICs and FPGAs to implement messaging middleware.

In all cases, the hardware-based appliances promise at least an order of magnitude boost in performance compared to software solutions. This allows the financial customers to replace many servers with a single appliance, reducing the datacenter footprint, along with the attendant power and cooling. Latency within the appliance is predictably low, but the end-to-end latency is still dependent upon the other pieces of the market trading system: the feed handler and the algorithmic engine on the server. Because of the separate devices and the network hops between them, the best-case latency is in the tens of microseconds.

The next logical step is to integrate the components into a single system in order to avoid all the network latency and intermediate memory copies. And that’s what Solace Systems has done. Announced on Monday at the High Performance Computing on Wall Street conference in New York, Solace has demonstrated sub-microsecond latencies by adding support for inter-process communications (IPC) via shared memory. Using Solace’s latest Unified Messaging Platform API, developers will be able to fold the ticker feed function, the messaging platform, and the algorithmic engine into the same application, and use shared memory IPC as the data transport.

Such applications do not rely on special hardware appliances. All you need is a standard multicore x86 server, preferably sitting in a colocation facility right next to the exchange. With quad-core chips now the norm, and eight-core chips (and greater) on the horizon, single servers are becoming powerful enough to handle these integrated trading applications. Solace ran tests with a million 100-byte messages per second, achieving an average latency of less than 700 nanoseconds using a single Intel Xeon “Harpertown” 5400 processor.

To put that in perspective, currently the largest market feed is delivered by the Options Price Reporting Authority (OPRA), which coincidentally tops out at about a million messages per second. However, those numbers are projected to rise, and as they do, latency tends to rise with it. Fortunately, core counts are increasing as well. Intel’s eight-core Nehalem EX processor is expected to be launched in early 2010, essentially doubling the processing power of the quad-core generation.

In fact, Solace CTO Shawn McAllister believes the Nehalem processors, in general, with their larger caches and better memory bandwidth, should deliver even lower latencies than they demonstrated with their Harpertown tests. He says for best results you want to keep each application on the same processor, and nail individual application components (like the feed handler and algo engine) to specific cores. That way, application data can be shared between the cores in the Level 2 cache, reducing latency even further.

Not all the applications that make up an automated trading suite can be run in a single server, however. There are risk management systems, order executions systems, and back-end settlement systems, among others, that can’t all be shoe-horned onto a single motherboard. The idea, of course, would be to put the most pathologically latency-sensitive trading applications in the server, and spread the rest out across the datacenter using the more traditional feed handlers, message platforms and servers. McAllister says one of the advantages of their model is that their common API allows developers to deploy the same code in a networked environment as in a shared memory one, since the middleware takes care of the data transport underneath the programmer interface.

Solace is not the only vendor to have thought to implement a messaging system using IPC on shared memory. In February, 29West introduced a similar IPC transport offering, claiming end-to-end latencies in the 3 to 5 microsecond range. But with Solace breaking the 1 microsecond barrier, McAllister thinks they’ve got a game changer — at least for the time being. Considering there is so much money at stake in algorithmic trading, the race toward zero latency is far from over.

Subscribe to HPCwire's Weekly Update!

Be the most informed person in the room! Stay ahead of the tech trends with industy updates delivered to you every week!

Hedge Funds (with Supercomputing help) Rank First Among Investors

May 22, 2017

In case you didn’t know, The Quants Run Wall Street Now, or so says a headline in today’s Wall Street Journal. Quant-run hedge funds now control the largest Read more…

By John Russell

IBM, D-Wave Report Quantum Computing Advances

May 18, 2017

IBM said this week it has built and tested a pair of quantum computing processors, including a prototype of a commercial version. That progress follows an an Read more…

By George Leopold

PRACEdays 2017 Wraps Up in Barcelona

May 18, 2017

Barcelona has been absolutely lovely; the weather, the food, the people. I am, sadly, finishing my last day at PRACEdays 2017 with two sessions: an in-depth loo Read more…

By Kim McMahon

US, Europe, Japan Deepen Research Computing Partnership

May 18, 2017

On May 17, 2017, a ceremony was held during the PRACEdays 2017 conference in Barcelona to announce the memorandum of understanding (MOU) between PRACE in Europe Read more…

By Tiffany Trader

HPE Extreme Performance Solutions

Exploring the Three Models of Remote Visualization

The explosion of data and advancement of digital technologies are dramatically changing the way many companies do business. With the help of high performance computing (HPC) solutions and data analytics platforms, manufacturers are developing products faster, healthcare providers are improving patient care, and energy companies are improving planning, exploration, and production. Read more…

NSF, IARPA, and SRC Push into “Semiconductor Synthetic Biology” Computing

May 18, 2017

Research into how biological systems might be fashioned into computational technology has a long history with various DNA-based computing approaches explored. N Read more…

By John Russell

DOE’s HPC4Mfg Leads to Paper Manufacturing Improvement

May 17, 2017

Papermaking ranks third behind only petroleum refining and chemical production in terms of energy consumption. Recently, simulations made possible by the U.S. D Read more…

By John Russell

PRACEdays 2017: The start of a beautiful week in Barcelona

May 17, 2017

Touching down in Barcelona on Saturday afternoon, it was warm, sunny, and oh so Spanish. I was greeted at my hotel with a glass of Cava to sip and treated to a Read more…

By Kim McMahon

NSF Issues $60M RFP for “Towards a Leadership-Class” System

May 16, 2017

In case you missed it, the National Science Foundation issued the request for proposals (RFP) for the next ‘Towards a Leadership-Class Computing Facility – Read more…

By John Russell

Cray Offers Supercomputing as a Service, Targets Biotechs First

May 16, 2017

Leading supercomputer vendor Cray and datacenter/cloud provider the Markley Group today announced plans to jointly deliver supercomputing as a service. The init Read more…

By John Russell

HPE’s Memory-centric The Machine Coming into View, Opens ARMs to 3rd-party Developers

May 16, 2017

Announced three years ago, HPE’s The Machine is said to be the largest R&D program in the venerable company’s history, one that could be progressing tow Read more…

By Doug Black

What’s Up with Hyperion as It Transitions From IDC?

May 15, 2017

If you’re wondering what’s happening with Hyperion Research – formerly the IDC HPC group – apparently you are not alone, says Steve Conway, now senior V Read more…

By John Russell

Nvidia’s Mammoth Volta GPU Aims High for AI, HPC

May 10, 2017

At Nvidia's GPU Technology Conference (GTC17) in San Jose, Calif., this morning, CEO Jensen Huang announced the company's much-anticipated Volta architecture a Read more…

By Tiffany Trader

HPE Launches Servers, Services, and Collaboration at GTC

May 10, 2017

Hewlett Packard Enterprise (HPE) today launched a new liquid cooled GPU-driven Apollo platform based on SGI ICE architecture, a new collaboration with NVIDIA, a Read more…

By John Russell

IBM PowerAI Tools Aim to Ease Deep Learning Data Prep, Shorten Training 

May 10, 2017

A new set of GPU-powered AI software announced by IBM today brings automation to many of the tedious, time consuming and complex aspects of AI project on-rampin Read more…

By Doug Black

Bright Computing 8.0 Adds Azure, Expands Machine Learning Support

May 9, 2017

Bright Computing, long a prominent provider of cluster management tools for HPC, today released version 8.0 of Bright Cluster Manager and Bright OpenStack. The Read more…

By John Russell

Microsoft Azure Will Debut Pascal GPU Instances This Year

May 8, 2017

As Nvidia's GPU Technology Conference gets underway in San Jose, Calif., Microsoft today revealed plans to add Pascal-generation GPU horsepower to its Azure clo Read more…

By Tiffany Trader

Quantum Bits: D-Wave and VW; Google Quantum Lab; IBM Expands Access

March 21, 2017

For a technology that’s usually characterized as far off and in a distant galaxy, quantum computing has been steadily picking up steam. Just how close real-wo Read more…

By John Russell

Google Pulls Back the Covers on Its First Machine Learning Chip

April 6, 2017

This week Google released a report detailing the design and performance characteristics of the Tensor Processing Unit (TPU), its custom ASIC for the inference Read more…

By Tiffany Trader

Trump Budget Targets NIH, DOE, and EPA; No Mention of NSF

March 16, 2017

President Trump’s proposed U.S. fiscal 2018 budget issued today sharply cuts science spending while bolstering military spending as he promised during the cam Read more…

By John Russell

HPC Compiler Company PathScale Seeks Life Raft

March 23, 2017

HPCwire has learned that HPC compiler company PathScale has fallen on difficult times and is asking the community for help or actively seeking a buyer for its a Read more…

By Tiffany Trader

Nvidia Responds to Google TPU Benchmarking

April 10, 2017

Last week, Google reported that its custom ASIC Tensor Processing Unit (TPU) was 15-30x faster for inferencing workloads than Nvidia's K80 GPU (see our coverage Read more…

By Tiffany Trader

CPU-based Visualization Positions for Exascale Supercomputing

March 16, 2017

Since our first formal product releases of OSPRay and OpenSWR libraries in 2016, CPU-based Software Defined Visualization (SDVis) has achieved wide-spread adopt Read more…

By Jim Jeffers, Principal Engineer and Engineering Leader, Intel

TSUBAME3.0 Points to Future HPE Pascal-NVLink-OPA Server

February 17, 2017

Since our initial coverage of the TSUBAME3.0 supercomputer yesterday, more details have come to light on this innovative project. Of particular interest is a ne Read more…

By Tiffany Trader

Facebook Open Sources Caffe2; Nvidia, Intel Rush to Optimize

April 18, 2017

From its F8 developer conference in San Jose, Calif., today, Facebook announced Caffe2, a new open-source, cross-platform framework for deep learning. Caffe2 is Read more…

By Tiffany Trader

Leading Solution Providers

Nvidia’s Mammoth Volta GPU Aims High for AI, HPC

May 10, 2017

At Nvidia's GPU Technology Conference (GTC17) in San Jose, Calif., this morning, CEO Jensen Huang announced the company's much-anticipated Volta architecture a Read more…

By Tiffany Trader

Tokyo Tech’s TSUBAME3.0 Will Be First HPE-SGI Super

February 16, 2017

In a press event Friday afternoon local time in Japan, Tokyo Institute of Technology (Tokyo Tech) announced its plans for the TSUBAME3.0 supercomputer, which w Read more…

By Tiffany Trader

Is Liquid Cooling Ready to Go Mainstream?

February 13, 2017

Lost in the frenzy of SC16 was a substantial rise in the number of vendors showing server oriented liquid cooling technologies. Three decades ago liquid cooling Read more…

By Steve Campbell

MIT Mathematician Spins Up 220,000-Core Google Compute Cluster

April 21, 2017

On Thursday, Google announced that MIT math professor and computational number theorist Andrew V. Sutherland had set a record for the largest Google Compute Eng Read more…

By Tiffany Trader

IBM Wants to be “Red Hat” of Deep Learning

January 26, 2017

IBM today announced the addition of TensorFlow and Chainer deep learning frameworks to its PowerAI suite of deep learning tools, which already includes popular Read more…

By John Russell

HPC Technique Propels Deep Learning at Scale

February 21, 2017

Researchers from Baidu's Silicon Valley AI Lab (SVAIL) have adapted a well-known HPC communication technique to boost the speed and scale of their neural networ Read more…

By Tiffany Trader

US Supercomputing Leaders Tackle the China Question

March 15, 2017

As China continues to prove its supercomputing mettle via the Top500 list and the forward march of its ambitious plans to stand up an exascale machine by 2020, Read more…

By Tiffany Trader

DOE Supercomputer Achieves Record 45-Qubit Quantum Simulation

April 13, 2017

In order to simulate larger and larger quantum systems and usher in an age of "quantum supremacy," researchers are stretching the limits of today's most advance Read more…

By Tiffany Trader

  • arrow
  • Click Here for More Headlines
  • arrow
Share This