Solace Systems Sets the Pace in the Race to Zero Latency

By Michael Feldman

September 14, 2009

In the algorithmic trading business, speed is literally money. An extra microsecond of latency between the market feed and the trading application could be worth a million dollars to a large investment bank or hedge fund. The annual take of algorithmic trading in the US is estimated in the billions of dollars per year — $8 billion according Tabb Group, a research and advisory firm for the financial industry.

That’s why companies that offer the fastest market messaging platforms are getting a lot of attention these days. In financial applications, messaging filters and massages the data, and as such, is the critical layer between the market data feed, or feed handler, and the trading application. For example, messaging middleware is the software that makes the decision to send MSFT messages to a subscriber that is looking to buy or sell Microsoft stock. But getting that information to the subscriber as quickly as possible is what determines how much of an advantage the customer has.

The lucrative messaging business has attracted a number of companies, including TIBCO Software, 29West, IBM, RTI, Tervela, NYSE Technologies, and Solace Systems. Of these, Solace has been one of the most aggressive in attacking the latency issue. The company’s big claim to fame is its hardware approach to message acceleration. Traditional messaging is accomplished via software running on servers, but Solace has developed what they call a message (or content) router. It’s implemented as an appliance that provides the message processing using FPGAs, network processors, and other off-the-shelf ASICs. The company’s Unified Messaging Platform API provides client applications access to the functionality.

According to Larry Neumann, Solace’s senior vice president of marketing and alliances, the hardware-based message router is analogous to what IP routers did for Internet, namely to commoditize software functionality into the network. The advantage, he says, is that the hardware approach gives a 10x performance boost — in some cases, 100x — compared to software-based messaging, mainly by eliminating all the context switching between the OS and the application. Also, FPGAs and ASICs just generally outperform CPUs for these kinds of high throughput workloads.

“Being a newer entrant into the market, if we were 20 percent faster, it would be very hard to displace the incumbent,” says Neumann. “But if you’re 10 times faster, they’ll take a good hard look at you; if you’re 100 times faster, it becomes pretty easy.”

The hardware is not identical for all use cases. Solace offers six different function-specific “blades” or cards that can be included in a configuration, and not all of them necessarily apply to financial market applications (Solace’s message platform offerings are applicable across a variety of application areas outside financial services, such as real-time billing systems, IPTV, mobile content distribution, and even geospatial applications like emergency alerts, proximity marketing, and social networking). For algorithmic trading, the minimum configuration is the network acceleration blade and the topic routing blade.

TIBCO Software and Tervela also offer hardware-based messaging appliances. In TIBCO’s case, the company is actually employing Solace blades, which are used to implement TIBCO’s Rendezvous messaging software in firmware. Tervela’s version is its own TMX Message Switch, which also uses a combination of ASICs and FPGAs to implement messaging middleware.

In all cases, the hardware-based appliances promise at least an order of magnitude boost in performance compared to software solutions. This allows the financial customers to replace many servers with a single appliance, reducing the datacenter footprint, along with the attendant power and cooling. Latency within the appliance is predictably low, but the end-to-end latency is still dependent upon the other pieces of the market trading system: the feed handler and the algorithmic engine on the server. Because of the separate devices and the network hops between them, the best-case latency is in the tens of microseconds.

The next logical step is to integrate the components into a single system in order to avoid all the network latency and intermediate memory copies. And that’s what Solace Systems has done. Announced on Monday at the High Performance Computing on Wall Street conference in New York, Solace has demonstrated sub-microsecond latencies by adding support for inter-process communications (IPC) via shared memory. Using Solace’s latest Unified Messaging Platform API, developers will be able to fold the ticker feed function, the messaging platform, and the algorithmic engine into the same application, and use shared memory IPC as the data transport.

Such applications do not rely on special hardware appliances. All you need is a standard multicore x86 server, preferably sitting in a colocation facility right next to the exchange. With quad-core chips now the norm, and eight-core chips (and greater) on the horizon, single servers are becoming powerful enough to handle these integrated trading applications. Solace ran tests with a million 100-byte messages per second, achieving an average latency of less than 700 nanoseconds using a single Intel Xeon “Harpertown” 5400 processor.

To put that in perspective, currently the largest market feed is delivered by the Options Price Reporting Authority (OPRA), which coincidentally tops out at about a million messages per second. However, those numbers are projected to rise, and as they do, latency tends to rise with it. Fortunately, core counts are increasing as well. Intel’s eight-core Nehalem EX processor is expected to be launched in early 2010, essentially doubling the processing power of the quad-core generation.

In fact, Solace CTO Shawn McAllister believes the Nehalem processors, in general, with their larger caches and better memory bandwidth, should deliver even lower latencies than they demonstrated with their Harpertown tests. He says for best results you want to keep each application on the same processor, and nail individual application components (like the feed handler and algo engine) to specific cores. That way, application data can be shared between the cores in the Level 2 cache, reducing latency even further.

Not all the applications that make up an automated trading suite can be run in a single server, however. There are risk management systems, order executions systems, and back-end settlement systems, among others, that can’t all be shoe-horned onto a single motherboard. The idea, of course, would be to put the most pathologically latency-sensitive trading applications in the server, and spread the rest out across the datacenter using the more traditional feed handlers, message platforms and servers. McAllister says one of the advantages of their model is that their common API allows developers to deploy the same code in a networked environment as in a shared memory one, since the middleware takes care of the data transport underneath the programmer interface.

Solace is not the only vendor to have thought to implement a messaging system using IPC on shared memory. In February, 29West introduced a similar IPC transport offering, claiming end-to-end latencies in the 3 to 5 microsecond range. But with Solace breaking the 1 microsecond barrier, McAllister thinks they’ve got a game changer — at least for the time being. Considering there is so much money at stake in algorithmic trading, the race toward zero latency is far from over.

Subscribe to HPCwire's Weekly Update!

Be the most informed person in the room! Stay ahead of the tech trends with industy updates delivered to you every week!

How ‘Knights Mill’ Gets Its Deep Learning Flops

June 22, 2017

Intel, the subject of much speculation regarding the delayed or potentially canceled “Aurora” contract (the Argonne Lab part of the CORAL “pre-exascale” award), parsed out additional information about the upc Read more…

By Tiffany Trader

Tsinghua Crowned Eight-Time Student Cluster Champions at ISC

June 22, 2017

Always a hard-fought competition, the Student Cluster Competition awards were announced Wednesday, June 21, at the ISC High Performance Conference 2017. Amid whoops and hollers from the crowd, Thomas Sterling presented t Read more…

By Kim McMahon

GPUs, Power9, Figure Prominently in IBM’s Bet on Weather Forecasting

June 22, 2017

IBM jumped into the weather forecasting business roughly a year and a half ago by purchasing The Weather Company. This week at ISC 2017, Big Blue rolled out plans to push deeper into climate science and develop more gran Read more…

By John Russell

Intersect 360 at ISC: HPC Industry at $44B by 2021

June 22, 2017

The care, feeding and sustained growth of the HPC industry increasingly is in the hands of the commercial market sector – in particular, it’s the hyperscale companies and their embrace of AI and deep learning – tha Read more…

By Doug Black

HPE Extreme Performance Solutions

Creating a Roadmap for HPC Innovation at ISC 2017

In an era where technological advancements are driving innovation to every sector, and powering major economic and scientific breakthroughs, high performance computing (HPC) is crucial to tackle the challenges of today and tomorrow. Read more…

At ISC – Goh on Go: Humans Can’t Scale, the Data-Centric Learning Machine Can

June 22, 2017

I've seen the future this week at ISC, it’s on display in prototype or Powerpoint form, and it’s going to dumbfound you. The future is an AI neural network designed to emulate and compete with the human brain. In thi Read more…

By Doug Black

AMD Charges Back into the Datacenter and HPC Workflows with EPYC Processor

June 20, 2017

AMD is charging back into the enterprise datacenter and select HPC workflows with its new EPYC 7000 processor line, code-named Naples, announced today at a “global” launch event in Austin TX. In many ways it was a fu Read more…

By John Russell

Hyperion: Deep Learning, AI Helping Drive Healthy HPC Industry Growth

June 20, 2017

To be at the ISC conference in Frankfurt this week is to experience deep immersion in deep learning. Users want to learn about it, vendors want to talk about it, analysts and journalists want to report on it. Deep learni Read more…

By Doug Black

OpenACC Shows Growing Strength at ISC

June 19, 2017

OpenACC is strutting its stuff at ISC this year touting expanding membership, a jump in downloads, favorable benchmarks across several architectures, new staff members, and new support by key HPC applications providers, Read more…

By John Russell

How ‘Knights Mill’ Gets Its Deep Learning Flops

June 22, 2017

Intel, the subject of much speculation regarding the delayed or potentially canceled “Aurora” contract (the Argonne Lab part of the CORAL “pre-exascal Read more…

By Tiffany Trader

Tsinghua Crowned Eight-Time Student Cluster Champions at ISC

June 22, 2017

Always a hard-fought competition, the Student Cluster Competition awards were announced Wednesday, June 21, at the ISC High Performance Conference 2017. Amid wh Read more…

By Kim McMahon

GPUs, Power9, Figure Prominently in IBM’s Bet on Weather Forecasting

June 22, 2017

IBM jumped into the weather forecasting business roughly a year and a half ago by purchasing The Weather Company. This week at ISC 2017, Big Blue rolled out pla Read more…

By John Russell

Intersect 360 at ISC: HPC Industry at $44B by 2021

June 22, 2017

The care, feeding and sustained growth of the HPC industry increasingly is in the hands of the commercial market sector – in particular, it’s the hyperscale Read more…

By Doug Black

At ISC – Goh on Go: Humans Can’t Scale, the Data-Centric Learning Machine Can

June 22, 2017

I've seen the future this week at ISC, it’s on display in prototype or Powerpoint form, and it’s going to dumbfound you. The future is an AI neural network Read more…

By Doug Black

AMD Charges Back into the Datacenter and HPC Workflows with EPYC Processor

June 20, 2017

AMD is charging back into the enterprise datacenter and select HPC workflows with its new EPYC 7000 processor line, code-named Naples, announced today at a “g Read more…

By John Russell

Hyperion: Deep Learning, AI Helping Drive Healthy HPC Industry Growth

June 20, 2017

To be at the ISC conference in Frankfurt this week is to experience deep immersion in deep learning. Users want to learn about it, vendors want to talk about it Read more…

By Doug Black

OpenACC Shows Growing Strength at ISC

June 19, 2017

OpenACC is strutting its stuff at ISC this year touting expanding membership, a jump in downloads, favorable benchmarks across several architectures, new staff Read more…

By John Russell

Quantum Bits: D-Wave and VW; Google Quantum Lab; IBM Expands Access

March 21, 2017

For a technology that’s usually characterized as far off and in a distant galaxy, quantum computing has been steadily picking up steam. Just how close real-wo Read more…

By John Russell

Trump Budget Targets NIH, DOE, and EPA; No Mention of NSF

March 16, 2017

President Trump’s proposed U.S. fiscal 2018 budget issued today sharply cuts science spending while bolstering military spending as he promised during the cam Read more…

By John Russell

HPC Compiler Company PathScale Seeks Life Raft

March 23, 2017

HPCwire has learned that HPC compiler company PathScale has fallen on difficult times and is asking the community for help or actively seeking a buyer for its a Read more…

By Tiffany Trader

Google Pulls Back the Covers on Its First Machine Learning Chip

April 6, 2017

This week Google released a report detailing the design and performance characteristics of the Tensor Processing Unit (TPU), its custom ASIC for the inference Read more…

By Tiffany Trader

CPU-based Visualization Positions for Exascale Supercomputing

March 16, 2017

In this contributed perspective piece, Intel’s Jim Jeffers makes the case that CPU-based visualization is now widely adopted and as such is no longer a contrarian view, but is rather an exascale requirement. Read more…

By Jim Jeffers, Principal Engineer and Engineering Leader, Intel

Nvidia Responds to Google TPU Benchmarking

April 10, 2017

Nvidia highlights strengths of its newest GPU silicon in response to Google's report on the performance and energy advantages of its custom tensor processor. Read more…

By Tiffany Trader

Nvidia’s Mammoth Volta GPU Aims High for AI, HPC

May 10, 2017

At Nvidia's GPU Technology Conference (GTC17) in San Jose, Calif., this morning, CEO Jensen Huang announced the company's much-anticipated Volta architecture a Read more…

By Tiffany Trader

Facebook Open Sources Caffe2; Nvidia, Intel Rush to Optimize

April 18, 2017

From its F8 developer conference in San Jose, Calif., today, Facebook announced Caffe2, a new open-source, cross-platform framework for deep learning. Caffe2 is the successor to Caffe, the deep learning framework developed by Berkeley AI Research and community contributors. Read more…

By Tiffany Trader

Leading Solution Providers

MIT Mathematician Spins Up 220,000-Core Google Compute Cluster

April 21, 2017

On Thursday, Google announced that MIT math professor and computational number theorist Andrew V. Sutherland had set a record for the largest Google Compute Engine (GCE) job. Sutherland ran the massive mathematics workload on 220,000 GCE cores using preemptible virtual machine instances. Read more…

By Tiffany Trader

Google Debuts TPU v2 and will Add to Google Cloud

May 25, 2017

Not long after stirring attention in the deep learning/AI community by revealing the details of its Tensor Processing Unit (TPU), Google last week announced the Read more…

By John Russell

US Supercomputing Leaders Tackle the China Question

March 15, 2017

Joint DOE-NSA report responds to the increased global pressures impacting the competitiveness of U.S. supercomputing. Read more…

By Tiffany Trader

Groq This: New AI Chips to Give GPUs a Run for Deep Learning Money

April 24, 2017

CPUs and GPUs, move over. Thanks to recent revelations surrounding Google’s new Tensor Processing Unit (TPU), the computing world appears to be on the cusp of Read more…

By Alex Woodie

Russian Researchers Claim First Quantum-Safe Blockchain

May 25, 2017

The Russian Quantum Center today announced it has overcome the threat of quantum cryptography by creating the first quantum-safe blockchain, securing cryptocurrencies like Bitcoin, along with classified government communications and other sensitive digital transfers. Read more…

By Doug Black

DOE Supercomputer Achieves Record 45-Qubit Quantum Simulation

April 13, 2017

In order to simulate larger and larger quantum systems and usher in an age of “quantum supremacy,” researchers are stretching the limits of today’s most advanced supercomputers. Read more…

By Tiffany Trader

Messina Update: The US Path to Exascale in 16 Slides

April 26, 2017

Paul Messina, director of the U.S. Exascale Computing Project, provided a wide-ranging review of ECP’s evolving plans last week at the HPC User Forum. Read more…

By John Russell

Knights Landing Processor with Omni-Path Makes Cloud Debut

April 18, 2017

HPC cloud specialist Rescale is partnering with Intel and HPC resource provider R Systems to offer first-ever cloud access to Xeon Phi "Knights Landing" processors. The infrastructure is based on the 68-core Intel Knights Landing processor with integrated Omni-Path fabric (the 7250F Xeon Phi). Read more…

By Tiffany Trader

  • arrow
  • Click Here for More Headlines
  • arrow
Share This