Bill Dally Sees Central Role for the GPU in Supercomputing

By Michael Feldman

October 5, 2009

Before Bill Dally joined NVIDIA as its chief scientist earlier this year, he had already enjoyed a long and accomplished career in academia, first at Caltech, then MIT, and finally at Stanford University. Along the way, he published over 200 research papers, and authored two textbooks, and collected IEEE’s Seymour Cray and ACM’s Maurice Wilkes awards.

But it wasn’t just about teaching and research. At heart, Dally is an architect and developer of parallel computing technology and holds over 50 patents in the field. While at Caltech, he designed the MOSSIM Simulation Engine and the Torus Routing chip. Later at MIT he developed two experimental parallel computer systems, the J-Machine and the M-Machine. His last 12 years have been spent at Stanford, where he helped develop the system architecture and networking technology found in most large parallel computers today. He also cofounded two commercial ventures: Velio Communications Inc., a company that built high performance communications chips (and which was later acquired by LSI); and Stream Processors Inc., a fabless semiconductor firm that offers parallel processors for embedded markets.

Over the past three years, NVIDIA’s move into the GPU computing space found resonance with Dally’s lifelong interest in parallel computing. In January of this year, NVIDIA CEO Jen-Hsun Huang enticed him to come work for the company as its new chief scientist. By then, NVIDIA’s future GPU architecture, Fermi, was already well into its development, giving Dally a clear indication of where the company was investing its future.

I got a chance to speak with Dally last week at the GPU Technology Conference in San Jose, California, and asked him why he chose to move from academia to NVIDIA, the significance of the Fermi architecture, and the future of GPU computing.

HPCwire: Bill, what drew you to come work for NVIDIA?

Bill Dally: That’s a good question. In many ways, I sort of had the dream job: a professor at Stanford, with brilliant colleagues and students around, and interesting problems to work on. But over a series of conversations with Jen-Hsun, he convinced me that it was a compelling opportunity to come here and define, not just the future of GPUs, but the future of computing as a whole. That just seemed like too exciting a thing to pass up.

HPCwire: Let’s jump into some of the news announced at the conference. The big announcement, of course, is Fermi, the new GPU architecture NVIDIA unveiled here. You’ve been talking quite a bit about it this week. How much were you involved in Fermi work?

Dally: Very little. I was actually involved in the architecture of the G80, as a consultant back in 2003. But by the time I joined the company in January, the architecture was largely done, and it was in the implementation phases. I did get involved in some implementation and circuit issues with Fermi. In particular, there were synchronizers that I helped to further improve the performance of, in collaboration with some of the circuit designers at NVIDIA.

HPCwire: There has already been a lot of talk about Fermi’s impact on high performance computing. What do think will be Fermi’s effect on supercomputing, from the low end to the high end, over the next couple of years?

Dally: I think it’s going to be huge. We’re in a situation — I talked about in my session yesterday — where GPU computing is at the tipping point. We already have the work of the pioneers, who have already gone to tremendous effort getting numerous applications — fluid dynamics applications, solid mechanics applications, analysis of genomic sequences, analysis of neural models — running on GPUs with tremendous speedups. We’ve seen 40x to 200x speedups over CPU performance and tremendous power savings. But it really hasn’t been the mainstream solution for high performance computing. It’s been in the niche.

I think there are really two main reasons for that: double precision performance and ECC. When we would go and talk with customers who wanted to build really large clusters, the ECC issue would always come up. They said if you want to build mission-critical applications, if you want to build a large cluster, it has to have ECC, or you can’t play with the big boys. Obviously we listened to that, and Fermi has ECC.

If you look at the one area where GPU computing has really taken off so far, it’s oil and gas exploration — for both seismic analysis and reservoir simulation. I think a big reason why that is one of the first areas to take off is because it can make very good use of single precision.

We heard how Bloomberg used GPUs for their bond pricing. Even though that’s a double precision application, they were able to get enough gains from the GT200, which has just one-eighth the double precision performance of Fermi. Now we’ve basically taken care of the two big obstacles for everybody.

When we start talking to people who want to build a huge cluster for the top one or top 10 of the TOP500 list, and they say, “We need to make it fit in this power envelope. We can’t do that with CPUs.” And they say, “What are the other alternatives?” Even with something like a Cell [processor], they can’t do it. The only way they can really do this is with GPU computing. I think we’re really poised for GPU computing to become the standard way of doing high performance computing.

The real rate limiter here is going to be porting of codes. It’s going to be limited by how people can take important codes and move them over to run on the GPU.

HPCwire: At one of the sessions here at the conference, there was talk about exaflop computing, a milestone which we’re supposed to hit in about nine years. Do you think GPU computing is going to be an integral part of that?

Dally: I think GPU computing is going to be the central part of any serious exascale effort. I was actually an author of that exascale report that [Cray CTO] Steve Scott had in his presentation. The reason is that — and Jen-Hsun made this point really well in his keynote presentation — GPUs are throughput computers. They’re optimized to deliver performance per dollar, per unit power, and per unit area for [applications] with plenty of parallelism.

In contrast, CPUs optimize for latency. They spend a lot of die area and a lot of power optimizing single thread performance and doing speculative computation: predicting branches and so on. All of that costs area and power, and doesn’t give you more FLOPS.

To get to exascale, it’s all about FLOPS per watt. It’s all about how efficiently you can perform computations, and GPUs are optimized for FLOPS per watt. They are the ideal throughput computer. Over time, they are going to evolve from their current position of being graphics devices that people are using to do computing to being really awesome throughput computing devices that can do both computing and graphics very well.

HPCwire: Is NVIDIA committed to the GPU-as-coprocessor model for the foreseeable future, or are you guys starting to think about integrating a sequential processor in the GPU at some point?

Dally: At some point that may make sense. If you look at today though, nobody’s asking us to make slower GPUs. Integration is an economic decision. The question is if it’s cheaper to put two functions on one chip or is it cheaper and more flexible to have two separate chips. And the answer today is that it’s more flexible to have two separate chips. With the ability to have a single address space that we provide, it doesn’t really matter which chip the CPU or the GPU are on. You want to have the bulk of the memory on the GPU side, so that you can be doing your calculations there. The time to launch threads is not limited by the PCIe connection. It may be limited a little by the driver software on the CPU, but integrating that on-board wouldn’t reduce that overhead in any substantial way.

So the only argument would be: “At what point in time would you be willing to carve out some die area, and make your GPU slower, and limit the flexibility of what GPUs you could match with CPUs to get the economic benefits of integration?” We don’t see that happening yet — at least at the high end.

At the low end, we do in fact do exactly that. Our Tegra product incorporates a GPU, a number of fixed function accelerators, and two ARM cores to make a really compelling system on a chip for mobile applications. At that low end of the spectrum, people don’t need the fastest possible GPU. But they do need an integrated solution that reduces the cost, the power, and the form factor. For mobile applications, all three of those features are critical, but for the high end parts, that’s not in the cards for the near future.
 

Subscribe to HPCwire's Weekly Update!

Be the most informed person in the room! Stay ahead of the tech trends with industy updates delivered to you every week!

2022 Road Trip: NASA Ames Takes Off

November 25, 2022

I left Dallas very early Friday morning after the conclusion of SC22. I had a race with the devil to get from Dallas to Mountain View, Calif., by Sunday. According to Google Maps, this 1,957 mile jaunt would be the longe Read more…

2022 Road Trip: Sandia Brain Trust Sounds Off

November 24, 2022

As the 2022 Great American Supercomputing Road Trip carries on, it’s Sandia’s turn. It was a bright sunny day when I rolled into Albuquerque after a high-speed run from Los Alamos National Laboratory. My interview su Read more…

2022 HPC Road Trip: Los Alamos

November 23, 2022

With SC22 in the rearview mirror, it’s time to get back to the 2022 Great American Supercomputing Road Trip. To refresh everyone’s memory, I jumped in the car on November 3rd and headed towards SC22 in Dallas, stoppi Read more…

Chipmakers Looking at New Architecture to Drive Computing Ahead

November 23, 2022

The ability to scale current computing designs is reaching a breaking point, and chipmakers such as Intel, Qualcomm and AMD are putting their brains together on an alternate architecture to push computing forward. The chipmakers are coalescing around the new concept of sparse computing, which involves bringing computing to data... Read more…

QuEra’s Quest: Build a Flexible Neutral Atom-based Quantum Computer

November 23, 2022

Last month, QuEra Computing began providing access to its 256-qubit, neutral atom-based quantum system, Aquila, from Amazon Braket. Founded in 2018, and built on technology developed at Harvard and MIT, QuEra, is one of Read more…

AWS Solution Channel

Shutterstock 1648511269

Avoid overspending with AWS Batch using a serverless cost guardian monitoring architecture

Pay-as-you-go resources are a compelling but daunting concept for budget conscious research customers. Uncertainty of cloud costs is a barrier-to-entry for most, and having near real-time cost visibility is critical. Read more…

 

shutterstock_1431394361

AI and the need for purpose-built cloud infrastructure

Modern AI solutions augment human understanding, preferences, intent, and even spoken language. AI improves our knowledge and understanding by delivering faster, more informed insights that fuel transformation beyond anything previously imagined. Read more…

SC22’s ‘HPC Accelerates’ Plenary Stresses Need for Collaboration

November 21, 2022

Every year, SC has a theme. For SC22 – held last week in Dallas – it was “HPC Accelerates”: a theme that conference chair Candace Culhane said reflected “how supercomputing is continuously changing the world by Read more…

Chipmakers Looking at New Architecture to Drive Computing Ahead

November 23, 2022

The ability to scale current computing designs is reaching a breaking point, and chipmakers such as Intel, Qualcomm and AMD are putting their brains together on an alternate architecture to push computing forward. The chipmakers are coalescing around the new concept of sparse computing, which involves bringing computing to data... Read more…

QuEra’s Quest: Build a Flexible Neutral Atom-based Quantum Computer

November 23, 2022

Last month, QuEra Computing began providing access to its 256-qubit, neutral atom-based quantum system, Aquila, from Amazon Braket. Founded in 2018, and built o Read more…

SC22’s ‘HPC Accelerates’ Plenary Stresses Need for Collaboration

November 21, 2022

Every year, SC has a theme. For SC22 – held last week in Dallas – it was “HPC Accelerates”: a theme that conference chair Candace Culhane said reflected Read more…

Quantum – Are We There (or Close) Yet? No, Says the Panel

November 19, 2022

For all of its politeness, a fascinating panel on the last day of SC22 – Quantum Computing: A Future for HPC Acceleration? – mostly served to illustrate the Read more…

RISC-V Is Far from Being an Alternative to x86 and Arm in HPC

November 18, 2022

One of the original RISC-V designers this week boldly predicted that the open architecture will surpass rival chip architectures in performance. "The prediction is two or three years we'll be surpassing your architectures and available performance with... Read more…

Gordon Bell Special Prize Goes to LLM-Based Covid Variant Prediction

November 17, 2022

For three years running, ACM has awarded not only its long-standing Gordon Bell Prize (read more about this year’s winner here!) but also its Gordon Bell Spec Read more…

2022 Gordon Bell Prize Goes to Plasma Accelerator Research

November 17, 2022

At the awards ceremony at SC22 in Dallas today, ACM awarded the 2022 ACM Gordon Bell Prize to a team of researchers who used four major supercomputers – inclu Read more…

Gordon Bell Nominee Used LLMs, HPC, Cerebras CS-2 to Predict Covid Variants

November 17, 2022

Large language models (LLMs) have taken the tech world by storm over the past couple of years, dominating headlines with their ability to generate convincing hu Read more…

Nvidia Shuts Out RISC-V Software Support for GPUs 

September 23, 2022

Nvidia is not interested in bringing software support to its GPUs for the RISC-V architecture despite being an early adopter of the open-source technology in its GPU controllers. Nvidia has no plans to add RISC-V support for CUDA, which is the proprietary GPU software platform, a company representative... Read more…

RISC-V Is Far from Being an Alternative to x86 and Arm in HPC

November 18, 2022

One of the original RISC-V designers this week boldly predicted that the open architecture will surpass rival chip architectures in performance. "The prediction is two or three years we'll be surpassing your architectures and available performance with... Read more…

AWS Takes the Short and Long View of Quantum Computing

August 30, 2022

It is perhaps not surprising that the big cloud providers – a poor term really – have jumped into quantum computing. Amazon, Microsoft Azure, Google, and th Read more…

Chinese Startup Biren Details BR100 GPU

August 22, 2022

Amid the high-performance GPU turf tussle between AMD and Nvidia (and soon, Intel), a new, China-based player is emerging: Biren Technology, founded in 2019 and headquartered in Shanghai. At Hot Chips 34, Biren co-founder and president Lingjie Xu and Biren CTO Mike Hong took the (virtual) stage to detail the company’s inaugural product: the Biren BR100 general-purpose GPU (GPGPU). “It is my honor to present... Read more…

Tesla Bulks Up Its GPU-Powered AI Super – Is Dojo Next?

August 16, 2022

Tesla has revealed that its biggest in-house AI supercomputer – which we wrote about last year – now has a total of 7,360 A100 GPUs, a nearly 28 percent uplift from its previous total of 5,760 GPUs. That’s enough GPU oomph for a top seven spot on the Top500, although the tech company best known for its electric vehicles has not publicly benchmarked the system. If it had, it would... Read more…

AMD Thrives in Servers amid Intel Restructuring, Layoffs

November 12, 2022

Chipmakers regularly indulge in a game of brinkmanship, with an example being Intel and AMD trying to upstage one another with server chip launches this week. But each of those companies are in different positions, with AMD playing its traditional role of a scrappy underdog trying to unseat the behemoth Intel... Read more…

JPMorgan Chase Bets Big on Quantum Computing

October 12, 2022

Most talk about quantum computing today, at least in HPC circles, focuses on advancing technology and the hurdles that remain. There are plenty of the latter. F Read more…

UCIe Consortium Incorporates, Nvidia and Alibaba Round Out Board

August 2, 2022

The Universal Chiplet Interconnect Express (UCIe) consortium is moving ahead with its effort to standardize a universal interconnect at the package level. The c Read more…

Leading Solution Providers

Contributors

Using Exascale Supercomputers to Make Clean Fusion Energy Possible

September 2, 2022

Fusion, the nuclear reaction that powers the Sun and the stars, has incredible potential as a source of safe, carbon-free and essentially limitless energy. But Read more…

Nvidia, Qualcomm Shine in MLPerf Inference; Intel’s Sapphire Rapids Makes an Appearance.

September 8, 2022

The steady maturation of MLCommons/MLPerf as an AI benchmarking tool was apparent in today’s release of MLPerf v2.1 Inference results. Twenty-one organization Read more…

Not Just Cash for Chips – The New Chips and Science Act Boosts NSF, DOE, NIST

August 3, 2022

After two-plus years of contentious debate, several different names, and final passage by the House (243-187) and Senate (64-33) last week, the Chips and Science Act will soon become law. Besides the $54.2 billion provided to boost US-based chip manufacturing, the act reshapes US science policy in meaningful ways. NSF’s proposed budget... Read more…

SC22 Unveils ACM Gordon Bell Prize Finalists

August 12, 2022

Courtesy of the schedule for the SC22 conference, we now have our first glimpse at the finalists for this year’s coveted Gordon Bell Prize. The Gordon Bell Pr Read more…

Intel Is Opening up Its Chip Factories to Academia

October 6, 2022

Intel is opening up its fabs for academic institutions so researchers can get their hands on physical versions of its chips, with the end goal of boosting semic Read more…

AMD Previews 400 Gig Adaptive SmartNIC SOC at Hot Chips

August 24, 2022

Fresh from finalizing its acquisitions of FPGA provider Xilinx (Feb. 2022) and DPU provider Pensando (May 2022) ), AMD previewed what it calls a 400 Gig Adaptive smartNIC SOC yesterday at Hot Chips. It is another contender in the increasingly crowded and blurry smartNIC/DPU space where distinguishing between the two isn’t always easy. The motivation for these device types... Read more…

Google Program to Free Chips Boosts University Semiconductor Design

August 11, 2022

A Google-led program to design and manufacture chips for free is becoming popular among researchers and computer enthusiasts. The search giant's open silicon program is providing the tools for anyone to design chips, which then get manufactured. Google foots the entire bill, from a chip's conception to delivery of the final product in a user's hand. Google's... Read more…

AMD’s Genoa CPUs Offer Up to 96 5nm Cores Across 12 Chiplets

November 10, 2022

AMD’s fourth-generation Epyc processor line has arrived, starting with the “general-purpose” architecture, called “Genoa,” the successor to third-gen Eypc Milan, which debuted in March of last year. At a launch event held today in San Francisco, AMD announced the general availability of the latest Epyc CPUs with up to 96 TSMC 5nm Zen 4 cores... Read more…

  • arrow
  • Click Here for More Headlines
  • arrow
HPCwire