The Week in Review

By HPCwire Staff

October 15, 2009

Here is a collection of highlights from this week’s news stream as reported by HPCwire.

Platform Computing Launches Symphony 5

Accelrys Releases Materials Studio 5.0

DOE to Explore Scientific Cloud Computing

Penguin Deploys HPC Solution at the U of Pittsburgh

Clustercorp Creates Rocks+Hybrid

Colfax Unveils First Eight Tesla GPU Server

Intel Reports Sucessful Third Quarter

GENI Project Receives $11.5M in NSF Funding

Sun Unveils High Performance Flash Storage Arrays

Nitrogen Cycle Rounds Out Climate Model

New PNNL Facilities Enable Biology, Computing Advancements

MSC.Software Leverages NVIDIA’s CUDA Architecture

Moore’s Law to Hold for 75 Years, If We’re Lucky

Inside Science reports on two physicists’ predictions for the eventual limit on processor speeds. The researchers have determined that computers have a speed limit that is as certain as the speed of light. They say that if processor speed continues to increase at the same rate, which, according to Moore’s law is a doubling every two years, they will hit a wall in 75 years.

If components are to continue shrinking, physicists must eventually code bits of information onto ever smaller particles. Smaller means faster in the microelectronic world, but physicists Lev Levitin and Tommaso Toffoli at Boston University in Massachusetts, have slapped a speed limit on computing, no matter how small the components get.

“If we believe in Moore’s law … then it would take about 75 to 80 years to achieve this quantum limit,” Levitin said.

“No system can overcome that limit. It doesn’t depend on the physical nature of the system or how it’s implemented, what algorithm you use for computation…any choice of hardware and software,” Levitin said. “This bound poses an absolute law of nature, just like the speed of light.”

Another researcher mentioned in the story holds that 75 years is far too optimistic, claiming the limit will be acheived much sooner, in roughly 20 years.

If such a limit exists, then future advancements will have to rely on more cores, faster interconnects, and parallel programming.

Carnegie Mellon’s Fast Array of Wimpy Nodes

Carnegie Mellon researchers together with Intel Labs Pittsburg have combined their talents to create an experimental, low-power computing cluster based on a Fast Array of Wimpy Nodes — or FAWN. Great name aside, the architecture gets its energy-efficiency by combining low-power embedded processors, like those typically used in netbooks, and flash memory, which is faster and consumes a lot less power than hard disks.

The work is being led by David Andersen, Carnegie Mellon assistant professor of computer science, and Michael Kaminsky, senior research scientist at ILP. The duo just received a best paper award for their report on FAWN at the Association for Computing Machinery’s annual Symposium on Operating Systems Principles. From the press release:

“FAWN systems can’t replace all of the servers in a datacenter, but they work really well for key-value storage systems, which need to access relatively small bits of information quickly,” Andersen said. Key-value storage systems are growing in both size and importance, he added, as ever larger social networks and shopping Web sites keep track of customers’ shopping carts, thumbnail photos of friends and a slew of message postings.

Even though the low-energy processors are not as fast as their top-speed cousins, they create a better balance between processor speed, I/O, and memory bandwidth. This is not the case anymore in conventional systems where the processors are too quick for their own good. For example, most CPUs end up wasting power just waiting for memory bottlenecks to clear.

A next-generation FAWN architecture will use Intel Atom processors, which are currently found in netbooks, mobile devices and other low-power applications.

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