The Week in Review
Here is a collection of highlights from this week’s news stream as reported by HPCwire.
A Cluster of Their Own
What happens to all the fancy supercomputers that universities get? Namely, who gets to use them? One imagines they are used mostly by researchers in pursuit of lofty science goals, but how much time is left over for student learners? Well someone at the LSU Center for Computation & Technology must have been asking similar questions, which led to this week’s announcement of a supercomputing cluster dedicated exclusively to student use. The cluster was named “Arete,” which comes from the Greek quality of excellence in fulfilling one’s full potential and purpose. Indeed.
From the announcement:
“Faculty and research staff are the primary users for LSU’s existing supercomputing systems, and we realized it is important, as part of our academic mission, to also provide students with opportunities to use these machines,” said CCT Interim Director Stephen David Beck. “With Arete, we are happy to provide a resource for the whole campus so students can take the skills they learn in the classroom and put them into practice, giving them a much deeper appreciation of how this technology is advancing research in many disciplines.”
A 72-node cluster with a peak performance of 5.3 teraflops, Arete is comparable to other high-end resources on campus. It is already installed and operational and will go live at the start of the Spring 2010 semester. The first student group to be assigned time on Arete will come from a CSC 7600 class, called ”High Performance Computing: Models, Methods and Means,” which Department of Computer Science Professor Thomas Sterling will teach this spring.
Tilera First with 100-Core Processor
Tilera Corp., which is known for its 36 and 64 core-count chips, announced this week four new processors, including the world’s first 100-core processor, the TILE-Gx100. Tilera says its Multicore Development Environment (MDE) will offer simplified many-core programming, and it has expanded its relationships with operating system and software vendors to enable rapid product deployment. From the release:
The TILE-Gx family — available with 16, 36, 64 and 100 cores — employs Tilera’s unique architecture that scales well beyond the core count of traditional microprocessors. Tilera’s two-dimensional iMesh interconnect eliminates the need for an on-chip bus and its Dynamic Distributed Cache (DDC) system allows each cores’ local cache to be shared coherently across the entire chip. These two key technologies enable the TILE Architecture performance to scale linearly with the number of cores on the chip — a feat that is currently unmatched.
For some additional info on the release, take a look at coverage from TG Daily, which includes this insight from Tilera spokesperson Bob Doud:
“Tilera is four years ahead of everyone else in the chip world. Unlike Intel, we were able to begin our chip design with a clean slate. Intel is weighed down by a certain amount of baggage, for example, an immense investment in X86 architecture. They have to ensure backwards compatibility for a number of server and consumer products.”
“But our view is that increasing performance is not just about driving up clock frequency. Although higher clock frequency does lead to higher speeds, the power draw goes up exponentially as a result. Our belief is that the performance should be raised via parallelism - or many cores running at modest clock speeds.”
The TILE-Gx processor family is available for a wide range of applications, among them enterprise networking, cloud computing, multimedia and wireless infrastructure.