Reconfigurable Computing Research Pushes Forward

By Nicole Hemsoth

November 20, 2009

Despite all the all the recent hoopla about GPGPUs and eight-core CPUs, proponents of reconfigurable computing continue to sing the praises of FPGA-based HPC. The main advantage of reconfigurable computing, or RC for short, is that programmers are able to change the circuitry of the chip on the fly. Thus, in theory, the hardware can be matched to the software, rather than the other way around. While there are a handful of commercial offerings from companies such as Convey Computer, XtremeData, GiDel, Mitrionics, and Impulse Accelerated Technologies, RC is still an area of active research.

In the U.S., the NSF Center for High-Performance Reconfigurable Computing (CHREC, pronounced “shreck”), acts as the research hub for RC, bringing together more than 30 organizations in this field. CHREC is run by Dr. Alan George, who gave an address at the SC09 Workshop on High-Performance Reconfigurable Computing Technology and Applications (HPRCTA’09) on November 15. We got the opportunity to ask Dr. George about the work going on at the Center and what he thinks RC technology can offer to high performance computing users.

HPCwire: FPGA-based reconfigurable computing has captured some loyal followers in the HPC community. What are the advantages of FPGAs for high-performance computing compared to fixed-logic architectures such as CPUs, GPUs, the Cell processor?

Alan George: HPC is approaching a crossroads in terms of enabling technologies and their inherent strengths and weaknesses. Goals and challenges in three principal areas are vitally important yet increasingly in conflict: performance, productivity, and sustainability. For example, HPC machines lauded in the upper tier of the TOP500 list as most powerful in the world are remarkably high in performance yet also remarkably massive in size, energy, heat, and cost, all featuring programmable, fixed-logic devices, for example, CPU, GPU, Cell. Meanwhile, throughout society, energy cost, source, and availability are a growing concern. As life-cycle costs of energy and cooling rise to approach and exceed that of software and hardware in total cost of ownership, these technologies may become unsustainable.

By contrast, numerous research studies show that computing with reconfigurable-logic devices — FPGAs, et al. — is fundamentally superior in terms of speed and energy, due to the many advantages of adaptive, customizable hardware parallelism. Common sense confirms this comparison. Programmable fixed-logic devices no matter their form feature a “one size fits all” or “Jack of all trades” philosophy, with a predefined structure of parallelism, yet attempting to support all applications or some major subset. In contrast, the structure of parallelism in reconfigurable-logic devices can be customized, that is, reconfigured, for each application or task on the fly, being versatile yet optimized specifically for each problem at hand. With this perspective, fixed-logic computing and accelerators are following a more evolutionary path, whereas RC is relatively new and revolutionary.

It should be noted that RC, as a new paradigm of computing, is broader than FPGA acceleration for HPC. FPGA devices are the leading commercial technology available today that is capable of RC, albeit not originally designed for RC, and thus FPGAs are the focal point for virtually all experimental research and commercial deployments, with a growing list of success stories. However, looking ahead more broadly, reconfigurable logic may be featured in future devices with a variety of structures, granularities, functionalities, etc., perhaps very similar to today’s FPGAs or perhaps quite different.

HPCwire: What role, or roles, do you see for RC technology in high performance computing and high performance embedded computing? Will RC be a niche solution in specific application areas or do you see this technology being used in general-purpose platforms that will be widely deployed?

George: Naturally, as a relatively new paradigm of computing, RC has started with emphasis in a few targeted areas, for example, aerospace and bioinformatics, where missions and users require dramatic improvement only possible by a revolutionary approach. As principal challenges — performance, productivity, and sustainability — become more pronounced, and as R&D in RC progresses, we believe that the RC paradigm will mature and expand in its role and influence to eventually become dominant in a broad range of applications, from satellites to servers to supercomputers. We are already witnessing this trend in several sectors of high-performance embedded computing. For example, in advanced computing on space missions, high performance and versatility are critical with limited energy, size, and weight. NASA, DOD, and other space-related agencies worldwide are increasingly featuring RC technologies in their platforms, as is the aerospace community in general. The driving issues in this community — again performance, productivity, and especially sustainability — are becoming increasingly important in HPC.

HPCwire: In the past couple of years, non-RC accelerators like the Cell processor and now, especially, general-purpose GPUs have been making big news in the HPC world, with major deployments planned. What has held back reconfigurable computing technology in this application space?

George: There are several reasons why Cell and GPU accelerators are more popular in HPC at present. Perhaps most obviously, they are viewed as inexpensive, due to leveraging of the gaming market. Vendors have invested heavily, both marketing and R&D, to broaden the appeal of these devices for the HPC community. Moreover, in terms of fundamental computing principles, they are an evolutionary development in device architecture, and as such represent less risk. However, we believe that inherent weaknesses of any fixed-logic device technology … in terms of broad applicability at speed and energy efficiency, will eventually become limiting factors.

By contrast, reconfigurable computing is a relatively new and immature paradigm of computing. Like any new paradigm, there are R&D challenges that must be solved before it can become more broadly applicable and eventually ubiquitous. With fixed-logic computing, the user and application have no control over underlying hardware parallelism; they simply attempt to exploit as much as the manufacturer has deemed to provide. With reconfigurable-logic computing, the user and application define the hardware parallelism, featuring wide and deep parallelism as appropriate, with selectable precision, optimized data paths, etc., up to the limits of total device capacity. This tremendous advantage in parallel computing potency comes with the challenge of complexity. Thus, as is natural for any new paradigm and set of technologies, design productivity is an important challenge at present for RC in general and FPGA devices in particular, so that HPC users, and others, can take full advantage without having to be trained as electrical engineers.

It should be noted that this life-cycle is commonplace in the history of technology. An established technology is dominant for many years; it experiences growth over a long period of time from evolutionary advances, and one day it is partially or wholly supplanted by a new, revolutionary technology, but only after that new technology has navigated a long and winding road of research and development. Productivity is often a key challenge for a new IT technology, learning how to effectively harness and exploit the inherent advantages of the new approach.

HPCwire: What do you see on the horizon that could propel reconfigurable computing into a more mainstream role?

George: There are two major factors on the horizon that we believe will dramatically change the landscape. One factor is the trend for performance, productivity, and sustainability borne by growing concerns with conventional technologies about speed versus energy consumption, which increasingly favors RC. The conventional model of computing with fixed-logic multicore devices is limiting in terms of performance per unit of energy as compared to reconfigurable-logic devices. However, RC is viewed by many as lagging in effective concepts and tools for application development by domain scientists and other users to harness this potency without special skills. Thus, the second factor is taming this new paradigm of computing and innovations in its technologies, so that it is amenable to a broader range of users. In this regard, many vendors and research groups are conducting R&D and developing new concepts, tools, and products to address this challenge. In the future, RC will become more important for a growing set of missions, applications, and users and, concomitantly, it will become more amenable to them, so that productivity is maximized alongside performance and sustainability.

HPCwire: The new Novo-G reconfigurable computing system at the NSF Center for High-Performance Reconfigurable Computing (CHREC) has been up and running for just a few months. Can you tell us about the machine and what you hope to accomplish with it?

George: Novo-G became operational in July of this year and is believed to be the most powerful RC machine ever fielded for research. Its size, cooling and power consumption are modest by HPC standards, but they hide its computational superiority. For example, in our first application experiment working with domain scientists in computational biology, performance was sustained with 96 FPGAs that matched that of the largest machines on the NSF TeraGrid, yet provided by a machine that is hundreds of times lower in cost, power, cooling, size, etc.

Housed in three racks, Novo-G consists of 24 standard Linux servers, plus a head node, connected by DDR InfiniBand and GigE. Each server features a tightly-coupled set of four FPGA accelerators on a ProcStar-III PCIe board from GiDEL supported by a conventional multicore CPU, motherboard, disk, etc. Each FPGA is a Stratix-III E260 device from Altera with 254K logic elements, 768 18×18 multipliers, and more than 4GB of DDR2 memory directly attached via three banks. Altogether, Novo-G features 96 of these FPGAs, with an upgrade underway that by January will double its RC capacity to 192 FPGAs via two coupled RC boards per server.

The purpose of Novo-G is to support a variety of research projects in CHREC related to RC performance, productivity and sustainability. Founded in 2007, CHREC is a national research center under the auspices of the I/UCRC program of the National Science Foundation and consists of more than 30 academic, industry and government partners working collaboratively on research in this field. In addition, several new collaborations have been inspired by Novo-G, with other research groups, for example, Boston University and the Air Force Research Laboratory, as well as tools vendors such as Impulse Accelerated Technologies and Mitrionics.

HPCwire: Can you talk about a few of the projects at CHREC that look especially promising?

George: On-going research projects at the four university sites of CHREC — the University of Florida, Brigham Young University led by Dr. Brent Nelson, George Washington University led by Dr. Tarek El-Ghazawi, and Virginia Tech led by Dr. Peter Athanas — fall into four categories: productivity, architecture, partial reconfiguration, and fault tolerance. In the area of productivity, several projects are underway, crafting novel concepts for design of RC applications and systems, including new methods and tools for design formulation and prediction, hardware virtualization, module and core reuse, design verification and optimization, and programming with high-level languages. With respect to architecture, researchers are working to characterize and optimize new and emerging devices — both fixed and reconfigurable logic — and systems, as well as methods to promote autonomous hardware reconfiguration. Both of these project areas of productivity and architecture relate well to HPC.

Meanwhile, one of the unique features of some RC devices is their ability to reconfigure portions of the hardware of the chip while other portions remain unchanged and thus operational, and this powerful feature involves many research and design challenges being studied and addressed by several teams. Last but not least, as process densities increase and become more susceptible to faults, environments become harsher, and resources become more prone to soft or hard errors, research challenges arise in fault tolerance. In this area, CHREC researchers are developing device- and system-level RC concepts and architectures to support scenarios that require high performance, versatility, and reliability with low power, cooling, and size, be it for outer space or the HPC computer room.

Subscribe to HPCwire's Weekly Update!

Be the most informed person in the room! Stay ahead of the tech trends with industry updates delivered to you every week!

Quantum Watchers – Terrific Interview with Caltech’s John Preskill by CERN

July 17, 2024

In case you missed it, there's a fascinating interview with John Preskill, the prominent Caltech physicist and pioneering quantum computing researcher that was recently posted by CERN’s department of experimental physi Read more…

Aurora AI-Driven Atmosphere Model is 5,000x Faster Than Traditional Systems

July 16, 2024

While the onset of human-driven climate change brings with it many horrors, the increase in the frequency and strength of storms poses an enormous threat to communities across the globe. As climate change is warming ocea Read more…

Researchers Say Memory Bandwidth and NVLink Speeds in Hopper Not So Simple

July 15, 2024

Researchers measured the real-world bandwidth of Nvidia's Grace Hopper superchip, with the chip-to-chip interconnect results falling well short of theoretical claims. A paper published on July 10 by researchers in the U. Read more…

Belt-Tightening in Store for Most Federal FY25 Science Budets

July 15, 2024

If it’s summer, it’s federal budgeting time, not to mention an election year as well. There’s an excellent summary of the curent state of FY25 efforts reported in AIP’s policy FYI: Science Policy News. Belt-tight Read more…

Peter Shor Wins IEEE 2025 Shannon Award

July 15, 2024

Peter Shor, the MIT mathematician whose ‘Shor’s algorithm’ sent shivers of fear through the encryption community and helped galvanize ongoing efforts to build quantum computers, has been named the 2025 winner of th Read more…

Weekly Wire Roundup: July 8-July 12, 2024

July 12, 2024

HPC news can get pretty sleepy in June and July, but this week saw a bump in activity midweek as Americans realized they still had work to do after the previous holiday weekend. The world outside the United States also s Read more…

Aurora AI-Driven Atmosphere Model is 5,000x Faster Than Traditional Systems

July 16, 2024

While the onset of human-driven climate change brings with it many horrors, the increase in the frequency and strength of storms poses an enormous threat to com Read more…

Shutterstock 1886124835

Researchers Say Memory Bandwidth and NVLink Speeds in Hopper Not So Simple

July 15, 2024

Researchers measured the real-world bandwidth of Nvidia's Grace Hopper superchip, with the chip-to-chip interconnect results falling well short of theoretical c Read more…

Shutterstock 2203611339

NSF Issues Next Solicitation and More Detail on National Quantum Virtual Laboratory

July 10, 2024

After percolating for roughly a year, NSF has issued the next solicitation for the National Quantum Virtual Lab program — this one focused on design and imple Read more…

NCSA’s SEAS Team Keeps APACE of AlphaFold2

July 9, 2024

High-performance computing (HPC) can often be challenging for researchers to use because it requires expertise in working with large datasets, scaling the softw Read more…

Anders Jensen on Europe’s Plan for AI-optimized Supercomputers, Welcoming the UK, and More

July 8, 2024

The recent ISC24 conference in Hamburg showcased LUMI and other leadership-class supercomputers co-funded by the EuroHPC Joint Undertaking (JU), including three Read more…

Generative AI to Account for 1.5% of World’s Power Consumption by 2029

July 8, 2024

Generative AI will take on a larger chunk of the world's power consumption to keep up with the hefty hardware requirements to run applications. "AI chips repres Read more…

US Senators Propose $32 Billion in Annual AI Spending, but Critics Remain Unconvinced

July 5, 2024

Senate leader, Chuck Schumer, and three colleagues want the US government to spend at least $32 billion annually by 2026 for non-defense related AI systems.  T Read more…

Point and Click HPC: High-Performance Desktops

July 3, 2024

Recently, an interesting paper appeared on Arvix called Use Cases for High-Performance Research Desktops. To be clear, the term desktop in this context does not Read more…

Atos Outlines Plans to Get Acquired, and a Path Forward

May 21, 2024

Atos – via its subsidiary Eviden – is the second major supercomputer maker outside of HPE, while others have largely dropped out. The lack of integrators and Atos' financial turmoil have the HPC market worried. If Atos goes under, HPE will be the only major option for building large-scale systems. Read more…

Everyone Except Nvidia Forms Ultra Accelerator Link (UALink) Consortium

May 30, 2024

Consider the GPU. An island of SIMD greatness that makes light work of matrix math. Originally designed to rapidly paint dots on a computer monitor, it was then Read more…

Comparing NVIDIA A100 and NVIDIA L40S: Which GPU is Ideal for AI and Graphics-Intensive Workloads?

October 30, 2023

With long lead times for the NVIDIA H100 and A100 GPUs, many organizations are looking at the new NVIDIA L40S GPU, which it’s a new GPU optimized for AI and g Read more…

Shutterstock_1687123447

Nvidia Economics: Make $5-$7 for Every $1 Spent on GPUs

June 30, 2024

Nvidia is saying that companies could make $5 to $7 for every $1 invested in GPUs over a four-year period. Customers are investing billions in new Nvidia hardwa Read more…

Nvidia Shipped 3.76 Million Data-center GPUs in 2023, According to Study

June 10, 2024

Nvidia had an explosive 2023 in data-center GPU shipments, which totaled roughly 3.76 million units, according to a study conducted by semiconductor analyst fir Read more…

AMD Clears Up Messy GPU Roadmap, Upgrades Chips Annually

June 3, 2024

In the world of AI, there's a desperate search for an alternative to Nvidia's GPUs, and AMD is stepping up to the plate. AMD detailed its updated GPU roadmap, w Read more…

Some Reasons Why Aurora Didn’t Take First Place in the Top500 List

May 15, 2024

The makers of the Aurora supercomputer, which is housed at the Argonne National Laboratory, gave some reasons why the system didn't make the top spot on the Top Read more…

Intel’s Next-gen Falcon Shores Coming Out in Late 2025 

April 30, 2024

It's a long wait for customers hanging on for Intel's next-generation GPU, Falcon Shores, which will be released in late 2025.  "Then we have a rich, a very Read more…

Leading Solution Providers

Contributors

Google Announces Sixth-generation AI Chip, a TPU Called Trillium

May 17, 2024

On Tuesday May 14th, Google announced its sixth-generation TPU (tensor processing unit) called Trillium.  The chip, essentially a TPU v6, is the company's l Read more…

Nvidia H100: Are 550,000 GPUs Enough for This Year?

August 17, 2023

The GPU Squeeze continues to place a premium on Nvidia H100 GPUs. In a recent Financial Times article, Nvidia reports that it expects to ship 550,000 of its lat Read more…

IonQ Plots Path to Commercial (Quantum) Advantage

July 2, 2024

IonQ, the trapped ion quantum computing specialist, delivered a progress report last week firming up 2024/25 product goals and reviewing its technology roadmap. Read more…

Choosing the Right GPU for LLM Inference and Training

December 11, 2023

Accelerating the training and inference processes of deep learning models is crucial for unleashing their true potential and NVIDIA GPUs have emerged as a game- Read more…

Nvidia’s New Blackwell GPU Can Train AI Models with Trillions of Parameters

March 18, 2024

Nvidia's latest and fastest GPU, codenamed Blackwell, is here and will underpin the company's AI plans this year. The chip offers performance improvements from Read more…

The NASA Black Hole Plunge

May 7, 2024

We have all thought about it. No one has done it, but now, thanks to HPC, we see what it looks like. Hold on to your feet because NASA has released videos of wh Read more…

Q&A with Nvidia’s Chief of DGX Systems on the DGX-GB200 Rack-scale System

March 27, 2024

Pictures of Nvidia's new flagship mega-server, the DGX GB200, on the GTC show floor got favorable reactions on social media for the sheer amount of computing po Read more…

MLPerf Inference 4.0 Results Showcase GenAI; Nvidia Still Dominates

March 28, 2024

There were no startling surprises in the latest MLPerf Inference benchmark (4.0) results released yesterday. Two new workloads — Llama 2 and Stable Diffusion Read more…

  • arrow
  • Click Here for More Headlines
  • arrow
HPCwire