Ubiquitous Parallelism and the Classroom

By Tom Murphy of Contra Costa College, Paul Gray of the University of Northern Iowa, Charlie Peck of Earlham College, and Dave Joiner of Kean University

November 20, 2009

The oft-contended best simple statement is that we need ubiquitous parallelism in the classroom. Once upon a time, it was solely the lunatic fringe, programming esoteric architectures squirreled away in very special corners of the globe that cared about parallelism. In the near future, most electronic devices will have multiple cores which would benefit greatly from parallel programming. The low hanging fruit is, of course, the student’s laptop, and aiding the student to make full use of that laptop.

So how do we get there?

Our perception of next steps comes from close to a decade of collaboration pushing parallel and distributed computing education. This doesn’t mean we are right, just that we have been walking the walk. Three of the four of us are computer scientists and Dave, our physicist, is essentially also one (of course he claims that we’re all physicists). The bulk of our time together, outside of our respective day jobs teaching, is spent leading week-long workshops for faculty – largely focused on the teaching of parallel and distributed programming and computational thinking. Our assertion is this: As computer architectures evolve from single core to multicore to manycore, the computer science curriculum must experience a commensurate single-course to multi-course to many-course evolution in terms of where parallelism is studied.

Thus, you’re probably not surprised we’re saying faculty education is the key way to get from here to there, using as many modes of conveyance as possible. For teaching parallelism in our courses, few of us CS educators have learned what we have needed from our own formal education. We possess a self-taught science/art crafted via the hands-on hard-knock cycles of design, debugging, and despair which provided us with rich learning opportunities. This highlights the goals we have for our students: theory tightly coupled with the pragmatic skills of the practiced practitioner, learned via the cycles of design, debugging, and despair. Note that performance programming is wonderfully resurfacing in importance, for if you don’t need performance, why bother with the complexity of a parallel solution? Just run on your friendly neighborhood SMP or NUMA architecture, which will suffice as a first order solution for many problems. It was performance parallel programming that put the ‘L’ in lunatic fringe, and to raise ‘L’, we will ultimately need to examine the isolated graduate and undergraduate courses and weave the key components of parallelism into the fabric of all computer science courses beginning at the earliest level.

So let’s get specific on possibilities for the first courses at the undergraduate level. The core of CS1 typically starts with the nomenclature, theory, and components of a simple algorithm and a basic block of execution. Flow of control is our next extension: branches, loops, and functions. Parallelism is easily a natural next layer. When we invoke parallelism, we might demonstrate by conjuring with threads and shared memory, since the use of shared memory will not perturb the student’s simple notion of array-like memory. Additionally, the most frequently used shared memory mechanism, OpenMP, allows a gradual move from pure von-Neumann towards “pure” shared memory parallelism. This will cover fine-grain parallelism. A hunger for a different course of studies leads to the course-grained approach of distributed memory parallelism with MPI. Larger scale parallelism is naturally necessarily discovered by students as the problems of interest continue to grow.

The legal battlefield of Amdahl and Gustafson is a good next stop, guiding us into the study of data structures and algorithms via a perilous path littered with algorithms which scale poorly. Unchecked and unplanned parallelism will lead us to throttled resources whether Von Neumann’s bottleneck or the more insidious communication costs incurred when trying to tame a parallel algorithm. Students can learn of dwarvish parallel patterns and associated phenomena such as a sequentially elegant quicksort quickly foundering in the presence of unamortized distributed memory costs.

This is a good time to consider how to squeeze weeks and weeks of new material on parallelism into a semester. Something has to give and something will give, but this is not a new dilemma. It is something we each faced when first crafting what we will cover in a course. It is something we face to a greater or lesser extent every time we re-teach a course given the pace of change in our discipline.

Now it is time for an anecdote. Tom interviewed Dave Paterson as part of the “Teach Parallel” series of interviews. The interview ranged over many topics, one of which was Dave’s fourth edition of “Computer Organization and Design”, which gloriously has parallel topics woven into each chapter. This led to talking with Dave’s publisher about targeting an adaptation of the book towards community colleges, such as Contra Costa College where Tom teaches. The publisher was surprised to learn no dilution of the 703 pages was desired. Tom plans to cherry pick the material to use in his Computer Architecture course, which is a continuation of an experiment he’s been running in all his courses, which allows the entire book is covered, just at varying depths. It is important for Tom to convey how to be a good student, part of which is being able to self-learn from practitioners’ resources. This raises a good point: more textbook support for parallelism is going to make this whole process a heck of a lot easier. Unfortunately, it takes awhile to prime the curricular pump.

Computer architecture has traditionally incorporated elements of parallelism and concurrency; via semaphores and atomic operations, pipelines and multiple functional units, SMP architectures, and instruction and data paths. It has always been the place where the key hardware issues of the current architectures inform the software designed to run on it.

There are no easy answers, but there really are clear steps. We need to help students get to a place where they think of a single processing unit as just a special case of multiple processing units, much like they now learn to view a single variable as a special case of an array.

About the Authors

Thomas Murphy is a professor of Computer Science at Contra Costa College (CCC). He is chair of the CCC Computer Science program and is director of the CCC High Performance Computing Center, which has supported both the Linux cluster administration program and the computational science education program. Thomas has worked with the National Computational Science Institute (NCSI) since 2002. He is one of four members of the NCSI Parallel and Distributed Working group, which presents several three to seven day workshops each year, and helps develop the Bootable Cluster CD software platform, the LittleFe hardware platform, and the CSERD (Computational Science Education Reference Desk) curricular platform.

Paul Gray is an Associate Professor of Computer Science at the University of Northern Iowa. He created the Bootable Cluster CD project (http://bccd.net/) and provides instructional support for the National Computational Sciences Institute summer workshops on Cluster and Parallel Computing. He was SC08 Education Program Chair and serves on the executive committee for the SC07-11 Education Program.

Charlie Peck is the leader of the The Cluster Computing Group (CCG) at Earlham College, a student/faculty research group in the Computer Science department. The CCG is the primary design and engineering team for LittleFe, developers of computational science software, e.g., Folding@Clusters, and technical contributors to Paul Gray’s Bootable Cluster CD project. Additionally, Charlie is the primary developer on the LittleFe project.

Dave Joiner is an assistant professor of Computational Mathematics in the New Jersey Center for Science, Technology, and Mathematics Education. The NJCSTME focuses on the training of science and math teachers with an integrated view of modern math, science, and computing. Additionally, Dave has collaborated since 1999 with the efforts of the Shodor Education Foundation, Inc., and the National Computational Science Institute.  He currently serves as a Co-PI on the Computational Science Education Reference Desk, the Pathway of the National Science Digital Library devoted to computational science education.

Subscribe to HPCwire's Weekly Update!

Be the most informed person in the room! Stay ahead of the tech trends with industy updates delivered to you every week!

TACC Helps ROSIE Bioscience Gateway Expand its Impact

April 26, 2017

Biomolecule structure prediction has long been challenging not least because the relevant software and workflows often require high end HPC systems that many bioscience researchers lack easy access to. Read more…

By John Russell

Messina Update: The U.S. Path to Exascale in 16 Slides

April 26, 2017

Paul Messina, director of the U.S. Exascale Computing Project, provided a wide-ranging review of ECP’s evolving plans last week at the HPC User Forum. Read more…

By John Russell

IBM, Nvidia, Stone Ridge Claim Gas & Oil Simulation Record

April 25, 2017

IBM, Nvidia, and Stone Ridge Technology today reported setting the performance record for a “billion cell” oil and gas reservoir simulation. Read more…

By John Russell

ASC17 Makes Splash at Wuxi Supercomputing Center

April 24, 2017

A record-breaking twenty student teams plus scores of company representatives, media professionals, staff and student volunteers transformed a formerly empty hall inside the Wuxi Supercomputing Center into a bustling hub of HPC activity, kicking off day one of 2017 Asia Student Supercomputer Challenge (ASC17). Read more…

By Tiffany Trader

HPE Extreme Performance Solutions

Remote Visualization Optimizing Life Sciences Operations and Care Delivery

As patients continually demand a better quality of care and increasingly complex workloads challenge healthcare organizations to innovate, investing in the right technologies is key to ensuring growth and success. Read more…

Groq This: New AI Chips to Give GPUs a Run for Deep Learning Money

April 24, 2017

CPUs and GPUs, move over. Thanks to recent revelations surrounding Google’s new Tensor Processing Unit (TPU), the computing world appears to be on the cusp of a new generation of chips designed specifically for deep learning workloads. Read more…

By Alex Woodie

Musk’s Latest Startup Eyes Brain-Computer Links

April 21, 2017

Elon Musk, the auto and space entrepreneur and severe critic of artificial intelligence, is forming a new venture that reportedly will seek to develop an interface between the human brain and computers. Read more…

By George Leopold

MIT Mathematician Spins Up 220,000-Core Google Compute Cluster

April 21, 2017

On Thursday, Google announced that MIT math professor and computational number theorist Andrew V. Sutherland had set a record for the largest Google Compute Engine (GCE) job. Sutherland ran the massive mathematics workload on 220,000 GCE cores using preemptible virtual machine instances. Read more…

By Tiffany Trader

NERSC Cori Shows the World How Many-Cores for the Masses Works

April 21, 2017

As its mission, the high performance computing center for the U.S. Department of Energy Office of Science, NERSC (the National Energy Research Supercomputer Center), supports a broad spectrum of forefront scientific research across diverse areas that includes climate, material science, chemistry, fusion energy, high-energy physics and many others. Read more…

By Rob Farber

Messina Update: The U.S. Path to Exascale in 16 Slides

April 26, 2017

Paul Messina, director of the U.S. Exascale Computing Project, provided a wide-ranging review of ECP’s evolving plans last week at the HPC User Forum. Read more…

By John Russell

ASC17 Makes Splash at Wuxi Supercomputing Center

April 24, 2017

A record-breaking twenty student teams plus scores of company representatives, media professionals, staff and student volunteers transformed a formerly empty hall inside the Wuxi Supercomputing Center into a bustling hub of HPC activity, kicking off day one of 2017 Asia Student Supercomputer Challenge (ASC17). Read more…

By Tiffany Trader

Groq This: New AI Chips to Give GPUs a Run for Deep Learning Money

April 24, 2017

CPUs and GPUs, move over. Thanks to recent revelations surrounding Google’s new Tensor Processing Unit (TPU), the computing world appears to be on the cusp of a new generation of chips designed specifically for deep learning workloads. Read more…

By Alex Woodie

NERSC Cori Shows the World How Many-Cores for the Masses Works

April 21, 2017

As its mission, the high performance computing center for the U.S. Department of Energy Office of Science, NERSC (the National Energy Research Supercomputer Center), supports a broad spectrum of forefront scientific research across diverse areas that includes climate, material science, chemistry, fusion energy, high-energy physics and many others. Read more…

By Rob Farber

Hyperion (IDC) Paints a Bullish Picture of HPC Future

April 20, 2017

Hyperion Research – formerly IDC’s HPC group – yesterday painted a fascinating and complicated portrait of the HPC community’s health and prospects at the HPC User Forum held in Albuquerque, NM. HPC sales are up and growing ($22 billion, all HPC segments, 2016). Read more…

By John Russell

Knights Landing Processor with Omni-Path Makes Cloud Debut

April 18, 2017

HPC cloud specialist Rescale is partnering with Intel and HPC resource provider R Systems to offer first-ever cloud access to Xeon Phi "Knights Landing" processors. The infrastructure is based on the 68-core Intel Knights Landing processor with integrated Omni-Path fabric (the 7250F Xeon Phi). Read more…

By Tiffany Trader

CERN openlab Explores New CPU/FPGA Processing Solutions

April 14, 2017

Through a CERN openlab project known as the ‘High-Throughput Computing Collaboration,’ researchers are investigating the use of various Intel technologies in data filtering and data acquisition systems. Read more…

By Linda Barney

DOE Supercomputer Achieves Record 45-Qubit Quantum Simulation

April 13, 2017

In order to simulate larger and larger quantum systems and usher in an age of “quantum supremacy,” researchers are stretching the limits of today’s most advanced supercomputers. Read more…

By Tiffany Trader

Google Pulls Back the Covers on Its First Machine Learning Chip

April 6, 2017

This week Google released a report detailing the design and performance characteristics of the Tensor Processing Unit (TPU), its custom ASIC for the inference phase of neural networks (NN). Read more…

By Tiffany Trader

Quantum Bits: D-Wave and VW; Google Quantum Lab; IBM Expands Access

March 21, 2017

For a technology that’s usually characterized as far off and in a distant galaxy, quantum computing has been steadily picking up steam. Read more…

By John Russell

Trump Budget Targets NIH, DOE, and EPA; No Mention of NSF

March 16, 2017

President Trump’s proposed U.S. fiscal 2018 budget issued today sharply cuts science spending while bolstering military spending as he promised during the campaign. Read more…

By John Russell

HPC Compiler Company PathScale Seeks Life Raft

March 23, 2017

HPCwire has learned that HPC compiler company PathScale has fallen on difficult times and is asking the community for help or actively seeking a buyer for its assets. Read more…

By Tiffany Trader

Nvidia Responds to Google TPU Benchmarking

April 10, 2017

Nvidia highlights strengths of its newest GPU silicon in response to Google's report on the performance and energy advantages of its custom tensor processor. Read more…

By Tiffany Trader

CPU-based Visualization Positions for Exascale Supercomputing

March 16, 2017

In this contributed perspective piece, Intel’s Jim Jeffers makes the case that CPU-based visualization is now widely adopted and as such is no longer a contrarian view, but is rather an exascale requirement. Read more…

By Jim Jeffers, Principal Engineer and Engineering Leader, Intel

For IBM/OpenPOWER: Success in 2017 = (Volume) Sales

January 11, 2017

To a large degree IBM and the OpenPOWER Foundation have done what they said they would – assembling a substantial and growing ecosystem and bringing Power-based products to market, all in about three years. Read more…

By John Russell

TSUBAME3.0 Points to Future HPE Pascal-NVLink-OPA Server

February 17, 2017

Since our initial coverage of the TSUBAME3.0 supercomputer yesterday, more details have come to light on this innovative project. Of particular interest is a new board design for NVLink-equipped Pascal P100 GPUs that will create another entrant to the space currently occupied by Nvidia's DGX-1 system, IBM's "Minsky" platform and the Supermicro SuperServer (1028GQ-TXR). Read more…

By Tiffany Trader

Leading Solution Providers

Tokyo Tech’s TSUBAME3.0 Will Be First HPE-SGI Super

February 16, 2017

In a press event Friday afternoon local time in Japan, Tokyo Institute of Technology (Tokyo Tech) announced its plans for the TSUBAME3.0 supercomputer, which will be Japan’s “fastest AI supercomputer,” Read more…

By Tiffany Trader

Is Liquid Cooling Ready to Go Mainstream?

February 13, 2017

Lost in the frenzy of SC16 was a substantial rise in the number of vendors showing server oriented liquid cooling technologies. Three decades ago liquid cooling was pretty much the exclusive realm of the Cray-2 and IBM mainframe class products. That’s changing. We are now seeing an emergence of x86 class server products with exotic plumbing technology ranging from Direct-to-Chip to servers and storage completely immersed in a dielectric fluid. Read more…

By Steve Campbell

IBM Wants to be “Red Hat” of Deep Learning

January 26, 2017

IBM today announced the addition of TensorFlow and Chainer deep learning frameworks to its PowerAI suite of deep learning tools, which already includes popular offerings such as Caffe, Theano, and Torch. Read more…

By John Russell

BioTeam’s Berman Charts 2017 HPC Trends in Life Sciences

January 4, 2017

Twenty years ago high performance computing was nearly absent from life sciences. Today it’s used throughout life sciences and biomedical research. Genomics and the data deluge from modern lab instruments are the main drivers, but so is the longer-term desire to perform predictive simulation in support of Precision Medicine (PM). There’s even a specialized life sciences supercomputer, ‘Anton’ from D.E. Shaw Research, and the Pittsburgh Supercomputing Center is standing up its second Anton 2 and actively soliciting project proposals. There’s a lot going on. Read more…

By John Russell

Facebook Open Sources Caffe2; Nvidia, Intel Rush to Optimize

April 18, 2017

From its F8 developer conference in San Jose, Calif., today, Facebook announced Caffe2, a new open-source, cross-platform framework for deep learning. Caffe2 is the successor to Caffe, the deep learning framework developed by Berkeley AI Research and community contributors. Read more…

By Tiffany Trader

HPC Startup Advances Auto-Parallelization’s Promise

January 23, 2017

The shift from single core to multicore hardware has made finding parallelism in codes more important than ever, but that hasn’t made the task of parallel programming any easier. Read more…

By Tiffany Trader

HPC Technique Propels Deep Learning at Scale

February 21, 2017

Researchers from Baidu’s Silicon Valley AI Lab (SVAIL) have adapted a well-known HPC communication technique to boost the speed and scale of their neural network training and now they are sharing their implementation with the larger deep learning community. Read more…

By Tiffany Trader

IDG to Be Bought by Chinese Investors; IDC to Spin Out HPC Group

January 19, 2017

US-based publishing and investment firm International Data Group, Inc. (IDG) will be acquired by a pair of Chinese investors, China Oceanwide Holdings Group Co., Ltd. Read more…

By Tiffany Trader

  • arrow
  • Click Here for More Headlines
  • arrow
Share This