AMD Server Roadmap: Cores, Lots of Them

By Michael Feldman

December 1, 2009

Even though SC09 was something of a coming out party for GPU computing, CPUs are the foundation of high performance computing. The x86 architecture, in particular, continues to dominate the space, with Intel clearly owning the majority of the HPC server market. That dominance will probably remain for the foreseeable future. AMD’s server roadmap over the next couple of years may be able to blunt some of its rival’s momentum, but there are no magic bullets in the company’s arsenal.

At AMD’s Financial Analyst Day on November 11, the company laid out its 2010-2011 product roadmap across all its markets. This year the company focused a lot more on its client-side products, with quite a bit of emphasis devoted to its CPU-GPU “Fusion” chip strategy (which I’ll get to in a moment). For the near term, AMD’s Opteron processors will be carrying the HPC load.

In early 2010, the 45nm “Magny-Cours” processor family will kick off the Opteron 6000 series, using the new “Maranello” platform and G34 socket. Magny-Cours will fulfill the 2P and 4P/8P server markets and is positioned as the “performance” Opteron chip. As such, it is expected to attract the majority of HPC server adoption, although the lower-power 1P and 2P Opteron 4000 series chips may be employed in certain cases. Magny-Cours will come with 8 or 12 cores, doubling up on the previous generation’s Shanghai and Istanbul processors, respectively. Likewise, the memory channels have doubled from 2 to 4, just to keep cores and memory bandwidth in balance. Other enhancements include DDR3 memory support and an Enhanced C1 state (C1E) to reduce power consumption under partial loads.

None of this is news. AMD has been talking up Magny-Cours for awhile now. However, the company did offer some new details about “Interlagos,” the Magny-Cours sequel that’s scheduled for release in 2011. Interlagos will be on the 32nm process node and will come in 12- and 16-core flavors. But it’s more than just core addition enabled by a process shrink. Interlagos will be based on the next-generation “Bulldozer” core architecture, which turns out to be a rather unique design.

According to AMD, each Bulldozer ” module consists of two integer “cores” plus a floating point unit (FPU) that encompasses two 128-bit wide FMACs. Each core and the FPU, has its own instruction scheduler. The FPU itself can either be dedicated to one of the integer cores or shared between the two of them. On the surface it looks as if AMD scrimped on floating point execution in favor of integer execution, but until more details are revealed on how Bulldozer performs on real workloads, it’s probably best to withhold judgement.

 Apparently AMD is counting the integer cores as actual cores, so a 16-core Interlagos processor would be made up of 8 Bulldozer modules. In reality, each module appears as a single core to software, but can carry two threads in SMT fashion. It seems like AMD has needlessly confused the semantics here. It probably would have been better just to call each Bulldozer module a core, with the further explanation that dedicated hardware exists to serve two threads of control simultaneously.

While AMD is going core happy, Intel will be doing its usual tick-tock routine. The 32nm “Westmere” shrink of Nehalem is due out in 2010, with the six-core Westmere EP slated for release in the first half of the year. In 2011, the new “Sandy Bridge” microarchitecture products will show up to meet Bulldozer head on. Trying to battle Intel in the CPU arena is going to be tough for AMD. Intel is about a year ahead of its smaller rival in semiconductor process technology, and has a much larger R&D effort to drive engineering innovation.

Where AMD has the upper hand is its GPU technology, courtesy of its ATI division. That’s why the company’s big focus for the next couple of years will be to fulfill its so-called Fusion strategy of integrating CPU and GPU IP onto the same die. It’s something CPU-centric Intel and, to a lesser extent, GPU-centric NVIDIA are also pursuing, but without the benefit of strong technologies in both areas.

The idea is to create an heterogeneous chip architecture that combines the CPU’s strength in sequential processing with the GPU’s superior data parallel processing capabilities. AMD calls this new architecture an APU (for Accelerated Processing Unit). Applications that mix video, audio, and graphics into more traditional applications will be the main beneficiaries, but that happens to represent a lot of the Web-related content at the heart of computing today. “I think Fusion is going to bring the forward pass to the computing business,” gushed AMD CEO Dirk Meyer at the recent Financial Analyst Day.

Unfortunately for HPC users, for the time being all of AMD’s Fusion efforts are aimed at the client side. The first APU, called Llano, is scheduled to show up in 2011. The GPU performance of these heterogeneous chips won’t rival discrete graphics devices, since die real estate obviously has to be shared with CPU resources. So in the near term at least, AMD will continue to offer standalone GPU products for high-end graphics users and, presumably, HPC users via its FireStream products. The only suggestion that APUs might extend beyond the client space was offered on a slide of AMD’s server roadmap, which had heterogeneous computing appear after 2012.

AMD’s focus on client computing is understandable since that is where most of the growth opportunities exist, albeit at smaller margins than the server space. Even in the latter market, AMD is focusing on mainstream enterprise needs. According to them, their “performance cluster” segment represents only 5 percent of their total server market, giving them little incentive to craft specialty products for the high end. In fact, Intel is more likely to be adventuresome, inasmuch as it can leverage a greater economy of scale than its smaller competitor. The chip maker’s recent announcement of a new collaboration with NEC is an example of the way Intel is pursuing special-purpose HPC.

Despite the dominance of Intel, most HPC system vendors are expected to continue to offer Opteron-based hardware. Certainly AMD’s devotion to upgradeability has made the system vendor’s life a little easier. And in any case, no one wants to return to a single source x86 world.

Cray is sort of a special case. At SC09, the company announced the XT6 (and mid-range XT6m) supercomputer, which will incorporate the Magny-Cours processor, thus fulfilling Cray’s commitment to stick with AMD until at least 2010. Since AMD will introduce the G34-compatible Interlagos in 2011, one can assume at XT6 gear will be socket upgradeable for at least another year. Beyond that, or maybe even before the XT6 has run its course, Cray may exercise its Intel option. When the supercomputer maker brought Intel inside in 2008, certainly it had more in mind than using Xeon silicon for its deskside CX1 system. I would expect to see a high-end supercomputer line with Intel processors introduced sometime within the next couple of years.

The wild card is NVIDIA. If more high performance computing over the next couple of years begins to rely on NVIDIA GPUs (or even AMD/ATI GPUs) to drive performance, the choice of CPU is calculated differently. In this case, cost and power concerns would tend to override performance, placing Opterons on a more even playing field with their Xeon counterparts. And if AMD and NVIDIA could bring themselves to collaborate on some sort of mutually-beneficial Opteron CPU/Fermi GPU arrangement, that might present an interesting challenge to Intel’s preeminence in HPC.

Subscribe to HPCwire's Weekly Update!

Be the most informed person in the room! Stay ahead of the tech trends with industy updates delivered to you every week!

PRACEdays Reflects Europe’s HPC Commitment

May 25, 2017

More than 250 attendees and participants came together for PRACEdays17 in Barcelona last week, part of the European HPC Summit Week 2017, held May 15-19 at t Read more…

By Tiffany Trader

Russian Researchers Claim First Quantum-Safe Blockchain

May 25, 2017

The Russian Quantum Center today announced it has overcome the threat of quantum cryptography by creating the first quantum-safe blockchain, securing cryptocurr Read more…

By Doug Black

Google Debuts TPU v2 and will Add to Google Cloud

May 25, 2017

Not long after stirring attention in the deep learning/AI community by revealing the details of its Tensor Processing Unit (TPU), Google last week announced the Read more…

By John Russell

Nvidia CEO Predicts AI ‘Cambrian Explosion’

May 25, 2017

The processing power and cloud access to developer tools used to train machine-learning models are making artificial intelligence ubiquitous across computing pl Read more…

By George Leopold

HPE Extreme Performance Solutions

Exploring the Three Models of Remote Visualization

The explosion of data and advancement of digital technologies are dramatically changing the way many companies do business. With the help of high performance computing (HPC) solutions and data analytics platforms, manufacturers are developing products faster, healthcare providers are improving patient care, and energy companies are improving planning, exploration, and production. Read more…

PGAS Use will Rise on New H/W Trends, Says Reinders

May 25, 2017

If you have not already tried using PGAS, it is time to consider adding PGAS to the programming techniques you know. Partitioned Global Array Space, commonly kn Read more…

By James Reinders

Exascale Escapes 2018 Budget Axe; Rest of Science Suffers

May 23, 2017

President Trump's proposed $4.1 trillion FY 2018 budget is good for U.S. exascale computing development, but grim for the rest of science and technology spend Read more…

By Tiffany Trader

Hedge Funds (with Supercomputing help) Rank First Among Investors

May 22, 2017

In case you didn’t know, The Quants Run Wall Street Now, or so says a headline in today’s Wall Street Journal. Quant-run hedge funds now control the largest Read more…

By John Russell

IBM, D-Wave Report Quantum Computing Advances

May 18, 2017

IBM said this week it has built and tested a pair of quantum computing processors, including a prototype of a commercial version. That progress follows an an Read more…

By George Leopold

PRACEdays Reflects Europe’s HPC Commitment

May 25, 2017

More than 250 attendees and participants came together for PRACEdays17 in Barcelona last week, part of the European HPC Summit Week 2017, held May 15-19 at t Read more…

By Tiffany Trader

PGAS Use will Rise on New H/W Trends, Says Reinders

May 25, 2017

If you have not already tried using PGAS, it is time to consider adding PGAS to the programming techniques you know. Partitioned Global Array Space, commonly kn Read more…

By James Reinders

Exascale Escapes 2018 Budget Axe; Rest of Science Suffers

May 23, 2017

President Trump's proposed $4.1 trillion FY 2018 budget is good for U.S. exascale computing development, but grim for the rest of science and technology spend Read more…

By Tiffany Trader

Cray Offers Supercomputing as a Service, Targets Biotechs First

May 16, 2017

Leading supercomputer vendor Cray and datacenter/cloud provider the Markley Group today announced plans to jointly deliver supercomputing as a service. The init Read more…

By John Russell

HPE’s Memory-centric The Machine Coming into View, Opens ARMs to 3rd-party Developers

May 16, 2017

Announced three years ago, HPE’s The Machine is said to be the largest R&D program in the venerable company’s history, one that could be progressing tow Read more…

By Doug Black

What’s Up with Hyperion as It Transitions From IDC?

May 15, 2017

If you’re wondering what’s happening with Hyperion Research – formerly the IDC HPC group – apparently you are not alone, says Steve Conway, now senior V Read more…

By John Russell

Nvidia’s Mammoth Volta GPU Aims High for AI, HPC

May 10, 2017

At Nvidia's GPU Technology Conference (GTC17) in San Jose, Calif., this morning, CEO Jensen Huang announced the company's much-anticipated Volta architecture a Read more…

By Tiffany Trader

HPE Launches Servers, Services, and Collaboration at GTC

May 10, 2017

Hewlett Packard Enterprise (HPE) today launched a new liquid cooled GPU-driven Apollo platform based on SGI ICE architecture, a new collaboration with NVIDIA, a Read more…

By John Russell

Quantum Bits: D-Wave and VW; Google Quantum Lab; IBM Expands Access

March 21, 2017

For a technology that’s usually characterized as far off and in a distant galaxy, quantum computing has been steadily picking up steam. Just how close real-wo Read more…

By John Russell

Trump Budget Targets NIH, DOE, and EPA; No Mention of NSF

March 16, 2017

President Trump’s proposed U.S. fiscal 2018 budget issued today sharply cuts science spending while bolstering military spending as he promised during the cam Read more…

By John Russell

Google Pulls Back the Covers on Its First Machine Learning Chip

April 6, 2017

This week Google released a report detailing the design and performance characteristics of the Tensor Processing Unit (TPU), its custom ASIC for the inference Read more…

By Tiffany Trader

HPC Compiler Company PathScale Seeks Life Raft

March 23, 2017

HPCwire has learned that HPC compiler company PathScale has fallen on difficult times and is asking the community for help or actively seeking a buyer for its a Read more…

By Tiffany Trader

CPU-based Visualization Positions for Exascale Supercomputing

March 16, 2017

Since our first formal product releases of OSPRay and OpenSWR libraries in 2016, CPU-based Software Defined Visualization (SDVis) has achieved wide-spread adopt Read more…

By Jim Jeffers, Principal Engineer and Engineering Leader, Intel

Nvidia Responds to Google TPU Benchmarking

April 10, 2017

Last week, Google reported that its custom ASIC Tensor Processing Unit (TPU) was 15-30x faster for inferencing workloads than Nvidia's K80 GPU (see our coverage Read more…

By Tiffany Trader

Nvidia’s Mammoth Volta GPU Aims High for AI, HPC

May 10, 2017

At Nvidia's GPU Technology Conference (GTC17) in San Jose, Calif., this morning, CEO Jensen Huang announced the company's much-anticipated Volta architecture a Read more…

By Tiffany Trader

TSUBAME3.0 Points to Future HPE Pascal-NVLink-OPA Server

February 17, 2017

Since our initial coverage of the TSUBAME3.0 supercomputer yesterday, more details have come to light on this innovative project. Of particular interest is a ne Read more…

By Tiffany Trader

Leading Solution Providers

Facebook Open Sources Caffe2; Nvidia, Intel Rush to Optimize

April 18, 2017

From its F8 developer conference in San Jose, Calif., today, Facebook announced Caffe2, a new open-source, cross-platform framework for deep learning. Caffe2 is Read more…

By Tiffany Trader

Tokyo Tech’s TSUBAME3.0 Will Be First HPE-SGI Super

February 16, 2017

In a press event Friday afternoon local time in Japan, Tokyo Institute of Technology (Tokyo Tech) announced its plans for the TSUBAME3.0 supercomputer, which w Read more…

By Tiffany Trader

Is Liquid Cooling Ready to Go Mainstream?

February 13, 2017

Lost in the frenzy of SC16 was a substantial rise in the number of vendors showing server oriented liquid cooling technologies. Three decades ago liquid cooling Read more…

By Steve Campbell

MIT Mathematician Spins Up 220,000-Core Google Compute Cluster

April 21, 2017

On Thursday, Google announced that MIT math professor and computational number theorist Andrew V. Sutherland had set a record for the largest Google Compute Eng Read more…

By Tiffany Trader

US Supercomputing Leaders Tackle the China Question

March 15, 2017

As China continues to prove its supercomputing mettle via the Top500 list and the forward march of its ambitious plans to stand up an exascale machine by 2020, Read more…

By Tiffany Trader

HPC Technique Propels Deep Learning at Scale

February 21, 2017

Researchers from Baidu's Silicon Valley AI Lab (SVAIL) have adapted a well-known HPC communication technique to boost the speed and scale of their neural networ Read more…

By Tiffany Trader

DOE Supercomputer Achieves Record 45-Qubit Quantum Simulation

April 13, 2017

In order to simulate larger and larger quantum systems and usher in an age of "quantum supremacy," researchers are stretching the limits of today's most advance Read more…

By Tiffany Trader

Knights Landing Processor with Omni-Path Makes Cloud Debut

April 18, 2017

HPC cloud specialist Rescale is partnering with Intel and HPC resource provider R Systems to offer first-ever cloud access to Xeon Phi "Knights Landing" process Read more…

By Tiffany Trader

  • arrow
  • Click Here for More Headlines
  • arrow
Share This