AMD Server Roadmap: Cores, Lots of Them

By Michael Feldman

December 1, 2009

Even though SC09 was something of a coming out party for GPU computing, CPUs are the foundation of high performance computing. The x86 architecture, in particular, continues to dominate the space, with Intel clearly owning the majority of the HPC server market. That dominance will probably remain for the foreseeable future. AMD’s server roadmap over the next couple of years may be able to blunt some of its rival’s momentum, but there are no magic bullets in the company’s arsenal.

At AMD’s Financial Analyst Day on November 11, the company laid out its 2010-2011 product roadmap across all its markets. This year the company focused a lot more on its client-side products, with quite a bit of emphasis devoted to its CPU-GPU “Fusion” chip strategy (which I’ll get to in a moment). For the near term, AMD’s Opteron processors will be carrying the HPC load.

In early 2010, the 45nm “Magny-Cours” processor family will kick off the Opteron 6000 series, using the new “Maranello” platform and G34 socket. Magny-Cours will fulfill the 2P and 4P/8P server markets and is positioned as the “performance” Opteron chip. As such, it is expected to attract the majority of HPC server adoption, although the lower-power 1P and 2P Opteron 4000 series chips may be employed in certain cases. Magny-Cours will come with 8 or 12 cores, doubling up on the previous generation’s Shanghai and Istanbul processors, respectively. Likewise, the memory channels have doubled from 2 to 4, just to keep cores and memory bandwidth in balance. Other enhancements include DDR3 memory support and an Enhanced C1 state (C1E) to reduce power consumption under partial loads.

None of this is news. AMD has been talking up Magny-Cours for awhile now. However, the company did offer some new details about “Interlagos,” the Magny-Cours sequel that’s scheduled for release in 2011. Interlagos will be on the 32nm process node and will come in 12- and 16-core flavors. But it’s more than just core addition enabled by a process shrink. Interlagos will be based on the next-generation “Bulldozer” core architecture, which turns out to be a rather unique design.

According to AMD, each Bulldozer ” module consists of two integer “cores” plus a floating point unit (FPU) that encompasses two 128-bit wide FMACs. Each core and the FPU, has its own instruction scheduler. The FPU itself can either be dedicated to one of the integer cores or shared between the two of them. On the surface it looks as if AMD scrimped on floating point execution in favor of integer execution, but until more details are revealed on how Bulldozer performs on real workloads, it’s probably best to withhold judgement.

 Apparently AMD is counting the integer cores as actual cores, so a 16-core Interlagos processor would be made up of 8 Bulldozer modules. In reality, each module appears as a single core to software, but can carry two threads in SMT fashion. It seems like AMD has needlessly confused the semantics here. It probably would have been better just to call each Bulldozer module a core, with the further explanation that dedicated hardware exists to serve two threads of control simultaneously.

While AMD is going core happy, Intel will be doing its usual tick-tock routine. The 32nm “Westmere” shrink of Nehalem is due out in 2010, with the six-core Westmere EP slated for release in the first half of the year. In 2011, the new “Sandy Bridge” microarchitecture products will show up to meet Bulldozer head on. Trying to battle Intel in the CPU arena is going to be tough for AMD. Intel is about a year ahead of its smaller rival in semiconductor process technology, and has a much larger R&D effort to drive engineering innovation.

Where AMD has the upper hand is its GPU technology, courtesy of its ATI division. That’s why the company’s big focus for the next couple of years will be to fulfill its so-called Fusion strategy of integrating CPU and GPU IP onto the same die. It’s something CPU-centric Intel and, to a lesser extent, GPU-centric NVIDIA are also pursuing, but without the benefit of strong technologies in both areas.

The idea is to create an heterogeneous chip architecture that combines the CPU’s strength in sequential processing with the GPU’s superior data parallel processing capabilities. AMD calls this new architecture an APU (for Accelerated Processing Unit). Applications that mix video, audio, and graphics into more traditional applications will be the main beneficiaries, but that happens to represent a lot of the Web-related content at the heart of computing today. “I think Fusion is going to bring the forward pass to the computing business,” gushed AMD CEO Dirk Meyer at the recent Financial Analyst Day.

Unfortunately for HPC users, for the time being all of AMD’s Fusion efforts are aimed at the client side. The first APU, called Llano, is scheduled to show up in 2011. The GPU performance of these heterogeneous chips won’t rival discrete graphics devices, since die real estate obviously has to be shared with CPU resources. So in the near term at least, AMD will continue to offer standalone GPU products for high-end graphics users and, presumably, HPC users via its FireStream products. The only suggestion that APUs might extend beyond the client space was offered on a slide of AMD’s server roadmap, which had heterogeneous computing appear after 2012.

AMD’s focus on client computing is understandable since that is where most of the growth opportunities exist, albeit at smaller margins than the server space. Even in the latter market, AMD is focusing on mainstream enterprise needs. According to them, their “performance cluster” segment represents only 5 percent of their total server market, giving them little incentive to craft specialty products for the high end. In fact, Intel is more likely to be adventuresome, inasmuch as it can leverage a greater economy of scale than its smaller competitor. The chip maker’s recent announcement of a new collaboration with NEC is an example of the way Intel is pursuing special-purpose HPC.

Despite the dominance of Intel, most HPC system vendors are expected to continue to offer Opteron-based hardware. Certainly AMD’s devotion to upgradeability has made the system vendor’s life a little easier. And in any case, no one wants to return to a single source x86 world.

Cray is sort of a special case. At SC09, the company announced the XT6 (and mid-range XT6m) supercomputer, which will incorporate the Magny-Cours processor, thus fulfilling Cray’s commitment to stick with AMD until at least 2010. Since AMD will introduce the G34-compatible Interlagos in 2011, one can assume at XT6 gear will be socket upgradeable for at least another year. Beyond that, or maybe even before the XT6 has run its course, Cray may exercise its Intel option. When the supercomputer maker brought Intel inside in 2008, certainly it had more in mind than using Xeon silicon for its deskside CX1 system. I would expect to see a high-end supercomputer line with Intel processors introduced sometime within the next couple of years.

The wild card is NVIDIA. If more high performance computing over the next couple of years begins to rely on NVIDIA GPUs (or even AMD/ATI GPUs) to drive performance, the choice of CPU is calculated differently. In this case, cost and power concerns would tend to override performance, placing Opterons on a more even playing field with their Xeon counterparts. And if AMD and NVIDIA could bring themselves to collaborate on some sort of mutually-beneficial Opteron CPU/Fermi GPU arrangement, that might present an interesting challenge to Intel’s preeminence in HPC.

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