Convey Computer President’s Letter

By Nicole Hemsoth

January 19, 2010

The new year is a time for reflection, especially after the turbulent economic environment that marked 2009. In that spirit, HPCwire invited the HPC vendor community to post a new year’s message to our readers. First in the series is Bruce Toal, CEO, president and co-founder for Convey Computer.

Bruce Toal, CEO, President, Co-Founder Convey ComputerDear HPCwire Readers, Customers, and Colleagues,

For a new computer company, 2009 was a year of proving that technical innovation could thrive in the crushingly competitive high-performance computing marketplace. It was our year to acquire more investment capital, more customers, and release the production units of our hybrid-core computer into the marketplace.

Happily, 2009 was a remarkable year for Convey Computer Corporation. As pioneers of hybrid-core computing – a technology designed to help high-performance computers run faster while significantly reducing the energy they use – we closed $24.15 million in Series B financing in July. The round of funding was led by new investor, Braemar Energy Ventures. Series A investors CenterPoint Ventures, Intel Capital, InterWest Partners, Rho Ventures, and Xilinx® also participated. Convey was founded in 2006 and introduced its product, the Convey HC-1™, in November 2008. To date, Convey has received $39.25 million in venture funding.

Our investors were impressed that the Convey team met its milestones, including recently shipping beta and production units to customers who are using the systems in diverse applications such as bioinformatics, data mining, government, and oil and gas. In 2009, Convey announced two new board members with extensive technology experience: Jiong Ma, Ph.D., of Braemar Energy Ventures, and Joshua Ruch of Rho Ventures.

The new round of investment capital meant that we could begin to expand our employee infrastructure. We now have a talented and knowledgeable sales force with proven expertise in the high-performance computing. At the same time, we are building our customer support organization and other company functions to deal with scaling production. Convey also expanded internationally in 2009 when we signed a master reseller agreement with HMK Supercomputing GmbH, whichwill represent Convey Computer in Germany, Switzerland, and Austria.

2010: The Focus Sharpens on Green HPC

“Hybrid-core” is a new market space identified by Convey. A hybrid-core computer improves application performance by combining an x86 core with hardware that implements application-specific instructions. Hybrid-core computing was developed to address what we saw as a perfect storm of technology trends, including:

  1. The need to continue extracting application performance from hardware rather than transferring the burden to programmers
  2. The flattening — or even the decline — in processor clock rates
  3. The need to reduce the cost and the use of energy in our data centers

The energy issue is paramount. Convey’s hybrid-core technology helps customers reduce energy costs associated with high-performance computing because we use FPGAs to power our compute engines. To illustrate: a modern data center today can cost up to $200 million to build, with power and cooling costs making up half of the annual operating costs. Every watt required to power a server nominally requires another watt to cool it. On key HPC workloads, Convey’s HC-1 reduces the number of servers required dramatically. One rack of Convey servers can replace multiple racks of traditional application servers, which means that customers can realize dramatically lower power and cooling costs. One of our customers, for example, realized a 91% reduction in their power and cooling costs. And they’re pretty happy about that!

Reducing power without sacrificing performance is one of the most important issues facing the HPC community over the coming years. The reason Convey will continue to focus on “Green HPC” is simple: data center economics have changed. Energy costs are consuming half the IT operating budget and the cost of floor space is limiting. As we’ve heard from Dr. John Shalf, head of Berkeley Lab’s Science-Driven Systems Architecture team, “Energy efficiency has become a first-order design constraint for future systems. We really don’t see the current path of scaling up conventional hardware as sustainable either in terms of the initial hardware cost or the price of powering such systems over its lifetime.

2010: Where’s the Software?

The same issues that have been driving high-performance computing for the last couple of decades – more performance/less price – will continue into 2010 and beyond. In our view, the performance issue is one part hardware and two parts software.

Our motto at Convey is that the system which is easier to program wins. Convey is an application-specific, low power node. What continues to challenge HPC is that the cost of a programmer for one year is MORE than the cost of acquiring a teraflop (peak performance) system. This is one reason we engineered the Convey system with the hardware and software architecture as an extension to the x86 ecosystem. When presented with a familiar environment, programmers benefit from 100 percent productivity and portability.

Many applications have code that was written long ago – in some case 20 years ago! Many of these applications still have “serial math” as their underpinning. And, before we forget, the universe of programmers capable of writing parallel programs does not seem to have grown any over the years. Now, HPC applications are moving into a different application space called data-intensive computing. The computer centers at Google and Microsoft are substantially larger than what was once thought of as a “classic” HPC center. For example, Microsoft’s Chicago datacenter is 24,000 square meters, houses some one million servers, and is powered by two 300MW substations!

The industry needs to focus more on software productivity, just as we are doing at Convey. Admittedly, it takes time and money to redefine. Meanwhile, extracting performance from our portfolio of HPC applications is easiest for the programmer if the compiler does the work or, at minimum, provides the hints that point the programmer in the right direction. Plus, having a full suite of development tools available to help in the debug and optimization phases of development helps a lot. We believe this is another area where our cache coherent, virtual memory approach really shines – in being able to step through all phases of the program, whether executing on the x86 or on the Convey coprocessor in a single process space.

2010: New Architectures Bring New Opportunities for Discovery in HPC

As the future continues to bring innovation to the HPC marketplace, we will also continue to innovate with hybrid-core technologies.From our perspective, computer architectures will continue to evolve with a greater emphasis on application flexibility.

Fundamental to our mission is to design and develop personalities with instructions that can replace thousands of iterations of standard x86 instruction for a particular application space and with full ANSI standard FORTRAN, C, and C++compiler support.Our technology stimulates the imaginative talents of computer architects and algorithm experts. It is no longer an exercise in using a standard instruction set for optimal performance, but a creative challenge to define a set of instructions that are optimized for a set of applications. The innovation continues as computing experts can “teach” a compiler how to recognize certain program constructs and then invoke these instructions.

We saw this first-hand as we worked in 2009 to develop the new Financial Analytics Personality (FAP). One of the major problems facing developers of financial applications is that the instruction set of commodity processors doesn’t map well to many financial algorithms. Even a simple intrinsic function can take hundreds of instructions and, in many of these applications, that intrinsic function must be executed millions of times.

The Convey solution hard-wires these functions into the HC-1system hardware, which can be many times more efficient than a sequence of commodity instructions. The ANSI standard Convey compilers automatically recognize constructs in the application that can take advantage of the hardware speed-ups. In effect, the developer doesn’t need to know the intricacies of the hardware, yet they reap the performance benefits.

Application-specific instructions are not practical to implement within a microprocessor unless the market that can take advantage of them is sizable, which means large enough to cover the three or five year development costs. Potential application-specific instructions must then compete for processor die space with other uses for transistors (more cache, more cores, etc.). Using a reconfigurable fabric (FPGAs) reduces the design cycle to months instead of years and avoids the huge costs to produce a custom device. And reconfigurable fabric can be used for many application areas, each optimized for that specific mission without competing for device real estate against other uses or areas.

This is one reason why we believe that FPGAs – with the technology’s inherent application flexibility and energy efficiency – represent the best solution for delivering more raw performance, nimble application development, and energy-efficient computing.

In closing, here’s wishing all of us a very exciting 2010.

Best Regards,

Bruce Toal
CEO, President, Co-Founder
Convey Computer Corporation
Convey Computer

Subscribe to HPCwire's Weekly Update!

Be the most informed person in the room! Stay ahead of the tech trends with industy updates delivered to you every week!

Researchers Scale COSMO Climate Code to 4888 GPUs on Piz Daint

October 17, 2017

Effective global climate simulation, sorely needed to anticipate and cope with global warming, has long been computationally challenging. Two of the major obstacles are the needed resolution and prolonged time to compute Read more…

By John Russell

UCSD Web-based Tool Tracking CA Wildfires Generates 1.5M Views

October 16, 2017

Tracking the wildfires raging in northern CA is an unpleasant but necessary part of guiding efforts to fight the fires and safely evacuate affected residents. One such tool – Firemap – is a web-based tool developed b Read more…

By John Russell

Exascale Imperative: New Movie from HPE Makes a Compelling Case

October 13, 2017

Why is pursuing exascale computing so important? In a new video – Hewlett Packard Enterprise: Eighteen Zeros – four HPE executives, a prominent national lab HPC researcher, and HPCwire managing editor Tiffany Trader Read more…

By John Russell

HPE Extreme Performance Solutions

Transforming Genomic Analytics with HPC-Accelerated Insights

Advancements in the field of genomics are revolutionizing our understanding of human biology, rapidly accelerating the discovery and treatment of genetic diseases, and dramatically improving human health. Read more…

Intel Delivers 17-Qubit Quantum Chip to European Research Partner

October 10, 2017

On Tuesday, Intel delivered a 17-qubit superconducting test chip to research partner QuTech, the quantum research institute of Delft University of Technology (TU Delft) in the Netherlands. The announcement marks a major milestone in the 10-year, $50-million collaborative relationship with TU Delft and TNO, the Dutch Organization for Applied Research, to accelerate advancements in quantum computing. Read more…

By Tiffany Trader

Intel Delivers 17-Qubit Quantum Chip to European Research Partner

October 10, 2017

On Tuesday, Intel delivered a 17-qubit superconducting test chip to research partner QuTech, the quantum research institute of Delft University of Technology (TU Delft) in the Netherlands. The announcement marks a major milestone in the 10-year, $50-million collaborative relationship with TU Delft and TNO, the Dutch Organization for Applied Research, to accelerate advancements in quantum computing. Read more…

By Tiffany Trader

Fujitsu Tapped to Build 37-Petaflops ABCI System for AIST

October 10, 2017

Fujitsu announced today it will build the long-planned AI Bridging Cloud Infrastructure (ABCI) which is set to become the fastest supercomputer system in Japan Read more…

By John Russell

HPC Chips – A Veritable Smorgasbord?

October 10, 2017

For the first time since AMD's ill-fated launch of Bulldozer the answer to the question, 'Which CPU will be in my next HPC system?' doesn't have to be 'Whichever variety of Intel Xeon E5 they are selling when we procure'. Read more…

By Dairsie Latimer

Delays, Smoke, Records & Markets – A Candid Conversation with Cray CEO Peter Ungaro

October 5, 2017

Earlier this month, Tom Tabor, publisher of HPCwire and I had a very personal conversation with Cray CEO Peter Ungaro. Cray has been on something of a Cinderell Read more…

By Tiffany Trader & Tom Tabor

Intel Debuts Programmable Acceleration Card

October 5, 2017

With a view toward supporting complex, data-intensive applications, such as AI inference, video streaming analytics, database acceleration and genomics, Intel i Read more…

By Doug Black

OLCF’s 200 Petaflops Summit Machine Still Slated for 2018 Start-up

October 3, 2017

The Department of Energy’s planned 200 petaflops Summit computer, which is currently being installed at Oak Ridge Leadership Computing Facility, is on track t Read more…

By John Russell

US Exascale Program – Some Additional Clarity

September 28, 2017

The last time we left the Department of Energy’s exascale computing program in July, things were looking very positive. Both the U.S. House and Senate had pas Read more…

By Alex R. Larzelere

US Coalesces Plans for First Exascale Supercomputer: Aurora in 2021

September 27, 2017

At the Advanced Scientific Computing Advisory Committee (ASCAC) meeting, in Arlington, Va., yesterday (Sept. 26), it was revealed that the "Aurora" supercompute Read more…

By Tiffany Trader

How ‘Knights Mill’ Gets Its Deep Learning Flops

June 22, 2017

Intel, the subject of much speculation regarding the delayed, rewritten or potentially canceled “Aurora” contract (the Argonne Lab part of the CORAL “ Read more…

By Tiffany Trader

Reinders: “AVX-512 May Be a Hidden Gem” in Intel Xeon Scalable Processors

June 29, 2017

Imagine if we could use vector processing on something other than just floating point problems.  Today, GPUs and CPUs work tirelessly to accelerate algorithms Read more…

By James Reinders

NERSC Scales Scientific Deep Learning to 15 Petaflops

August 28, 2017

A collaborative effort between Intel, NERSC and Stanford has delivered the first 15-petaflops deep learning software running on HPC platforms and is, according Read more…

By Rob Farber

Oracle Layoffs Reportedly Hit SPARC and Solaris Hard

September 7, 2017

Oracle’s latest layoffs have many wondering if this is the end of the line for the SPARC processor and Solaris OS development. As reported by multiple sources Read more…

By John Russell

US Coalesces Plans for First Exascale Supercomputer: Aurora in 2021

September 27, 2017

At the Advanced Scientific Computing Advisory Committee (ASCAC) meeting, in Arlington, Va., yesterday (Sept. 26), it was revealed that the "Aurora" supercompute Read more…

By Tiffany Trader

Google Releases Deeplearn.js to Further Democratize Machine Learning

August 17, 2017

Spreading the use of machine learning tools is one of the goals of Google’s PAIR (People + AI Research) initiative, which was introduced in early July. Last w Read more…

By John Russell

GlobalFoundries Puts Wind in AMD’s Sails with 12nm FinFET

September 24, 2017

From its annual tech conference last week (Sept. 20), where GlobalFoundries welcomed more than 600 semiconductor professionals (reaching the Santa Clara venue Read more…

By Tiffany Trader

Graphcore Readies Launch of 16nm Colossus-IPU Chip

July 20, 2017

A second $30 million funding round for U.K. AI chip developer Graphcore sets up the company to go to market with its “intelligent processing unit” (IPU) in Read more…

By Tiffany Trader

Leading Solution Providers

Amazon Debuts New AMD-based GPU Instances for Graphics Acceleration

September 12, 2017

Last week Amazon Web Services (AWS) streaming service, AppStream 2.0, introduced a new GPU instance called Graphics Design intended to accelerate graphics. The Read more…

By John Russell

Nvidia Responds to Google TPU Benchmarking

April 10, 2017

Nvidia highlights strengths of its newest GPU silicon in response to Google's report on the performance and energy advantages of its custom tensor processor. Read more…

By Tiffany Trader

EU Funds 20 Million Euro ARM+FPGA Exascale Project

September 7, 2017

At the Barcelona Supercomputer Centre on Wednesday (Sept. 6), 16 partners gathered to launch the EuroEXA project, which invests €20 million over three-and-a-half years into exascale-focused research and development. Led by the Horizon 2020 program, EuroEXA picks up the banner of a triad of partner projects — ExaNeSt, EcoScale and ExaNoDe — building on their work... Read more…

By Tiffany Trader

Cray Moves to Acquire the Seagate ClusterStor Line

July 28, 2017

This week Cray announced that it is picking up Seagate's ClusterStor HPC storage array business for an undisclosed sum. "In short we're effectively transitioning the bulk of the ClusterStor product line to Cray," said CEO Peter Ungaro. Read more…

By Tiffany Trader

Delays, Smoke, Records & Markets – A Candid Conversation with Cray CEO Peter Ungaro

October 5, 2017

Earlier this month, Tom Tabor, publisher of HPCwire and I had a very personal conversation with Cray CEO Peter Ungaro. Cray has been on something of a Cinderell Read more…

By Tiffany Trader & Tom Tabor

Intel Launches Software Tools to Ease FPGA Programming

September 5, 2017

Field Programmable Gate Arrays (FPGAs) have a reputation for being difficult to program, requiring expertise in specialty languages, like Verilog or VHDL. Easin Read more…

By Tiffany Trader

IBM Advances Web-based Quantum Programming

September 5, 2017

IBM Research is pairing its Jupyter-based Data Science Experience notebook environment with its cloud-based quantum computer, IBM Q, in hopes of encouraging a new class of entrepreneurial user to solve intractable problems that even exceed the capabilities of the best AI systems. Read more…

By Alex Woodie

Intel, NERSC and University Partners Launch New Big Data Center

August 17, 2017

A collaboration between the Department of Energy’s National Energy Research Scientific Computing Center (NERSC), Intel and five Intel Parallel Computing Cente Read more…

By Linda Barney

  • arrow
  • Click Here for More Headlines
  • arrow
Share This