Chips Ahoy: Vendors Show Off Their Latest Silicon

By Michael Feldman

February 9, 2010

Chipmakers converged on San Francisco this week to talk up their newest semiconductor products at the International Solid State Circuits Conference (ISSCC). Of particular interest to the HPC crowd are Intel’s Westmere EP and “Tukwila” Itanium 9300, and IBM’s POWER7.

In truth, the new quad-core Tukwila is not likely to have much of an impact on HPC. SGI is the only real hope that this seventh-generation Itanium will see any supercomputing action. Under the new Rackable leadership, SGI has left a lot to the imagination as far as possible Itanium-equipped Altix systems. SGI previewed its Nehalem EX-based Altix UV servers last November, and implied there would be Itanium-based versions of UV at some point, but has yet to talk about any products.

It might be relatively straightforward for SGI to build a Tukwila-based UV. The Itanium 9300 processors share platform components with Nehalem EX, including the QuickPath Interconnect (QPI), the Scalable Memory Interconnect, the 7500 Memory Buffer, and the I/O hub. Because of this commonality, Intel says manufacturers could use a common node controller for both Nehalem EX and Itanium 9300 systems. Given that SGI has already built a UV hub node controller for its shared memory systems, the company may have an easy path to an Itanium UV product.

But in general, the new Itanium is being targeted for mission-critical systems in the enterprise. These are typically high-end servers that can’t tolerate any downtime, and are especially valued for high-volume transactional applications in industries like energy, health care, telecom and manufacturing. According to Intel, Itanium’s penetration into this market is growing, reaching $5 billion in 2008 (estimated to be $4 billion in 2009 due to the recession). The chipmaker also points to a growing roster of OEMs that will be offering Itanium 9300-based machines, including Bull, HP, NEC, Hitachi, and new Itanium converts, Supermicro and China-based Inspur.

By contrast, the Westmere EP is guaranteed to see plenty of HPC action. The new Xeon chip is the 32 nm shrink of the highly popular quad-core Nehalem EP for dual-socket servers. Intel’s x86 franchise is represented by nearly 400 of the top 500 HPC systems in the world, a proportion that is likely even higher in the overall HPC server space. Intel hasn’t locked down a date when the new Xeons will start shipping, although the plan is to get them on the street in the first half of 2010.

The new features of Westmere can be summed up thusly: six cores and 12 MB of cache. That represents a 50 percent increase compared to Nehalem EP. The smaller transistor geometries mean Intel engineers were able to cram over a billion transistors on the die, which is apparently enough silicon real estate to add the two additional cores and 4 MB more cache. A quad-core variant of the Westmere EP will also be available at some point.

Even with the additional cores and cache, there was some spare silicon left over to add support for special AES (Advanced Encryption Standard) instructions, which, as its name implies, is aimed at speeding up encryption/decryption software. The engineers also came up with some additional power gating smarts to Westmere, allowing the processor to shut down processor components other than the actual processor cores (like the L3 cache, QPI interfaces, and memory controller), although it’s not clear if this feature will be available in the Xeon server parts.

Since Intel did its big architectural reset last year with the Nehalem redesign, all the goodies from that generation — integrated memory controller, QPI interface, “Hyper-Threading,” etc. — will be carried over to the Westmere processor. That should guarantee socket compatibility with the chipsets and DDR3 memory used in the Nehalem EP machines. Whether or not this means HPC users will be swapping out Nehalem EP parts with their Westmere counterparts remains to be seen.

Finally, IBM officially launched its much-anticipated POWER7 processor this week. The new chips are aimed at high-end enterprise and supercomputing servers, and also support large-scale transaction processing and analytics workloads across all application domains. In conjunction with the chip launch, four POWER7-equipped server systems were also announced: the Power 780, 770, 755, and 750. “These are the most flexible systems ever made by any company in the world,” boasted Ross Mauri, general manager of IBM Power Systems.

Hyperbole aside, of the three chips mentioned in this article, the POWER7 is the definite performance leader. In a clear departure from the POWER6 design, which delivered high clock speeds (up to 5 GHz), dual-core processors and off-chip L3 cache, the POWER7 retreats a bit on the clock speed (3 to 4 GHz), but comes with up to 8 cores and 32 MB of on-chip L3. Compare this to Tukwila at 4 cores and 24 MB of L3, and Westmere EP at 6 cores and 12 MB. Note that both the Intel chips execute up to two threads per core simultaneously, while the POWER7 can go up to four threads. The comparison with Westmere is especially interesting since IBM managed to get two more cores, two more threads per core, and 20 more megabytes of L3 cache using roughly the same number of transistors: 1.2 billion for POWER7 versus 1.17 billion for Westmere EP.

So how did Big Blue manage to make the most of its die real estate? The biggest contributor was IBM’s decision to go with embedded DRAM (eDRAM) for the on-chip L3 cache. Compared to traditional SRAM-based L3, which uses six transistors per bit, eDRAM uses just one transistor plus one capacitor. According to IBM, if they relied on SRAM technology, the equivalent chip would have consumed around 2 billion transistors and used significantly more power.

Given the x86 juggernaut in high performance computing, it’s not clear how much of the market POWER7 will grab. It was interesting that IBM’s press release included a podcast with Cindy Farach-Carson, associate vice provost for Research at Rice University and a professor of biochemistry and cell biology, who was introduced as an early user of POWER7 technology. Her work involves analyzing cancer genomic data to find the micro-RNA sequence responsible for turning slow growing cancers into more invasive and deadly variants.

The Power 755 server is the POWER7 product IBM has built for the HPC market. A 755 box contains four POWER7 processors, and since each core can execute up to four threads, a single node has the capability to run 128 threads simultaneously. Presumably this is the server (or a version thereof) that will go into the multi-petaflop Blue Waters supercomputer destined for the University of Illinois at Urbana-Champaign/NCSA sometime in 2011. In the interim, IBM is hoping other HPC users latch on to POWER7. If not, IBM will be happy to sell you a Westmere EP cluster.

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