Chips Ahoy: Vendors Show Off Their Latest Silicon

By Michael Feldman

February 9, 2010

Chipmakers converged on San Francisco this week to talk up their newest semiconductor products at the International Solid State Circuits Conference (ISSCC). Of particular interest to the HPC crowd are Intel’s Westmere EP and “Tukwila” Itanium 9300, and IBM’s POWER7.

In truth, the new quad-core Tukwila is not likely to have much of an impact on HPC. SGI is the only real hope that this seventh-generation Itanium will see any supercomputing action. Under the new Rackable leadership, SGI has left a lot to the imagination as far as possible Itanium-equipped Altix systems. SGI previewed its Nehalem EX-based Altix UV servers last November, and implied there would be Itanium-based versions of UV at some point, but has yet to talk about any products.

It might be relatively straightforward for SGI to build a Tukwila-based UV. The Itanium 9300 processors share platform components with Nehalem EX, including the QuickPath Interconnect (QPI), the Scalable Memory Interconnect, the 7500 Memory Buffer, and the I/O hub. Because of this commonality, Intel says manufacturers could use a common node controller for both Nehalem EX and Itanium 9300 systems. Given that SGI has already built a UV hub node controller for its shared memory systems, the company may have an easy path to an Itanium UV product.

But in general, the new Itanium is being targeted for mission-critical systems in the enterprise. These are typically high-end servers that can’t tolerate any downtime, and are especially valued for high-volume transactional applications in industries like energy, health care, telecom and manufacturing. According to Intel, Itanium’s penetration into this market is growing, reaching $5 billion in 2008 (estimated to be $4 billion in 2009 due to the recession). The chipmaker also points to a growing roster of OEMs that will be offering Itanium 9300-based machines, including Bull, HP, NEC, Hitachi, and new Itanium converts, Supermicro and China-based Inspur.

By contrast, the Westmere EP is guaranteed to see plenty of HPC action. The new Xeon chip is the 32 nm shrink of the highly popular quad-core Nehalem EP for dual-socket servers. Intel’s x86 franchise is represented by nearly 400 of the top 500 HPC systems in the world, a proportion that is likely even higher in the overall HPC server space. Intel hasn’t locked down a date when the new Xeons will start shipping, although the plan is to get them on the street in the first half of 2010.

The new features of Westmere can be summed up thusly: six cores and 12 MB of cache. That represents a 50 percent increase compared to Nehalem EP. The smaller transistor geometries mean Intel engineers were able to cram over a billion transistors on the die, which is apparently enough silicon real estate to add the two additional cores and 4 MB more cache. A quad-core variant of the Westmere EP will also be available at some point.

Even with the additional cores and cache, there was some spare silicon left over to add support for special AES (Advanced Encryption Standard) instructions, which, as its name implies, is aimed at speeding up encryption/decryption software. The engineers also came up with some additional power gating smarts to Westmere, allowing the processor to shut down processor components other than the actual processor cores (like the L3 cache, QPI interfaces, and memory controller), although it’s not clear if this feature will be available in the Xeon server parts.

Since Intel did its big architectural reset last year with the Nehalem redesign, all the goodies from that generation — integrated memory controller, QPI interface, “Hyper-Threading,” etc. — will be carried over to the Westmere processor. That should guarantee socket compatibility with the chipsets and DDR3 memory used in the Nehalem EP machines. Whether or not this means HPC users will be swapping out Nehalem EP parts with their Westmere counterparts remains to be seen.

Finally, IBM officially launched its much-anticipated POWER7 processor this week. The new chips are aimed at high-end enterprise and supercomputing servers, and also support large-scale transaction processing and analytics workloads across all application domains. In conjunction with the chip launch, four POWER7-equipped server systems were also announced: the Power 780, 770, 755, and 750. “These are the most flexible systems ever made by any company in the world,” boasted Ross Mauri, general manager of IBM Power Systems.

Hyperbole aside, of the three chips mentioned in this article, the POWER7 is the definite performance leader. In a clear departure from the POWER6 design, which delivered high clock speeds (up to 5 GHz), dual-core processors and off-chip L3 cache, the POWER7 retreats a bit on the clock speed (3 to 4 GHz), but comes with up to 8 cores and 32 MB of on-chip L3. Compare this to Tukwila at 4 cores and 24 MB of L3, and Westmere EP at 6 cores and 12 MB. Note that both the Intel chips execute up to two threads per core simultaneously, while the POWER7 can go up to four threads. The comparison with Westmere is especially interesting since IBM managed to get two more cores, two more threads per core, and 20 more megabytes of L3 cache using roughly the same number of transistors: 1.2 billion for POWER7 versus 1.17 billion for Westmere EP.

So how did Big Blue manage to make the most of its die real estate? The biggest contributor was IBM’s decision to go with embedded DRAM (eDRAM) for the on-chip L3 cache. Compared to traditional SRAM-based L3, which uses six transistors per bit, eDRAM uses just one transistor plus one capacitor. According to IBM, if they relied on SRAM technology, the equivalent chip would have consumed around 2 billion transistors and used significantly more power.

Given the x86 juggernaut in high performance computing, it’s not clear how much of the market POWER7 will grab. It was interesting that IBM’s press release included a podcast with Cindy Farach-Carson, associate vice provost for Research at Rice University and a professor of biochemistry and cell biology, who was introduced as an early user of POWER7 technology. Her work involves analyzing cancer genomic data to find the micro-RNA sequence responsible for turning slow growing cancers into more invasive and deadly variants.

The Power 755 server is the POWER7 product IBM has built for the HPC market. A 755 box contains four POWER7 processors, and since each core can execute up to four threads, a single node has the capability to run 128 threads simultaneously. Presumably this is the server (or a version thereof) that will go into the multi-petaflop Blue Waters supercomputer destined for the University of Illinois at Urbana-Champaign/NCSA sometime in 2011. In the interim, IBM is hoping other HPC users latch on to POWER7. If not, IBM will be happy to sell you a Westmere EP cluster.

Subscribe to HPCwire's Weekly Update!

Be the most informed person in the room! Stay ahead of the tech trends with industy updates delivered to you every week!

Hedge Funds (with Supercomputing help) Rank First Among Investors

May 22, 2017

In case you didn’t know, The Quants Run Wall Street Now, or so says a headline in today’s Wall Street Journal. Quant-run hedge funds now control the largest Read more…

By John Russell

IBM, D-Wave Report Quantum Computing Advances

May 18, 2017

IBM said this week it has built and tested a pair of quantum computing processors, including a prototype of a commercial version. That progress follows an an Read more…

By George Leopold

PRACEdays 2017 Wraps Up in Barcelona

May 18, 2017

Barcelona has been absolutely lovely; the weather, the food, the people. I am, sadly, finishing my last day at PRACEdays 2017 with two sessions: an in-depth loo Read more…

By Kim McMahon

US, Europe, Japan Deepen Research Computing Partnership

May 18, 2017

On May 17, 2017, a ceremony was held during the PRACEdays 2017 conference in Barcelona to announce the memorandum of understanding (MOU) between PRACE in Europe Read more…

By Tiffany Trader

HPE Extreme Performance Solutions

Exploring the Three Models of Remote Visualization

The explosion of data and advancement of digital technologies are dramatically changing the way many companies do business. With the help of high performance computing (HPC) solutions and data analytics platforms, manufacturers are developing products faster, healthcare providers are improving patient care, and energy companies are improving planning, exploration, and production. Read more…

NSF, IARPA, and SRC Push into “Semiconductor Synthetic Biology” Computing

May 18, 2017

Research into how biological systems might be fashioned into computational technology has a long history with various DNA-based computing approaches explored. N Read more…

By John Russell

DOE’s HPC4Mfg Leads to Paper Manufacturing Improvement

May 17, 2017

Papermaking ranks third behind only petroleum refining and chemical production in terms of energy consumption. Recently, simulations made possible by the U.S. D Read more…

By John Russell

PRACEdays 2017: The start of a beautiful week in Barcelona

May 17, 2017

Touching down in Barcelona on Saturday afternoon, it was warm, sunny, and oh so Spanish. I was greeted at my hotel with a glass of Cava to sip and treated to a Read more…

By Kim McMahon

NSF Issues $60M RFP for “Towards a Leadership-Class” System

May 16, 2017

In case you missed it, the National Science Foundation issued the request for proposals (RFP) for the next ‘Towards a Leadership-Class Computing Facility – Read more…

By John Russell

Cray Offers Supercomputing as a Service, Targets Biotechs First

May 16, 2017

Leading supercomputer vendor Cray and datacenter/cloud provider the Markley Group today announced plans to jointly deliver supercomputing as a service. The init Read more…

By John Russell

HPE’s Memory-centric The Machine Coming into View, Opens ARMs to 3rd-party Developers

May 16, 2017

Announced three years ago, HPE’s The Machine is said to be the largest R&D program in the venerable company’s history, one that could be progressing tow Read more…

By Doug Black

What’s Up with Hyperion as It Transitions From IDC?

May 15, 2017

If you’re wondering what’s happening with Hyperion Research – formerly the IDC HPC group – apparently you are not alone, says Steve Conway, now senior V Read more…

By John Russell

Nvidia’s Mammoth Volta GPU Aims High for AI, HPC

May 10, 2017

At Nvidia's GPU Technology Conference (GTC17) in San Jose, Calif., this morning, CEO Jensen Huang announced the company's much-anticipated Volta architecture a Read more…

By Tiffany Trader

HPE Launches Servers, Services, and Collaboration at GTC

May 10, 2017

Hewlett Packard Enterprise (HPE) today launched a new liquid cooled GPU-driven Apollo platform based on SGI ICE architecture, a new collaboration with NVIDIA, a Read more…

By John Russell

IBM PowerAI Tools Aim to Ease Deep Learning Data Prep, Shorten Training 

May 10, 2017

A new set of GPU-powered AI software announced by IBM today brings automation to many of the tedious, time consuming and complex aspects of AI project on-rampin Read more…

By Doug Black

Bright Computing 8.0 Adds Azure, Expands Machine Learning Support

May 9, 2017

Bright Computing, long a prominent provider of cluster management tools for HPC, today released version 8.0 of Bright Cluster Manager and Bright OpenStack. The Read more…

By John Russell

Microsoft Azure Will Debut Pascal GPU Instances This Year

May 8, 2017

As Nvidia's GPU Technology Conference gets underway in San Jose, Calif., Microsoft today revealed plans to add Pascal-generation GPU horsepower to its Azure clo Read more…

By Tiffany Trader

Quantum Bits: D-Wave and VW; Google Quantum Lab; IBM Expands Access

March 21, 2017

For a technology that’s usually characterized as far off and in a distant galaxy, quantum computing has been steadily picking up steam. Just how close real-wo Read more…

By John Russell

Google Pulls Back the Covers on Its First Machine Learning Chip

April 6, 2017

This week Google released a report detailing the design and performance characteristics of the Tensor Processing Unit (TPU), its custom ASIC for the inference Read more…

By Tiffany Trader

Trump Budget Targets NIH, DOE, and EPA; No Mention of NSF

March 16, 2017

President Trump’s proposed U.S. fiscal 2018 budget issued today sharply cuts science spending while bolstering military spending as he promised during the cam Read more…

By John Russell

HPC Compiler Company PathScale Seeks Life Raft

March 23, 2017

HPCwire has learned that HPC compiler company PathScale has fallen on difficult times and is asking the community for help or actively seeking a buyer for its a Read more…

By Tiffany Trader

Nvidia Responds to Google TPU Benchmarking

April 10, 2017

Last week, Google reported that its custom ASIC Tensor Processing Unit (TPU) was 15-30x faster for inferencing workloads than Nvidia's K80 GPU (see our coverage Read more…

By Tiffany Trader

CPU-based Visualization Positions for Exascale Supercomputing

March 16, 2017

Since our first formal product releases of OSPRay and OpenSWR libraries in 2016, CPU-based Software Defined Visualization (SDVis) has achieved wide-spread adopt Read more…

By Jim Jeffers, Principal Engineer and Engineering Leader, Intel

TSUBAME3.0 Points to Future HPE Pascal-NVLink-OPA Server

February 17, 2017

Since our initial coverage of the TSUBAME3.0 supercomputer yesterday, more details have come to light on this innovative project. Of particular interest is a ne Read more…

By Tiffany Trader

Facebook Open Sources Caffe2; Nvidia, Intel Rush to Optimize

April 18, 2017

From its F8 developer conference in San Jose, Calif., today, Facebook announced Caffe2, a new open-source, cross-platform framework for deep learning. Caffe2 is Read more…

By Tiffany Trader

Leading Solution Providers

Nvidia’s Mammoth Volta GPU Aims High for AI, HPC

May 10, 2017

At Nvidia's GPU Technology Conference (GTC17) in San Jose, Calif., this morning, CEO Jensen Huang announced the company's much-anticipated Volta architecture a Read more…

By Tiffany Trader

Tokyo Tech’s TSUBAME3.0 Will Be First HPE-SGI Super

February 16, 2017

In a press event Friday afternoon local time in Japan, Tokyo Institute of Technology (Tokyo Tech) announced its plans for the TSUBAME3.0 supercomputer, which w Read more…

By Tiffany Trader

Is Liquid Cooling Ready to Go Mainstream?

February 13, 2017

Lost in the frenzy of SC16 was a substantial rise in the number of vendors showing server oriented liquid cooling technologies. Three decades ago liquid cooling Read more…

By Steve Campbell

MIT Mathematician Spins Up 220,000-Core Google Compute Cluster

April 21, 2017

On Thursday, Google announced that MIT math professor and computational number theorist Andrew V. Sutherland had set a record for the largest Google Compute Eng Read more…

By Tiffany Trader

IBM Wants to be “Red Hat” of Deep Learning

January 26, 2017

IBM today announced the addition of TensorFlow and Chainer deep learning frameworks to its PowerAI suite of deep learning tools, which already includes popular Read more…

By John Russell

HPC Technique Propels Deep Learning at Scale

February 21, 2017

Researchers from Baidu's Silicon Valley AI Lab (SVAIL) have adapted a well-known HPC communication technique to boost the speed and scale of their neural networ Read more…

By Tiffany Trader

US Supercomputing Leaders Tackle the China Question

March 15, 2017

As China continues to prove its supercomputing mettle via the Top500 list and the forward march of its ambitious plans to stand up an exascale machine by 2020, Read more…

By Tiffany Trader

DOE Supercomputer Achieves Record 45-Qubit Quantum Simulation

April 13, 2017

In order to simulate larger and larger quantum systems and usher in an age of "quantum supremacy," researchers are stretching the limits of today's most advance Read more…

By Tiffany Trader

  • arrow
  • Click Here for More Headlines
  • arrow
Share This