Chips Ahoy: Vendors Show Off Their Latest Silicon

By Michael Feldman

February 9, 2010

Chipmakers converged on San Francisco this week to talk up their newest semiconductor products at the International Solid State Circuits Conference (ISSCC). Of particular interest to the HPC crowd are Intel’s Westmere EP and “Tukwila” Itanium 9300, and IBM’s POWER7.

In truth, the new quad-core Tukwila is not likely to have much of an impact on HPC. SGI is the only real hope that this seventh-generation Itanium will see any supercomputing action. Under the new Rackable leadership, SGI has left a lot to the imagination as far as possible Itanium-equipped Altix systems. SGI previewed its Nehalem EX-based Altix UV servers last November, and implied there would be Itanium-based versions of UV at some point, but has yet to talk about any products.

It might be relatively straightforward for SGI to build a Tukwila-based UV. The Itanium 9300 processors share platform components with Nehalem EX, including the QuickPath Interconnect (QPI), the Scalable Memory Interconnect, the 7500 Memory Buffer, and the I/O hub. Because of this commonality, Intel says manufacturers could use a common node controller for both Nehalem EX and Itanium 9300 systems. Given that SGI has already built a UV hub node controller for its shared memory systems, the company may have an easy path to an Itanium UV product.

But in general, the new Itanium is being targeted for mission-critical systems in the enterprise. These are typically high-end servers that can’t tolerate any downtime, and are especially valued for high-volume transactional applications in industries like energy, health care, telecom and manufacturing. According to Intel, Itanium’s penetration into this market is growing, reaching $5 billion in 2008 (estimated to be $4 billion in 2009 due to the recession). The chipmaker also points to a growing roster of OEMs that will be offering Itanium 9300-based machines, including Bull, HP, NEC, Hitachi, and new Itanium converts, Supermicro and China-based Inspur.

By contrast, the Westmere EP is guaranteed to see plenty of HPC action. The new Xeon chip is the 32 nm shrink of the highly popular quad-core Nehalem EP for dual-socket servers. Intel’s x86 franchise is represented by nearly 400 of the top 500 HPC systems in the world, a proportion that is likely even higher in the overall HPC server space. Intel hasn’t locked down a date when the new Xeons will start shipping, although the plan is to get them on the street in the first half of 2010.

The new features of Westmere can be summed up thusly: six cores and 12 MB of cache. That represents a 50 percent increase compared to Nehalem EP. The smaller transistor geometries mean Intel engineers were able to cram over a billion transistors on the die, which is apparently enough silicon real estate to add the two additional cores and 4 MB more cache. A quad-core variant of the Westmere EP will also be available at some point.

Even with the additional cores and cache, there was some spare silicon left over to add support for special AES (Advanced Encryption Standard) instructions, which, as its name implies, is aimed at speeding up encryption/decryption software. The engineers also came up with some additional power gating smarts to Westmere, allowing the processor to shut down processor components other than the actual processor cores (like the L3 cache, QPI interfaces, and memory controller), although it’s not clear if this feature will be available in the Xeon server parts.

Since Intel did its big architectural reset last year with the Nehalem redesign, all the goodies from that generation — integrated memory controller, QPI interface, “Hyper-Threading,” etc. — will be carried over to the Westmere processor. That should guarantee socket compatibility with the chipsets and DDR3 memory used in the Nehalem EP machines. Whether or not this means HPC users will be swapping out Nehalem EP parts with their Westmere counterparts remains to be seen.

Finally, IBM officially launched its much-anticipated POWER7 processor this week. The new chips are aimed at high-end enterprise and supercomputing servers, and also support large-scale transaction processing and analytics workloads across all application domains. In conjunction with the chip launch, four POWER7-equipped server systems were also announced: the Power 780, 770, 755, and 750. “These are the most flexible systems ever made by any company in the world,” boasted Ross Mauri, general manager of IBM Power Systems.

Hyperbole aside, of the three chips mentioned in this article, the POWER7 is the definite performance leader. In a clear departure from the POWER6 design, which delivered high clock speeds (up to 5 GHz), dual-core processors and off-chip L3 cache, the POWER7 retreats a bit on the clock speed (3 to 4 GHz), but comes with up to 8 cores and 32 MB of on-chip L3. Compare this to Tukwila at 4 cores and 24 MB of L3, and Westmere EP at 6 cores and 12 MB. Note that both the Intel chips execute up to two threads per core simultaneously, while the POWER7 can go up to four threads. The comparison with Westmere is especially interesting since IBM managed to get two more cores, two more threads per core, and 20 more megabytes of L3 cache using roughly the same number of transistors: 1.2 billion for POWER7 versus 1.17 billion for Westmere EP.

So how did Big Blue manage to make the most of its die real estate? The biggest contributor was IBM’s decision to go with embedded DRAM (eDRAM) for the on-chip L3 cache. Compared to traditional SRAM-based L3, which uses six transistors per bit, eDRAM uses just one transistor plus one capacitor. According to IBM, if they relied on SRAM technology, the equivalent chip would have consumed around 2 billion transistors and used significantly more power.

Given the x86 juggernaut in high performance computing, it’s not clear how much of the market POWER7 will grab. It was interesting that IBM’s press release included a podcast with Cindy Farach-Carson, associate vice provost for Research at Rice University and a professor of biochemistry and cell biology, who was introduced as an early user of POWER7 technology. Her work involves analyzing cancer genomic data to find the micro-RNA sequence responsible for turning slow growing cancers into more invasive and deadly variants.

The Power 755 server is the POWER7 product IBM has built for the HPC market. A 755 box contains four POWER7 processors, and since each core can execute up to four threads, a single node has the capability to run 128 threads simultaneously. Presumably this is the server (or a version thereof) that will go into the multi-petaflop Blue Waters supercomputer destined for the University of Illinois at Urbana-Champaign/NCSA sometime in 2011. In the interim, IBM is hoping other HPC users latch on to POWER7. If not, IBM will be happy to sell you a Westmere EP cluster.

Subscribe to HPCwire's Weekly Update!

Be the most informed person in the room! Stay ahead of the tech trends with industy updates delivered to you every week!

Tech Giants Outline Battle Plans for Future HPC Market

August 21, 2017

Four companies engaged in a cage fight for leadership in the emerging HPC market of the 2020s are, despite deep differences in some areas, in violent agreement on at least one thing: the power consumption and latency pen Read more…

By Doug Black

Geospatial Data Research Leverages GPUs

August 17, 2017

MapD Technologies, the GPU-accelerated database specialist, said it is working with university researchers on leveraging graphics processors to advance geospatial analytics. The San Francisco-based company is collabor Read more…

By George Leopold

Intel, NERSC and University Partners Launch New Big Data Center

August 17, 2017

A collaboration between the Department of Energy’s National Energy Research Scientific Computing Center (NERSC), Intel and five Intel Parallel Computing Centers (IPCCs) has resulted in a new Big Data Center (BDC) that Read more…

By Linda Barney

HPE Extreme Performance Solutions

Leveraging Deep Learning for Fraud Detection

Advancements in computing technologies and the expanding use of e-commerce platforms have dramatically increased the risk of fraud for financial services companies and their customers. Read more…

Google Releases Deeplearn.js to Further Democratize Machine Learning

August 17, 2017

Spreading the use of machine learning tools is one of the goals of Google’s PAIR (People + AI Research) initiative, which was introduced in early July. Last week the cloud giant released deeplearn.js as part of that in Read more…

By John Russell

Tech Giants Outline Battle Plans for Future HPC Market

August 21, 2017

Four companies engaged in a cage fight for leadership in the emerging HPC market of the 2020s are, despite deep differences in some areas, in violent agreement Read more…

By Doug Black

Microsoft Bolsters Azure With Cloud HPC Deal

August 15, 2017

Microsoft has acquired cloud computing software vendor Cycle Computing in a move designed to bring orchestration tools along with high-end computing access capabilities to the cloud. Terms of the acquisition were not disclosed. Read more…

By George Leopold

HPE Ships Supercomputer to Space Station, Final Destination Mars

August 14, 2017

With a manned mission to Mars on the horizon, the demand for space-based supercomputing is at hand. Today HPE and NASA sent the first off-the-shelf HPC system i Read more…

By Tiffany Trader

AMD EPYC Video Takes Aim at Intel’s Broadwell

August 14, 2017

Let the benchmarking begin. Last week, AMD posted a YouTube video in which one of its EPYC-based systems outperformed a ‘comparable’ Intel Broadwell-based s Read more…

By John Russell

Deep Learning Thrives in Cancer Moonshot

August 8, 2017

The U.S. War on Cancer, certainly a worthy cause, is a collection of programs stretching back more than 40 years and abiding under many banners. The latest is t Read more…

By John Russell

IBM Raises the Bar for Distributed Deep Learning

August 8, 2017

IBM is announcing today an enhancement to its PowerAI software platform aimed at facilitating the practical scaling of AI models on today’s fastest GPUs. Scal Read more…

By Tiffany Trader

IBM Storage Breakthrough Paves Way for 330TB Tape Cartridges

August 3, 2017

IBM announced yesterday a new record for magnetic tape storage that it says will keep tape storage density on a Moore's law-like path far into the next decade. Read more…

By Tiffany Trader

AMD Stuffs a Petaflops of Machine Intelligence into 20-Node Rack

August 1, 2017

With its Radeon “Vega” Instinct datacenter GPUs and EPYC “Naples” server chips entering the market this summer, AMD has positioned itself for a two-head Read more…

By Tiffany Trader

How ‘Knights Mill’ Gets Its Deep Learning Flops

June 22, 2017

Intel, the subject of much speculation regarding the delayed, rewritten or potentially canceled “Aurora” contract (the Argonne Lab part of the CORAL “ Read more…

By Tiffany Trader

Nvidia’s Mammoth Volta GPU Aims High for AI, HPC

May 10, 2017

At Nvidia's GPU Technology Conference (GTC17) in San Jose, Calif., this morning, CEO Jensen Huang announced the company's much-anticipated Volta architecture a Read more…

By Tiffany Trader

Reinders: “AVX-512 May Be a Hidden Gem” in Intel Xeon Scalable Processors

June 29, 2017

Imagine if we could use vector processing on something other than just floating point problems.  Today, GPUs and CPUs work tirelessly to accelerate algorithms Read more…

By James Reinders

Quantum Bits: D-Wave and VW; Google Quantum Lab; IBM Expands Access

March 21, 2017

For a technology that’s usually characterized as far off and in a distant galaxy, quantum computing has been steadily picking up steam. Just how close real-wo Read more…

By John Russell

Russian Researchers Claim First Quantum-Safe Blockchain

May 25, 2017

The Russian Quantum Center today announced it has overcome the threat of quantum cryptography by creating the first quantum-safe blockchain, securing cryptocurrencies like Bitcoin, along with classified government communications and other sensitive digital transfers. Read more…

By Doug Black

Nvidia Responds to Google TPU Benchmarking

April 10, 2017

Nvidia highlights strengths of its newest GPU silicon in response to Google's report on the performance and energy advantages of its custom tensor processor. Read more…

By Tiffany Trader

Groq This: New AI Chips to Give GPUs a Run for Deep Learning Money

April 24, 2017

CPUs and GPUs, move over. Thanks to recent revelations surrounding Google’s new Tensor Processing Unit (TPU), the computing world appears to be on the cusp of Read more…

By Alex Woodie

HPC Compiler Company PathScale Seeks Life Raft

March 23, 2017

HPCwire has learned that HPC compiler company PathScale has fallen on difficult times and is asking the community for help or actively seeking a buyer for its a Read more…

By Tiffany Trader

Leading Solution Providers

Trump Budget Targets NIH, DOE, and EPA; No Mention of NSF

March 16, 2017

President Trump’s proposed U.S. fiscal 2018 budget issued today sharply cuts science spending while bolstering military spending as he promised during the cam Read more…

By John Russell

CPU-based Visualization Positions for Exascale Supercomputing

March 16, 2017

In this contributed perspective piece, Intel’s Jim Jeffers makes the case that CPU-based visualization is now widely adopted and as such is no longer a contrarian view, but is rather an exascale requirement. Read more…

By Jim Jeffers, Principal Engineer and Engineering Leader, Intel

Google Debuts TPU v2 and will Add to Google Cloud

May 25, 2017

Not long after stirring attention in the deep learning/AI community by revealing the details of its Tensor Processing Unit (TPU), Google last week announced the Read more…

By John Russell

Six Exascale PathForward Vendors Selected; DoE Providing $258M

June 15, 2017

The much-anticipated PathForward awards for hardware R&D in support of the Exascale Computing Project were announced today with six vendors selected – AMD Read more…

By John Russell

Top500 Results: Latest List Trends and What’s in Store

June 19, 2017

Greetings from Frankfurt and the 2017 International Supercomputing Conference where the latest Top500 list has just been revealed. Although there were no major Read more…

By Tiffany Trader

IBM Clears Path to 5nm with Silicon Nanosheets

June 5, 2017

Two years since announcing the industry’s first 7nm node test chip, IBM and its research alliance partners GlobalFoundries and Samsung have developed a proces Read more…

By Tiffany Trader

Messina Update: The US Path to Exascale in 16 Slides

April 26, 2017

Paul Messina, director of the U.S. Exascale Computing Project, provided a wide-ranging review of ECP’s evolving plans last week at the HPC User Forum. Read more…

By John Russell

Graphcore Readies Launch of 16nm Colossus-IPU Chip

July 20, 2017

A second $30 million funding round for U.K. AI chip developer Graphcore sets up the company to go to market with its “intelligent processing unit” (IPU) in Read more…

By Tiffany Trader

  • arrow
  • Click Here for More Headlines
  • arrow
Share This